^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PIC32 Integrated Serial Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Microchip Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-pic32/pic32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "pic32_uart.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* UART name and device definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PIC32_DEV_NAME "pic32-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PIC32_MAX_UARTS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PIC32_SDEV_NAME "ttyPIC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* pic32_sport pointer for console use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* wait for tx empty, otherwise chars will be lost or corrupted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline int pic32_enable_clock(struct pic32_sport *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret = clk_prepare_enable(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) sport->ref_clk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void pic32_disable_clock(struct pic32_sport *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) sport->ref_clk--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clk_disable_unprepare(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* serial core request to check if uart tx buffer is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned int pic32_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* serial core request to set UART outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* set loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PIC32_UART_MODE_LPBK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PIC32_UART_MODE_LPBK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* get the state of CTS input pin for this port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static unsigned int get_cts_state(struct pic32_sport *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* read and invert UxCTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (gpio_is_valid(sport->cts_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return !gpio_get_value(sport->cts_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* serial core request to return the state of misc UART input pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int mctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!sport->hw_flow_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else if (get_cts_state(sport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* DSR and CD are not supported in PIC32, so return 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * RI is not supported in PIC32, so return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mctrl |= TIOCM_CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mctrl |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* stop tx and start tx are not called in pairs, therefore a flag indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * the status of irq to control the irq-depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (en && !tx_irq_enabled(sport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enable_irq(sport->irq_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tx_irq_enabled(sport) = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else if (!en && tx_irq_enabled(sport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* use disable_irq_nosync() and not disable_irq() to avoid self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * imposed deadlock by not waiting for irq handler to end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * since this callback is called from interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) disable_irq_nosync(sport->irq_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tx_irq_enabled(sport) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* serial core request to disable tx ASAP (used for flow control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void pic32_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* wait for tx empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pic32_wait_deplete_txbuf(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PIC32_UART_STA_UTXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pic32_uart_irqtxen(sport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* serial core request to (re)enable tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void pic32_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pic32_uart_irqtxen(sport, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PIC32_UART_STA_UTXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* serial core request to stop rx, called before port shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void pic32_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* disable rx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) disable_irq(sport->irq_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* receiver Enable bit OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PIC32_UART_STA_URXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* serial core request to start/stop emitting break char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PIC32_UART_STA_UTXBRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PIC32_UART_STA_UTXBRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* get port type in string format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const char *pic32_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* read all chars in rx fifo and send them to core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void pic32_uart_do_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct tty_port *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int max_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* limit number of char read in interrupt, should not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * higher than fifo size anyway since we're much faster than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * serial port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) max_count = PIC32_UART_RX_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tty = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 sta_reg, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* get overrun/fifo empty information from status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* fifo reset is required to clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PIC32_UART_STA_OERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tty_insert_flip_char(tty, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Can at least one more character can be read? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!(sta_reg & PIC32_UART_STA_URXDA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* read the character and increment the rx counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) c = pic32_uart_readl(sport, PIC32_UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) c &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (sta_reg & PIC32_UART_STA_FERR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* do stats first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (sta_reg & PIC32_UART_STA_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (sta_reg & PIC32_UART_STA_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* update flag wrt read_status_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sta_reg &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (sta_reg & PIC32_UART_STA_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (sta_reg & PIC32_UART_STA_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (uart_handle_sysrq_char(port, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if ((sta_reg & port->ignore_status_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tty_insert_flip_char(tty, c, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } while (--max_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tty_flip_buffer_push(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* fill tx fifo with chars to send, stop when fifo is about to be full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * or when all chars have been sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void pic32_uart_do_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pic32_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto txq_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* keep stuffing chars into uart tx buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * 1) until uart fifo is full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * 2) until the circ buffer is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * (all chars have been sent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * 3) until the max count is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * (prevents lingering here for too long in certain cases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) while (!(PIC32_UART_STA_UTXBF &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pic32_uart_readl(sport, PIC32_UART_STA))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int c = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pic32_uart_writel(sport, PIC32_UART_TX, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (--max_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto txq_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) txq_empty:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pic32_uart_irqtxen(sport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* RX interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pic32_uart_do_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* TX interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pic32_uart_do_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* FAULT interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* do nothing: pic32_uart_do_rx() handles faults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* enable rx & tx operation on uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void pic32_uart_en_and_unmask(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PIC32_UART_MODE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* disable rx & tx operation on uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void pic32_uart_dsbl_and_mask(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* wait for tx empty, otherwise chars will be lost or corrupted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pic32_wait_deplete_txbuf(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PIC32_UART_MODE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* serial core request to initialize uart and start rx operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int pic32_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = pic32_enable_clock(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto out_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* clear status and mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pic32_uart_writel(sport, PIC32_UART_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pic32_uart_writel(sport, PIC32_UART_STA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* disable uart and mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pic32_uart_dsbl_and_mask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* set default baud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Each UART of a PIC32 has three interrupts therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * we setup driver to register the 3 irqs for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * For each irq request_irq() is called with interrupt disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * And the irq is enabled as soon as we are ready to handle them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tx_irq_enabled(sport) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pic32_uart_type(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) sport->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!sport->irq_fault_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(port->dev, "%s: kasprintf err!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) goto out_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sport->irqflags_fault, sport->irq_fault_name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __func__, sport->irq_fault, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pic32_uart_type(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto out_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pic32_uart_type(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sport->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!sport->irq_rx_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(port->dev, "%s: kasprintf err!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto out_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) sport->irqflags_rx, sport->irq_rx_name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __func__, sport->irq_rx, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pic32_uart_type(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) goto out_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pic32_uart_type(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) sport->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!sport->irq_tx_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(port->dev, "%s: kasprintf err!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto out_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sport->irqflags_tx, sport->irq_tx_name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __func__, sport->irq_tx, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pic32_uart_type(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto out_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* set rx interrupt on first receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* set interrupt on empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PIC32_UART_STA_UTXISEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* enable all interrupts and eanable uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pic32_uart_en_and_unmask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enable_irq(sport->irq_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) out_t:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) kfree(sport->irq_tx_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) free_irq(sport->irq_tx, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) out_r:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) kfree(sport->irq_rx_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) free_irq(sport->irq_rx, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) out_f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) kfree(sport->irq_fault_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) free_irq(sport->irq_fault, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) out_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* serial core request to flush & disable uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void pic32_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* disable uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pic32_uart_dsbl_and_mask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pic32_disable_clock(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* free all 3 interrupts for this UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) free_irq(sport->irq_fault, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) free_irq(sport->irq_tx, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) free_irq(sport->irq_rx, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* serial core request to change current uart setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void pic32_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* disable uart and mask all interrupts while changing speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pic32_uart_dsbl_and_mask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* stop bit options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (new->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PIC32_UART_MODE_STSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PIC32_UART_MODE_STSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* parity options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (new->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (new->c_cflag & PARODD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PIC32_UART_MODE_PDSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PIC32_UART_MODE_PDSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PIC32_UART_MODE_PDSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PIC32_UART_MODE_PDSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PIC32_UART_MODE_PDSEL1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PIC32_UART_MODE_PDSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* if hw flow ctrl, then the pins must be specified in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* enable hardware flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PIC32_UART_MODE_UEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PIC32_UART_MODE_UEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PIC32_UART_MODE_RTSMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* disable hardware flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PIC32_UART_MODE_UEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PIC32_UART_MODE_UEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PIC32_UART_MODE_RTSMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Always 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) new->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Mark/Space parity is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) new->c_cflag &= ~CMSPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* update baud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) quot = uart_get_divisor(port, baud) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pic32_uart_writel(sport, PIC32_UART_BRG, quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (tty_termios_baud_rate(new))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) tty_termios_encode_baud_rate(new, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* enable uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pic32_uart_en_and_unmask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* serial core request to claim uart iomem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int pic32_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct resource *res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (unlikely(!res_mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!request_mem_region(port->mapbase, resource_size(res_mem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "pic32_uart_mem"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) port->membase = devm_ioremap(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) resource_size(res_mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!port->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(port->dev, "Unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) release_mem_region(port->mapbase, resource_size(res_mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* serial core request to release uart iomem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void pic32_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct resource *res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int res_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (unlikely(!res_mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) res_size = resource_size(res_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) release_mem_region(port->mapbase, res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* serial core request to do any port required auto-configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void pic32_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (pic32_uart_request_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) port->type = PORT_PIC32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* serial core request to check that port information in serinfo are suitable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int pic32_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct serial_struct *serinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (port->type != PORT_PIC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (port->irq != serinfo->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (port->iotype != serinfo->io_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (port->mapbase != (unsigned long)serinfo->iomem_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* serial core callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct uart_ops pic32_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .tx_empty = pic32_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .get_mctrl = pic32_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .set_mctrl = pic32_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .start_tx = pic32_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .stop_tx = pic32_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .stop_rx = pic32_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .break_ctl = pic32_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .startup = pic32_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .shutdown = pic32_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .set_termios = pic32_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .type = pic32_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .release_port = pic32_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .request_port = pic32_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .config_port = pic32_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .verify_port = pic32_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #ifdef CONFIG_SERIAL_PIC32_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* output given char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void pic32_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* wait for tx empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pic32_wait_deplete_txbuf(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* console core request to output given string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static void pic32_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct pic32_sport *sport = pic32_sports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct uart_port *port = pic32_get_port(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* call uart helper to deal with \r\n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) uart_console_write(port, s, count, pic32_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* console core request to setup given console, find matching uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * port and setup it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int pic32_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct pic32_sport *sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct uart_port *port = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) sport = pic32_sports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) port = pic32_get_port(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = pic32_enable_clock(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static struct uart_driver pic32_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static struct console pic32_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .name = PIC32_SDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .write = pic32_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .setup = pic32_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .data = &pic32_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define PIC32_SCONSOLE (&pic32_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int __init pic32_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) register_console(&pic32_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) console_initcall(pic32_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Late console initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int __init pic32_late_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (!(pic32_console.flags & CON_ENABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) register_console(&pic32_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) core_initcall(pic32_late_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define PIC32_SCONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static struct uart_driver pic32_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .driver_name = PIC32_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .dev_name = PIC32_SDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .nr = PIC32_MAX_UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .cons = PIC32_SCONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int pic32_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct pic32_sport *sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int uart_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct resource *res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) uart_idx = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!res_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) sport->idx = uart_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) sport->irq_fault = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) sport->irqflags_fault = IRQF_NO_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) sport->irq_rx = irq_of_parse_and_map(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) sport->irqflags_rx = IRQF_NO_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) sport->irq_tx = irq_of_parse_and_map(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) sport->irqflags_tx = IRQF_NO_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) sport->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) sport->cts_gpio = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) sport->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Hardware flow control: gpios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * !Note: Basically, CTS is needed for reading the status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) sport->hw_flow_ctrl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (gpio_is_valid(sport->cts_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) sport->hw_flow_ctrl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret = devm_gpio_request(sport->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) sport->cts_gpio, "CTS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "error requesting CTS GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = gpio_direction_input(sport->cts_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_err(&pdev->dev, "error setting CTS GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pic32_sports[uart_idx] = sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) port = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) memset(port, 0, sizeof(*port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) port->mapbase = res_mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) port->ops = &pic32_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) port->uartclk = clk_get_rate(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) port->line = uart_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = uart_add_one_port(&pic32_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_err(port->dev, "%s: uart add port error!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #ifdef CONFIG_SERIAL_PIC32_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (uart_console(port) && (pic32_console.flags & CON_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* The peripheral clock has been enabled by console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * so disable it till the port is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pic32_disable_clock(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) platform_set_drvdata(pdev, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __func__, uart_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* automatic unroll of sport and gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int pic32_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct uart_port *port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct pic32_sport *sport = to_pic32_sport(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) uart_remove_one_port(&pic32_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pic32_disable_clock(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pic32_sports[sport->idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* automatic unroll of sport and gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static const struct of_device_id pic32_serial_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { .compatible = "microchip,pic32mzda-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static struct platform_driver pic32_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .probe = pic32_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .remove = pic32_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .name = PIC32_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .of_match_table = of_match_ptr(pic32_serial_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int __init pic32_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = uart_register_driver(&pic32_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pr_err("failed to register %s:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) pic32_uart_driver.driver_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret = platform_driver_register(&pic32_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pr_err("fail to register pic32 uart\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) uart_unregister_driver(&pic32_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) arch_initcall(pic32_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void __exit pic32_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #ifdef CONFIG_SERIAL_PIC32_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unregister_console(&pic32_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) platform_driver_unregister(&pic32_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) uart_unregister_driver(&pic32_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) module_exit(pic32_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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