^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/nmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pch_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PCH_UART_HANDLED_RX_INT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PCH_UART_HANDLED_TX_INT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PCH_UART_HANDLED_MS_INT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PCH_UART_HANDLED_LS_INT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCH_UART_DRIVER_DEVICE "ttyPCH"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Set the max number of UART port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Intel EG20T PCH: 4 port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * LAPIS Semiconductor ML7213 IOH: 3 port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * LAPIS Semiconductor ML7223 IOH: 2 port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCH_UART_NR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCH_UART_RBR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCH_UART_THR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCH_UART_IER_ERBFI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCH_UART_IER_ETBEI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCH_UART_IER_ELSI 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCH_UART_IER_EDSSI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCH_UART_IIR_IP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCH_UART_IIR_IID 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCH_UART_IIR_MSI 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCH_UART_IIR_TRI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCH_UART_IIR_RRI 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCH_UART_IIR_REI 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCH_UART_IIR_TOI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCH_UART_IIR_FIFO256 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCH_UART_IIR_FE 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCH_UART_FCR_FIFOE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCH_UART_FCR_RFR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCH_UART_FCR_TFR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCH_UART_FCR_DMS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCH_UART_FCR_FIFO256 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCH_UART_FCR_RFTL 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCH_UART_FCR_RFTL1 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCH_UART_FCR_RFTL64 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCH_UART_FCR_RFTL128 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCH_UART_FCR_RFTL224 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCH_UART_FCR_RFTL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCH_UART_LCR_WLS 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCH_UART_LCR_STB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCH_UART_LCR_PEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCH_UART_LCR_EPS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCH_UART_LCR_SP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCH_UART_LCR_SB 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCH_UART_LCR_DLAB 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCH_UART_LCR_NP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PCH_UART_LCR_SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCH_UART_LCR_5BIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCH_UART_LCR_6BIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCH_UART_LCR_7BIT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCH_UART_LCR_8BIT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCH_UART_MCR_DTR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCH_UART_MCR_RTS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCH_UART_MCR_OUT 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCH_UART_MCR_LOOP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCH_UART_MCR_AFE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCH_UART_LSR_DR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCH_UART_LSR_ERR (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCH_UART_MSR_DCTS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCH_UART_MSR_DDSR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCH_UART_MSR_TERI 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCH_UART_MSR_DDCD 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCH_UART_MSR_CTS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCH_UART_MSR_DSR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCH_UART_MSR_RI 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCH_UART_MSR_DCD 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCH_UART_DLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCH_UART_DLM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCH_UART_BRCSR 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCH_UART_HAL_STB1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PCH_UART_HAL_CLR_RX_FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCH_UART_HAL_DMA_MODE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCH_UART_HAL_FIFO_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PCH_UART_FCR_FIFO256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct pch_uart_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct eg20t_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) resource_size_t mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int start_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int start_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int tx_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int trigger_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct pch_uart_buffer rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int dmsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct dma_async_tx_descriptor *desc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct dma_async_tx_descriptor *desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pch_dma_slave param_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct pch_dma_slave param_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct scatterlist *sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int orig_nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct scatterlist sg_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int tx_dma_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void *rx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dma_addr_t rx_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IRQ_NAME_SIZE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) char irq_name[IRQ_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* protect the eg20t_port private structure and io access to membase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * struct pch_uart_driver_data - private data structure for UART-DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @port_type: The type of UART port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @line_no: UART port line number (0, 1, 2...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct pch_uart_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int line_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enum pch_uart_num_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pch_et20t_uart0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pch_et20t_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pch_et20t_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pch_et20t_uart3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pch_ml7213_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pch_ml7213_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pch_ml7213_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pch_ml7223_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pch_ml7223_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pch_ml7831_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pch_ml7831_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct pch_uart_driver_data drv_dat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static unsigned int default_baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static unsigned int user_uartclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const int trigger_level_256[4] = { 1, 64, 128, 224 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const int trigger_level_64[4] = { 1, 16, 32, 56 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const int trigger_level_16[4] = { 1, 4, 8, 14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const int trigger_level_1[4] = { 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PCH_REGS_BUFSIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static ssize_t port_show_regs(struct file *file, char __user *user_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct eg20t_port *priv = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned char lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "PCH EG20T port[%d] regs:\n", priv->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "=================================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "BRCSR: \t0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ioread8(priv->membase + PCH_UART_BRCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) lcr = ioread8(priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iowrite8(lcr, priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (len > PCH_REGS_BUFSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) len = PCH_REGS_BUFSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct file_operations port_regs_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .read = port_show_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .llseek = default_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct dmi_system_id pch_uart_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ident = "CM-iTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (void *)CMITC_UARTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .ident = "FRI2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (void *)FRI2_64_UARTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .ident = "Fish River Island II",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (void *)FRI2_48_UARTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .ident = "COMe-mTT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (void *)NTC1_UARTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .ident = "nanoETXexpress-TT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (void *)NTC1_UARTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .ident = "MinnowBoard",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (void *)MINNOW_UARTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Return UART clock, checking for board specific clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static unsigned int pch_uart_get_uartclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const struct dmi_system_id *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (user_uartclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return user_uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) d = dmi_first_match(pch_uart_dmi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return (unsigned long)d->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return DEFAULT_UARTCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 ier = ioread8(priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ier |= flag & PCH_UART_IER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) iowrite8(ier, priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 ier = ioread8(priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ier &= ~(flag & PCH_UART_IER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) iowrite8(ier, priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int parity, unsigned int bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int stb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int dll, dlm, lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (div < 0 || USHRT_MAX <= div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dll = (unsigned int)div & 0x00FFU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dlm = ((unsigned int)div >> 8) & 0x00FFU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (bits & ~PCH_UART_LCR_WLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (stb & ~PCH_UART_LCR_STB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) lcr = parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) lcr |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) lcr |= stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) __func__, baud, div, lcr, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) iowrite8(dll, priv->membase + PCH_UART_DLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iowrite8(dlm, priv->membase + PCH_UART_DLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) iowrite8(lcr, priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __func__, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) priv->membase + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) iowrite8(priv->fcr, priv->membase + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned int fifo_size, unsigned int trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (dmamode & ~PCH_UART_FCR_DMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __func__, dmamode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __func__, fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (trigger & ~PCH_UART_FCR_RFTL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __func__, trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) switch (priv->fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) priv->trigger_level =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) priv->trigger_level =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) priv->trigger_level =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) priv->trigger_level =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) fcr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) priv->membase + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) iowrite8(fcr, priv->membase + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) priv->fcr = fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned int msr = ioread8(priv->membase + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) priv->dmsr = msr & PCH_UART_MSR_DELTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return (u8)msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void pch_uart_hal_write(struct eg20t_port *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const unsigned char *buf, int tx_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int thr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < tx_size;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) thr = buf[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) iowrite8(thr, priv->membase + PCH_UART_THR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int rx_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 rbr, lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) lsr = ioread8(priv->membase + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) lsr = ioread8(priv->membase + UART_LSR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rbr = ioread8(priv->membase + PCH_UART_RBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (lsr & UART_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (uart_handle_sysrq_char(port, rbr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) buf[i++] = rbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ioread8(priv->membase + UART_IIR) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ioread8(priv->membase + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) lcr = ioread8(priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) lcr |= PCH_UART_LCR_SB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) lcr &= ~PCH_UART_LCR_SB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) iowrite8(lcr, priv->membase + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tty_insert_flip_string(tport, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __func__, port->x_char, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) buf[0] = port->x_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int dma_push_rx(struct eg20t_port *priv, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int room;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) room = tty_buffer_request_room(tport, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (room < size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) size - room);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!room)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) port->icount.rx += room;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return room;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void pch_free_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (priv->chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dma_release_channel(priv->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) priv->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (priv->chan_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dma_release_channel(priv->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) priv->chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (priv->rx_buf_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) priv->rx_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) priv->rx_buf_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) priv->rx_buf_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static bool filter(struct dma_chan *chan, void *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct pch_dma_slave *param = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) chan->device->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) chan->private = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void pch_request_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct pci_dev *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct pch_dma_slave *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct eg20t_port *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Get DMA's dev information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dma_dev = pci_get_slot(priv->pdev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Set Tx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) param = &priv->param_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) param->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) param->tx_reg = port->mapbase + UART_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) chan = dma_request_channel(mask, filter, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) priv->chan_tx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Set Rx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) param = &priv->param_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) param->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) param->rx_reg = port->mapbase + UART_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) chan = dma_request_channel(mask, filter, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dma_release_channel(priv->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) priv->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Get Consistent memory for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) &priv->rx_buf_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) priv->chan_rx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void pch_dma_rx_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct eg20t_port *priv = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) count = dma_push_rx(priv, priv->trigger_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) async_tx_ack(priv->desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PCH_UART_HAL_RX_ERR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void pch_dma_tx_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct eg20t_port *priv = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct scatterlist *sg = priv->sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) for (i = 0; i < priv->nent; i++, sg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) xmit->tail += sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) port->icount.tx += sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) xmit->tail &= UART_XMIT_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) async_tx_ack(priv->desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) priv->tx_dma_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) priv->nent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) priv->orig_nent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) kfree(priv->sg_tx_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int pop_tx(struct eg20t_port *priv, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) goto pop_tx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int cnt_to_end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int sz = min(size - count, cnt_to_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) count += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) } while (!uart_circ_empty(xmit) && count < size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pop_tx_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) count, size - count, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int handle_rx_to(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct pch_uart_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!priv->start_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PCH_UART_HAL_RX_ERR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) buf = &priv->rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = push_rx(priv, buf->buf, rx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } while (rx_size == buf->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return PCH_UART_HANDLED_RX_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int handle_rx(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return handle_rx_to(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int dma_handle_rx(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) sg = &priv->sg_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) sg_dma_len(sg) = priv->trigger_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) sg_dma_address(sg) = priv->rx_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) desc = dmaengine_prep_slave_sg(priv->chan_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) sg, 1, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) priv->desc_rx = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) desc->callback = pch_dma_rx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) desc->callback_param = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) desc->tx_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dma_async_issue_pending(priv->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return PCH_UART_HANDLED_RX_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static unsigned int handle_tx(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int tx_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!priv->start_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __func__, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) priv->tx_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) fifo_size = max(priv->fifo_size, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) tx_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (pop_tx_x(priv, xmit->buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pch_uart_hal_write(priv, xmit->buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) tx_empty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) fifo_size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) size = min(xmit->head - xmit->tail, fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) size = fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) tx_size = pop_tx(priv, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (tx_size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) port->icount.tx += tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) tx_empty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) priv->tx_empty = tx_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (tx_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return PCH_UART_HANDLED_TX_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static unsigned int dma_handle_tx(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!priv->start_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) __func__, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) priv->tx_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (priv->tx_dma_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __func__, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) priv->tx_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) fifo_size = max(priv->fifo_size, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (pop_tx_x(priv, xmit->buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pch_uart_hal_write(priv, xmit->buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) fifo_size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) xmit->tail, UART_XMIT_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (!bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (bytes > fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) num = bytes / fifo_size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) size = fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rem = bytes % fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) size = bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rem = bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) __func__, num, size, rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) priv->tx_dma_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!priv->sg_tx_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) sg = priv->sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) for (i = 0; i < num; i++, sg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (i == (num - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) sg_set_page(sg, virt_to_page(xmit->buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) rem, fifo_size * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) sg_set_page(sg, virt_to_page(xmit->buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) size, fifo_size * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) sg = priv->sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!nent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) priv->orig_nent = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) priv->nent = nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) for (i = 0; i < nent; i++, sg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) fifo_size * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) sg_dma_address(sg) = (sg_dma_address(sg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ~(UART_XMIT_SIZE - 1)) + sg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (i == (nent - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) sg_dma_len(sg) = rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) sg_dma_len(sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) desc = dmaengine_prep_slave_sg(priv->chan_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) priv->desc_tx = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) desc->callback = pch_dma_tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) desc->callback_param = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) desc->tx_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dma_async_issue_pending(priv->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return PCH_UART_HANDLED_TX_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct uart_port *port = &priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct tty_struct *tty = tty_port_tty_get(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) char *error_msg[5] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (lsr & PCH_UART_LSR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) error_msg[i++] = "Error data in FIFO\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (lsr & UART_LSR_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) error_msg[i++] = " Framing Error\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (lsr & UART_LSR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) error_msg[i++] = " Parity Error\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (lsr & UART_LSR_OE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) error_msg[i++] = " Overrun Error\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (tty == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) for (i = 0; error_msg[i] != NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_err(&priv->pdev->dev, error_msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct eg20t_port *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) unsigned int handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) u8 lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) unsigned char iid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int next = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u8 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) while (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) iid = pch_uart_hal_get_iid(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (iid & PCH_UART_IIR_IP) /* No Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) switch (iid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) case PCH_UART_IID_RLS: /* Receiver Line Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) lsr = pch_uart_hal_get_line_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) UART_LSR_PE | UART_LSR_OE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pch_uart_err_ir(priv, lsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = PCH_UART_HANDLED_RX_ERR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret = PCH_UART_HANDLED_LS_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case PCH_UART_IID_RDR: /* Received Data Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (priv->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pch_uart_hal_disable_interrupt(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PCH_UART_HAL_RX_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PCH_UART_HAL_RX_ERR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = dma_handle_rx(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) pch_uart_hal_enable_interrupt(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PCH_UART_HAL_RX_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PCH_UART_HAL_RX_ERR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = handle_rx(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case PCH_UART_IID_RDR_TO: /* Received Data Ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) (FIFO Timeout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = handle_rx_to(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case PCH_UART_IID_THRE: /* Transmitter Holding Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (priv->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = dma_handle_tx(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = handle_tx(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case PCH_UART_IID_MS: /* Modem Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) msr = pch_uart_hal_get_modem(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) next = 0; /* MS ir prioirty is the lowest. So, MS ir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) means final interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if ((msr & UART_MSR_ANY_DELTA) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret |= PCH_UART_HANDLED_MS_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) default: /* Never junp to this label */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) iid, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) handled |= (unsigned int)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* This function tests whether the transmitter fifo and shifter for the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) described by 'port' is empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static unsigned int pch_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (priv->tx_empty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* Returns the current state of modem control inputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static unsigned int pch_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u8 modem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) unsigned int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) modem = pch_uart_hal_get_modem(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (modem & UART_MSR_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (modem & UART_MSR_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret |= TIOCM_RNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (modem & UART_MSR_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (modem & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 mcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (mctrl & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mcr |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (mctrl & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mcr |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) mcr |= UART_MCR_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (priv->mcr & UART_MCR_AFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mcr |= UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) iowrite8(mcr, priv->membase + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static void pch_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) priv->start_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) priv->tx_dma_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static void pch_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (priv->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (priv->tx_dma_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) priv->start_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static void pch_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) priv->start_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PCH_UART_HAL_RX_ERR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* Enable the modem status interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static void pch_uart_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Control the transmission of a break signal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static void pch_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) pch_uart_hal_set_break(priv, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* Grab any interrupt resources and initialise any low level driver state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static int pch_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int trigger_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) priv->tx_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (port->uartclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) priv->uartclk = port->uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) port->uartclk = priv->uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret = pch_uart_hal_set_line(priv, default_baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PCH_UART_HAL_STB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) switch (priv->fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) fifo_size = PCH_UART_HAL_FIFO256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) fifo_size = PCH_UART_HAL_FIFO64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) fifo_size = PCH_UART_HAL_FIFO16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) fifo_size = PCH_UART_HAL_FIFO_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) switch (priv->trigger) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) case PCH_UART_HAL_TRIGGER1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) trigger_level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case PCH_UART_HAL_TRIGGER_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) trigger_level = priv->fifo_size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) case PCH_UART_HAL_TRIGGER_M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) trigger_level = priv->fifo_size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) case PCH_UART_HAL_TRIGGER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) trigger_level = priv->fifo_size - (priv->fifo_size / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) priv->trigger_level = trigger_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) fifo_size, priv->trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) priv->irq_name, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (priv->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) pch_request_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) priv->start_rx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PCH_UART_HAL_RX_ERR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) uart_update_timeout(port, CS8, default_baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static void pch_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dev_err(priv->port.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pch_free_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) free_irq(priv->port.irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* Change the port parameters, including word length, parity, stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) *bits. Update read_status_mask and ignore_status_mask to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *the types of events we are interested in receiving. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static void pch_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct ktermios *termios, struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) unsigned int baud, parity, bits, stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) bits = PCH_UART_HAL_5BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) bits = PCH_UART_HAL_6BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) bits = PCH_UART_HAL_7BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) default: /* CS8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) bits = PCH_UART_HAL_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) stb = PCH_UART_HAL_STB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) stb = PCH_UART_HAL_STB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) parity = PCH_UART_HAL_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) parity = PCH_UART_HAL_PARITY_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) parity = PCH_UART_HAL_PARITY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* Only UART0 has auto hardware flow function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) priv->mcr |= UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) priv->mcr &= ~UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (rtn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Don't rewrite B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const char *pch_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return KBUILD_MODNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static void pch_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pci_iounmap(priv->pdev, priv->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) pci_release_regions(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static int pch_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) membase = pci_iomap(priv->pdev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (!membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pci_release_regions(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) priv->membase = port->membase = membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static void pch_uart_config_port(struct uart_port *port, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (type & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) port->type = priv->port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) pch_uart_request_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static int pch_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct serial_struct *serinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) priv = container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (serinfo->flags & UPF_LOW_LATENCY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev_info(priv->port.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) "PCH UART : Use PIO Mode (without DMA)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) priv->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) serinfo->flags &= ~UPF_LOW_LATENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #ifndef CONFIG_PCH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!priv->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pch_request_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (priv->chan_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) priv->use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_info(priv->port.dev, "PCH UART: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) priv->use_dma ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) "Use DMA Mode" : "No DMA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * Wait for transmitter & holding register to empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static void wait_for_xmitr(struct eg20t_port *up, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) unsigned int status, tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Wait up to 10ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) status = ioread8(up->membase + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if ((status & bits) == bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (--tmout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* Wait up to 1s for flow control if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (up->port.flags & UPF_CONS_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) unsigned int tmout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) for (tmout = 1000000; tmout; tmout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) unsigned int msr = ioread8(up->membase + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (msr & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) touch_nmi_watchdog();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * Console polling routines for communicate via uart while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * in an interrupt or debug context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int pch_uart_get_poll_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct eg20t_port *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) u8 lsr = ioread8(priv->membase + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (!(lsr & UART_LSR_DR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return ioread8(priv->membase + PCH_UART_RBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static void pch_uart_put_poll_char(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) unsigned int ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct eg20t_port *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * First save the IER then disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ier = ioread8(priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) wait_for_xmitr(priv, UART_LSR_THRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * Send the character out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) iowrite8(c, priv->membase + PCH_UART_THR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * and restore the IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) wait_for_xmitr(priv, BOTH_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) iowrite8(ier, priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #endif /* CONFIG_CONSOLE_POLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static const struct uart_ops pch_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .tx_empty = pch_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .set_mctrl = pch_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .get_mctrl = pch_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .stop_tx = pch_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .start_tx = pch_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .stop_rx = pch_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .enable_ms = pch_uart_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .break_ctl = pch_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .startup = pch_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .shutdown = pch_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .set_termios = pch_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* .pm = pch_uart_pm, Not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .type = pch_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .release_port = pch_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .request_port = pch_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .config_port = pch_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .verify_port = pch_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .poll_get_char = pch_uart_get_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .poll_put_char = pch_uart_put_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static void pch_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct eg20t_port *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) container_of(port, struct eg20t_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) wait_for_xmitr(priv, UART_LSR_THRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) iowrite8(ch, priv->membase + PCH_UART_THR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * Print a string to the serial port trying not to disturb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * any possible real use of the port...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * The console_lock must be held when we get here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pch_console_write(struct console *co, const char *s, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) int priv_locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) int port_locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) u8 ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) priv = pch_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) touch_nmi_watchdog();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (priv->port.sysrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* call to uart_handle_sysrq_char already took the priv lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) priv_locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* serial8250_handle_port() already took the port lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) port_locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) } else if (oops_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) priv_locked = spin_trylock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) port_locked = spin_trylock(&priv->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) spin_lock(&priv->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * First save the IER then disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ier = ioread8(priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) uart_console_write(&priv->port, s, count, pch_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * and restore the IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) wait_for_xmitr(priv, BOTH_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) iowrite8(ier, priv->membase + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (port_locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) spin_unlock(&priv->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (priv_locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static int __init pch_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) int baud = default_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * Check whether an invalid uart number has been specified, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * if so, search for the first available port that does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (co->index >= PCH_UART_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) port = &pch_uart_ports[co->index]->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (!port || (!port->iobase && !port->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) port->uartclk = pch_uart_get_uartclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static struct uart_driver pch_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static struct console pch_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .name = PCH_UART_DRIVER_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .write = pch_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .setup = pch_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .flags = CON_PRINTBUFFER | CON_ANYTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .data = &pch_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define PCH_CONSOLE (&pch_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define PCH_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static struct uart_driver pch_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .driver_name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .dev_name = PCH_UART_DRIVER_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .major = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .nr = PCH_UART_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .cons = PCH_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) unsigned int iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) unsigned int mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) unsigned char *rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) int fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) int port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct pch_uart_driver_data *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) char name[32]; /* for debugfs file name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) board = &drv_dat[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) port_type = board->port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) goto init_port_alloc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (!rxbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) goto init_port_free_txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) switch (port_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) case PORT_PCH_8LINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) fifosize = 256; /* EG20T/ML7213: UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) case PORT_PCH_2LINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) goto init_port_hal_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) iobase = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) mapbase = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) priv->mapbase = mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) priv->iobase = iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) priv->tx_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) priv->rxbuf.buf = rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) priv->rxbuf.size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) priv->fifo_size = fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) priv->uartclk = pch_uart_get_uartclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) priv->port_type = port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) priv->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) priv->port.iobase = iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) priv->port.membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) priv->port.mapbase = mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) priv->port.irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) priv->port.iotype = UPIO_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) priv->port.ops = &pch_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) priv->port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) priv->port.fifosize = fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) priv->port.line = board->line_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) priv->trigger = PCH_UART_HAL_TRIGGER_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) snprintf(priv->irq_name, IRQ_NAME_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) priv->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) spin_lock_init(&priv->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) pci_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) priv->trigger_level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) priv->fcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) of_property_read_u32(pdev->dev.of_node, "clock-frequency"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) , &user_uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) pch_uart_ports[board->line_no] = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ret = uart_add_one_port(&pch_uart_driver, &priv->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto init_port_hal_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) NULL, priv, &port_regs_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) init_port_hal_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) pch_uart_ports[board->line_no] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) free_page((unsigned long)rxbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) init_port_free_txbuf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) init_port_alloc_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static void pch_uart_exit_port(struct eg20t_port *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) debugfs_remove(priv->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) uart_remove_one_port(&pch_uart_driver, &priv->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) free_page((unsigned long)priv->rxbuf.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static void pch_uart_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) struct eg20t_port *priv = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pch_uart_ports[priv->port.line] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) pch_uart_exit_port(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct eg20t_port *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) uart_suspend_port(&pch_uart_driver, &priv->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static int __maybe_unused pch_uart_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct eg20t_port *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) uart_resume_port(&pch_uart_driver, &priv->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static const struct pci_device_id pch_uart_pci_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .driver_data = pch_et20t_uart0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .driver_data = pch_et20t_uart1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .driver_data = pch_et20t_uart2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .driver_data = pch_et20t_uart3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .driver_data = pch_ml7213_uart0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .driver_data = pch_ml7213_uart1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .driver_data = pch_ml7213_uart2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .driver_data = pch_ml7223_uart0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .driver_data = pch_ml7223_uart1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .driver_data = pch_ml7831_uart0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .driver_data = pch_ml7831_uart1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) {0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static int pch_uart_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) struct eg20t_port *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) goto probe_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) priv = pch_uart_init_port(pdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) goto probe_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) pci_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) probe_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) probe_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) pch_uart_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) pch_uart_pci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) static struct pci_driver pch_uart_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .name = "pch_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .id_table = pch_uart_pci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .probe = pch_uart_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .remove = pch_uart_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .driver.pm = &pch_uart_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static int __init pch_uart_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* register as UART driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ret = uart_register_driver(&pch_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* register as PCI driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ret = pci_register_driver(&pch_uart_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) uart_unregister_driver(&pch_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) module_init(pch_uart_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static void __exit pch_uart_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) pci_unregister_driver(&pch_uart_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) uart_unregister_driver(&pch_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) module_exit(pch_uart_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) module_param(default_baud, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) MODULE_PARM_DESC(default_baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) "Default BAUD for initial driver state and console (default 9600)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) module_param(user_uartclk, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) MODULE_PARM_DESC(user_uartclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) "Override UART default or board specific UART clock");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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