^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Actions Semi Owl family serial console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Actions Semi, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2016-2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OWL_UART_PORT_NUM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OWL_UART_DEV_NAME "ttyOWL"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OWL_UART_CTL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OWL_UART_RXDAT 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OWL_UART_TXDAT 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OWL_UART_STAT 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OWL_UART_CTL_DWLS_5BITS (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OWL_UART_CTL_DWLS_6BITS (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OWL_UART_CTL_DWLS_7BITS (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OWL_UART_CTL_DWLS_8BITS (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OWL_UART_CTL_STPS_2BITS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OWL_UART_CTL_PRS_NONE (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OWL_UART_CTL_PRS_ODD (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OWL_UART_CTL_PRS_MARK (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OWL_UART_CTL_PRS_EVEN (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OWL_UART_CTL_AFE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OWL_UART_CTL_TRFS_TX BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OWL_UART_CTL_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OWL_UART_CTL_RXDE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OWL_UART_CTL_TXDE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OWL_UART_CTL_RXIE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OWL_UART_CTL_TXIE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OWL_UART_CTL_LBEN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OWL_UART_STAT_RIP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OWL_UART_STAT_TIP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OWL_UART_STAT_RXER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OWL_UART_STAT_TFER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OWL_UART_STAT_RXST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OWL_UART_STAT_RFEM BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OWL_UART_STAT_TFFU BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OWL_UART_STAT_CTSS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OWL_UART_STAT_RTSS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OWL_UART_STAT_TFES BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OWL_UART_STAT_UTBB BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct uart_driver owl_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct owl_uart_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int tx_fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct owl_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(val, port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return readl(port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ctl = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ctl |= OWL_UART_CTL_LBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ctl &= ~OWL_UART_CTL_LBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) owl_uart_write(port, ctl, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static unsigned int owl_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 stat, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ctl = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) stat = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (stat & OWL_UART_STAT_RTSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mctrl |= TIOCM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned int owl_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void owl_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val |= OWL_UART_STAT_RIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) owl_uart_write(port, val, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void owl_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val |= OWL_UART_STAT_TIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) owl_uart_write(port, val, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void owl_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) owl_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) val = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val |= OWL_UART_STAT_TIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) owl_uart_write(port, val, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) val = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val |= OWL_UART_CTL_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void owl_uart_send_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ch = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) owl_uart_write(port, ch, OWL_UART_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) owl_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void owl_uart_receive_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 stat, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val &= ~OWL_UART_CTL_TRFS_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) stat = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) while (!(stat & OWL_UART_STAT_RFEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (stat & OWL_UART_STAT_RXER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (stat & OWL_UART_STAT_RXST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* We are not able to distinguish the error type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) stat &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (stat & OWL_UART_STAT_RXST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val = owl_uart_read(port, OWL_UART_RXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if ((stat & port->ignore_status_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tty_insert_flip_char(&port->state->port, val, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) stat = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static irqreturn_t owl_uart_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) stat = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (stat & OWL_UART_STAT_RIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) owl_uart_receive_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (stat & OWL_UART_STAT_TIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) owl_uart_send_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) stat = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) owl_uart_write(port, stat, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void owl_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int owl_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "owl-uart", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) owl_uart_write(port, val, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val |= OWL_UART_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk_set_rate(owl_port->clk, baud * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void owl_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct owl_uart_port *owl_port = to_owl_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ctl = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ctl &= ~OWL_UART_CTL_DWLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ctl |= OWL_UART_CTL_DWLS_5BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ctl |= OWL_UART_CTL_DWLS_6BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ctl |= OWL_UART_CTL_DWLS_7BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ctl |= OWL_UART_CTL_DWLS_8BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ctl |= OWL_UART_CTL_STPS_2BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ctl &= ~OWL_UART_CTL_STPS_2BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ctl &= ~OWL_UART_CTL_PRS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (termios->c_cflag & CMSPAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ctl |= OWL_UART_CTL_PRS_MARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ctl |= OWL_UART_CTL_PRS_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } else if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ctl |= OWL_UART_CTL_PRS_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ctl |= OWL_UART_CTL_PRS_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ctl |= OWL_UART_CTL_PRS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (termios->c_cflag & CRTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ctl |= OWL_UART_CTL_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctl &= ~OWL_UART_CTL_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) owl_uart_write(port, ctl, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) owl_uart_change_baudrate(owl_port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Don't rewrite B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) port->read_status_mask |= OWL_UART_STAT_RXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) port->read_status_mask |= OWL_UART_STAT_RXST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void owl_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) devm_release_mem_region(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) devm_iounmap(port->dev, port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int owl_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!devm_request_mem_region(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) resource_size(res), dev_name(port->dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) port->membase = devm_ioremap(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const char *owl_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return (port->type == PORT_OWL) ? "owl-uart" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int owl_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (port->type != PORT_OWL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (port->irq != ser->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void owl_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) port->type = PORT_OWL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) owl_uart_request_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct uart_ops owl_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .set_mctrl = owl_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .get_mctrl = owl_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .tx_empty = owl_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .start_tx = owl_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .stop_rx = owl_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .stop_tx = owl_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .startup = owl_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .shutdown = owl_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .set_termios = owl_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .type = owl_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .config_port = owl_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .request_port = owl_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .release_port = owl_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .verify_port = owl_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #ifdef CONFIG_SERIAL_OWL_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void owl_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) owl_uart_write(port, ch, OWL_UART_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void owl_uart_port_write(struct uart_port *port, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 old_ctl, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (port->sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) locked = spin_trylock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) old_ctl = owl_uart_read(port, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) val = old_ctl | OWL_UART_CTL_TRFS_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* disable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) owl_uart_write(port, val, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uart_console_write(port, s, count, owl_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* wait until all contents have been sent out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* clear IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) val = owl_uart_read(port, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) owl_uart_write(port, val, OWL_UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) owl_uart_write(port, old_ctl, OWL_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void owl_uart_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct owl_uart_port *owl_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) owl_port = owl_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!owl_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) owl_uart_port_write(&owl_port->port, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int owl_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct owl_uart_port *owl_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) owl_port = owl_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!owl_port || !owl_port->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct console owl_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .name = OWL_UART_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .write = owl_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .setup = owl_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .data = &owl_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int __init owl_uart_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) register_console(&owl_uart_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) console_initcall(owl_uart_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void owl_uart_early_console_write(struct console *co,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct earlycon_device *dev = co->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) owl_uart_port_write(&dev->port, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) device->con->write = owl_uart_early_console_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) owl_uart_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define OWL_UART_CONSOLE (&owl_uart_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define OWL_UART_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct uart_driver owl_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .driver_name = "owl-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .dev_name = OWL_UART_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .nr = OWL_UART_PORT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .cons = OWL_UART_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const struct owl_uart_info owl_s500_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .tx_fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const struct owl_uart_info owl_s900_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .tx_fifosize = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct of_device_id owl_uart_dt_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .compatible = "actions,s500-uart", .data = &owl_s500_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .compatible = "actions,s900-uart", .data = &owl_s900_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int owl_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) const struct owl_uart_info *info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct resource *res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct owl_uart_port *owl_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) info = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!res_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(&pdev->dev, "could not get mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (owl_uart_ports[pdev->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!owl_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) owl_port->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (IS_ERR(owl_port->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_err(&pdev->dev, "could not get clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return PTR_ERR(owl_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = clk_prepare_enable(owl_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(&pdev->dev, "could not enable clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) owl_port->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) owl_port->port.line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) owl_port->port.type = PORT_OWL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) owl_port->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) owl_port->port.mapbase = res_mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) owl_port->port.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) owl_port->port.uartclk = clk_get_rate(owl_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (owl_port->port.uartclk == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(&pdev->dev, "clock rate is zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) owl_port->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) owl_port->port.ops = &owl_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) owl_uart_ports[pdev->id] = owl_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) platform_set_drvdata(pdev, owl_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) owl_uart_ports[pdev->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int owl_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) uart_remove_one_port(&owl_uart_driver, &owl_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) owl_uart_ports[pdev->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) clk_disable_unprepare(owl_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static struct platform_driver owl_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .probe = owl_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .remove = owl_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .name = "owl-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .of_match_table = owl_uart_dt_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int __init owl_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = uart_register_driver(&owl_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = platform_driver_register(&owl_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uart_unregister_driver(&owl_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static void __exit owl_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) platform_driver_unregister(&owl_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uart_unregister_driver(&owl_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) module_init(owl_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) module_exit(owl_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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