^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for OMAP-UART controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on drivers/serial/8250.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Govindraj R <govindraj.raja@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Thara Gopinath <thara@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Note: This driver is made separate from 8250 driver as we cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * over load 8250 driver with omap platform specific configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * features like DMA, it makes easier to implement features like DMA and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * hardware flow control and software flow control configuration with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * this driver as required for the omap-platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/platform_data/serial-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP_MAX_HSUART_PORTS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP_UART_REV_42 0x0402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_UART_REV_46 0x0406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP_UART_REV_52 0x0502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP_UART_REV_63 0x0603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_UART_TX_WAKEUP_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Feature flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* SCR register bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* FCR register bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* MVR register bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP_UART_MVR_SCHEME_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP_UART_MVR_MAJ_MASK 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP_UART_MVR_MAJ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP_UART_MVR_MIN_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP_UART_DMA_CH_FREE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP_MODE13X_SPEED 230400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* WER = 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Enable module level wakeup in WER reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP_UART_WER_MOD_WKUP 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Enable XON/XOFF flow control on output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP_UART_SW_TX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Enable XON/XOFF flow control on input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP_UART_SW_RX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP_UART_SW_CLR 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP_UART_TCR_TRIG 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct uart_omap_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 uart_dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 uart_dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int rx_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int tx_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dma_addr_t rx_buf_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dma_addr_t tx_buf_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int uart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Buffer for rx dma. It is not required for tx because the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * comes from port structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned char *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int prev_rx_dma_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int tx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int tx_dma_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int rx_dma_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spinlock_t tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spinlock_t rx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* timer to poll activity on rx dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct timer_list rx_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int rx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int rx_poll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int rx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct uart_omap_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct uart_omap_dma uart_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned char ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned char lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned char fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned char efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned char dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned char dlh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned char mdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned char scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned char wer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Some bits in registers are cleared on a read, so they must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * be saved whenever the register is read, but the bits will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * be immediately processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int lsr_break_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char msr_saved_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long port_activity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int context_loss_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct gpio_desc *rts_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pm_qos_request pm_qos_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 calc_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct work_struct qos_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool is_suspending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int rs485_tx_filter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Forward declaration of functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) offset <<= up->port.regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return readw(up->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline void serial_out(struct uart_omap_port *up, int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) offset <<= up->port.regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writew(value, up->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) serial_out(up, UART_FCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!pdata || !pdata->get_context_loss_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return pdata->get_context_loss_count(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* REVISIT: Remove this when omap3 boots in device tree only mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!pdata || !pdata->enable_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pdata->enable_wakeup(up->dev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Calculate the absolute difference between the desired and actual baud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * rate for the given mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline int calculate_baud_abs_diff(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int baud, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int n = port->uartclk / (mode * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int abs_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) n = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) abs_diff = baud - (port->uartclk / (mode * n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (abs_diff < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) abs_diff = -abs_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return abs_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @port: uart port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @baud: baudrate for which mode needs to be determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Returns true if baud rate is MODE16X and false if MODE13X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * and Error Rates" determines modes not for all common baud rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * E.g. for 1000000 baud rate mode must be 16x, but according to that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * table it's determined as 13x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return (abs_diff_13 >= abs_diff_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * serial_omap_get_divisor - calculate divisor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @port: uart port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @baud: baudrate for which divisor needs to be calculated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!serial_omap_baud_is_mode16(port, baud))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mode = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mode = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return port->uartclk/(mode * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void serial_omap_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) up->ier |= UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void serial_omap_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Handle RS-485 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* THR interrupt is fired when both TX FIFO and TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * shift register are empty. This means there's nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * left to transmit now, so make sure the THR interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * is fired when TX FIFO is below the trigger level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * disable THR interrupts and toggle the RS-485 GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * data direction pin if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) serial_out(up, UART_OMAP_SCR, up->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (up->rts_gpiod &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) gpiod_get_value(up->rts_gpiod) != res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (port->rs485.delay_rts_after_send > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mdelay(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) port->rs485.delay_rts_after_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gpiod_set_value(up->rts_gpiod, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* We're asked to stop, but there's still stuff in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * UART FIFO, so make sure the THR interrupt is fired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * when both TX FIFO and TX shift register are empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * The next THR interrupt (if no transmission is started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * in the meantime) will indicate the end of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * transmission. Therefore we _don't_ disable THR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * interrupts in this situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) up->scr |= OMAP_UART_SCR_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) serial_out(up, UART_OMAP_SCR, up->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (up->ier & UART_IER_THRI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) up->ier &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void serial_omap_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) up->port.read_status_mask &= ~UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct circ_buf *xmit = &up->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (up->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) serial_out(up, UART_TX, up->port.x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) up->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) up->rs485_tx_filter_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) serial_omap_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) count = up->port.fifosize / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) serial_out(up, UART_TX, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) up->rs485_tx_filter_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uart_write_wakeup(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) serial_omap_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!(up->ier & UART_IER_THRI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) up->ier |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void serial_omap_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Handle RS-485 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Fire THR interrupts when FIFO is below trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) serial_out(up, UART_OMAP_SCR, up->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* if rts not already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpiod_set_value(up->rts_gpiod, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (port->rs485.delay_rts_before_send > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mdelay(port->rs485.delay_rts_before_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if ((port->rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) !(port->rs485.flags & SER_RS485_RX_DURING_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) up->rs485_tx_filter_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) serial_omap_enable_ier_thri(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void serial_omap_throttle(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void serial_omap_unthrottle(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) up->ier |= UART_IER_RLSI | UART_IER_RDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static unsigned int check_modem_status(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) status = serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) status |= up->msr_saved_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) up->msr_saved_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if ((status & UART_MSR_ANY_DELTA) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) up->port.state != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (status & UART_MSR_TERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) up->port.icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (status & UART_MSR_DDSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) up->port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (status & UART_MSR_DDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uart_handle_dcd_change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (&up->port, status & UART_MSR_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (status & UART_MSR_DCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uart_handle_cts_change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) (&up->port, status & UART_MSR_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) wake_up_interruptible(&up->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Read one data character out to avoid stalling the receiver according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * to the table 23-246 of the omap4 TRM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (likely(lsr & UART_LSR_DR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) up->rs485_tx_filter_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) up->rs485_tx_filter_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) up->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (lsr & UART_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) lsr &= ~(UART_LSR_FE | UART_LSR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) up->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * We do the SysRQ and SAK checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * here because otherwise the break
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * may get masked by ignore_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * or read_status_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (uart_handle_break(&up->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (lsr & UART_LSR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) up->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (lsr & UART_LSR_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) up->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (lsr & UART_LSR_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) up->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #ifdef CONFIG_SERIAL_OMAP_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (up->port.line == up->port.cons->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Recover the break flag from console xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) lsr |= up->lsr_break_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned char ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!(lsr & UART_LSR_DR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ch = serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) up->rs485_tx_filter_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) up->rs485_tx_filter_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) up->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (uart_handle_sysrq_char(&up->port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * serial_omap_irq() - This handles the interrupt from one port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * @irq: uart port irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * @dev_id: uart port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static irqreturn_t serial_omap_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct uart_omap_port *up = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int iir, lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int max_count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) iir = serial_in(up, UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (iir & UART_IIR_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) lsr = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* extract IRQ type from IIR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) type = iir & 0x3e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case UART_IIR_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) check_modem_status(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case UART_IIR_THRI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) transmit_chars(up, lsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case UART_IIR_RX_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case UART_IIR_RDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) serial_omap_rdi(up, lsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case UART_IIR_RLSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) serial_omap_rlsi(up, lsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case UART_IIR_CTS_RTS_DSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* simply try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case UART_IIR_XOFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) } while (max_count--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tty_flip_buffer_push(&up->port.state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) up->port_activity = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static unsigned int serial_omap_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static unsigned int serial_omap_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) status = check_modem_status(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (status & UART_MSR_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (status & UART_MSR_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret |= TIOCM_RNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (status & UART_MSR_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (status & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned char mcr = 0, old_mcr, lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (mctrl & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mcr |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (mctrl & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mcr |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (mctrl & TIOCM_OUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mcr |= UART_MCR_OUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (mctrl & TIOCM_OUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mcr |= UART_MCR_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mcr |= UART_MCR_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) old_mcr = serial_in(up, UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) UART_MCR_DTR | UART_MCR_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) up->mcr = old_mcr | mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) serial_out(up, UART_MCR, up->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) lcr = serial_in(up, UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) up->efr |= UART_EFR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) up->efr &= ~UART_EFR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) serial_out(up, UART_EFR, up->efr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) serial_out(up, UART_LCR, lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void serial_omap_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) up->lcr |= UART_LCR_SBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) up->lcr &= ~UART_LCR_SBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) serial_out(up, UART_LCR, up->lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int serial_omap_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Allocate the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) up->name, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Optional wake-up IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (up->wakeirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) free_irq(up->port.irq, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * Clear the FIFO buffers and disable them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * (they will be reenabled in set_termios())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) serial_omap_clear_fifos(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Clear the interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) (void) serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (serial_in(up, UART_LSR) & UART_LSR_DR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) (void) serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (void) serial_in(up, UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (void) serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * Now, initialize the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) serial_out(up, UART_LCR, UART_LCR_WLEN8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Most PC uarts need OUT2 raised to enable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) up->port.mctrl |= TIOCM_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) serial_omap_set_mctrl(&up->port, up->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) up->msr_saved_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Finally, enable interrupts. Note: Modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * are set via set_termios(), which will be occurring imminently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * anyway, so we don't enable them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) up->ier = UART_IER_RLSI | UART_IER_RDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Enable module level wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) up->wer = OMAP_UART_WER_MOD_WKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) up->wer |= OMAP_UART_TX_WAKEUP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) serial_out(up, UART_OMAP_WER, up->wer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) up->port_activity = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void serial_omap_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Disable interrupts from this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) up->ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) serial_out(up, UART_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) up->port.mctrl &= ~TIOCM_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) serial_omap_set_mctrl(&up->port, up->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * Disable break condition and FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) serial_omap_clear_fifos(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * Read data port to reset things, and then free the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (serial_in(up, UART_LSR) & UART_LSR_DR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) (void) serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) free_irq(up->port.irq, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_pm_clear_wake_irq(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static void serial_omap_uart_qos_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct uart_omap_port *up = container_of(work, struct uart_omap_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) qos_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) unsigned char cval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned int baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) cval = UART_LCR_WLEN5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) cval = UART_LCR_WLEN6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) cval = UART_LCR_WLEN7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) cval = UART_LCR_WLEN8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) cval |= UART_LCR_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (termios->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) cval |= UART_LCR_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!(termios->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cval |= UART_LCR_EPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (termios->c_cflag & CMSPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) cval |= UART_LCR_SPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * Ask the core to calculate the divisor for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) quot = serial_omap_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* calculate wakeup latency constraint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) up->latency = up->calc_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) schedule_work(&up->qos_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) up->dll = quot & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) up->dlh = quot >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) up->mdr1 = UART_OMAP_MDR1_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) UART_FCR_ENABLE_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * Ok, we're now changing the port state. Do it with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * Update the per-port timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (termios->c_iflag & (BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) up->port.read_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) up->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) up->port.ignore_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) up->port.ignore_status_mask |= UART_LSR_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * ignore all characters if CREAD is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) up->port.ignore_status_mask |= UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * Modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) up->ier &= ~UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (UART_ENABLE_MS(&up->port, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) up->ier |= UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) serial_out(up, UART_LCR, cval); /* reset DLAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) up->lcr = cval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) up->scr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* FIFOs and DMA Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* FCR can be changed only when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * baud clock is not running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * DLL_REG and DLH_REG set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) serial_out(up, UART_DLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) serial_out(up, UART_DLM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) serial_out(up, UART_LCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) up->efr &= ~UART_EFR_SCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* FIFO ENABLE, DMA MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * sets Enables the granularity of 1 for TRIGGER RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * level. Along with setting RX FIFO trigger level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * to 1 (as noted below, 16 characters) and TLR[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * to zero this will result RX FIFO threshold level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * to 1 character, instead of 16 as noted in comment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Set receive FIFO threshold to 16 characters and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * transmit FIFO threshold to 32 spaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) UART_FCR_ENABLE_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) serial_out(up, UART_FCR, up->fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) serial_out(up, UART_OMAP_SCR, up->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) serial_out(up, UART_MCR, up->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) serial_out(up, UART_EFR, up->efr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Protocol, Baud Rate, and Interrupt Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) serial_omap_mdr1_errataset(up, up->mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) serial_out(up, UART_OMAP_MDR1, up->mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) serial_out(up, UART_LCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) serial_out(up, UART_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) serial_out(up, UART_DLL, up->dll); /* LS of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) serial_out(up, UART_LCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) serial_out(up, UART_EFR, up->efr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) serial_out(up, UART_LCR, cval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!serial_omap_baud_is_mode16(port, baud))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) up->mdr1 = UART_OMAP_MDR1_13X_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) up->mdr1 = UART_OMAP_MDR1_16X_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) serial_omap_mdr1_errataset(up, up->mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) serial_out(up, UART_OMAP_MDR1, up->mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* Configure flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) serial_out(up, UART_XON1, termios->c_cc[VSTART]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Enable access to TCR/TLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) up->efr |= UART_EFR_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* Disable AUTORTS and AUTOCTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (up->port.flags & UPF_SOFT_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* clear SW control mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) up->efr &= OMAP_UART_SW_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * IXON Flag:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * Enable XON/XOFF flow control on input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Receiver compares XON1, XOFF1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (termios->c_iflag & IXON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) up->efr |= OMAP_UART_SW_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * IXOFF Flag:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * Enable XON/XOFF flow control on output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * Transmit XON1, XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (termios->c_iflag & IXOFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) up->port.status |= UPSTAT_AUTOXOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) up->efr |= OMAP_UART_SW_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * IXANY Flag:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Enable any character to restart output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * Operation resumes after receiving any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * character after recognition of the XOFF character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (termios->c_iflag & IXANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) up->mcr |= UART_MCR_XONANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) up->mcr &= ~UART_MCR_XONANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) serial_out(up, UART_MCR, up->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) serial_out(up, UART_EFR, up->efr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) serial_out(up, UART_LCR, up->lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) serial_omap_set_mctrl(&up->port, up->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) serial_omap_pm(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) unsigned char efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) efr = serial_in(up, UART_EFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) serial_out(up, UART_EFR, efr | UART_EFR_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) serial_out(up, UART_LCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) serial_out(up, UART_EFR, efr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) serial_out(up, UART_LCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static void serial_omap_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_dbg(port->dev, "serial_omap_release_port+\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int serial_omap_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_dbg(port->dev, "serial_omap_request_port+\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static void serial_omap_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) up->port.type = PORT_OMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* we don't want the core code to modify any port params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_dbg(port->dev, "serial_omap_verify_port+\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) serial_omap_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return up->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) unsigned int status, tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Wait up to 10ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) status = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (status & UART_LSR_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) up->lsr_break_flag = UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (--tmout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Wait up to 1s for flow control if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (up->port.flags & UPF_CONS_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) tmout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) for (tmout = 1000000; tmout; tmout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned int msr = serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (msr & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) serial_out(up, UART_TX, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int serial_omap_poll_get_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) status = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (!(status & UART_LSR_DR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) status = NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) status = serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #endif /* CONFIG_CONSOLE_POLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #ifdef CONFIG_SERIAL_OMAP_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #ifdef CONFIG_SERIAL_EARLYCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) offset <<= port->regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return readw(port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static void omap_serial_early_out(struct uart_port *port, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) offset <<= port->regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) writew(value, port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static void omap_serial_early_putc(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) status = omap_serial_early_in(port, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if ((status & BOTH_EMPTY) == BOTH_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) omap_serial_early_out(port, UART_TX, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static void early_omap_serial_write(struct console *console, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct earlycon_device *device = console->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct uart_port *port = &device->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) uart_console_write(port, s, count, omap_serial_early_putc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static int __init early_omap_serial_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) const char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct uart_port *port = &device->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (!(device->port.membase || device->port.iobase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) port->regshift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) device->con->write = early_omap_serial_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #endif /* CONFIG_SERIAL_EARLYCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static struct uart_driver serial_omap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static void serial_omap_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) serial_out(up, UART_TX, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) serial_omap_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct uart_omap_port *up = serial_omap_console_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) unsigned int ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (up->port.sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) locked = spin_trylock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * First save the IER then disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ier = serial_in(up, UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) serial_out(up, UART_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) uart_console_write(&up->port, s, count, serial_omap_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * and restore the IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) serial_out(up, UART_IER, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * The receive handling will happen properly because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * receive ready bit will still be set; it is not cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * on read. However, modem control will not, we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * call it if we have saved something in the saved flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * while processing with interrupts off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (up->msr_saved_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) check_modem_status(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) serial_omap_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct uart_omap_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (serial_omap_console_ports[co->index] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) up = serial_omap_console_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return uart_set_options(&up->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static struct console serial_omap_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .name = OMAP_SERIAL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .write = serial_omap_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .setup = serial_omap_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .data = &serial_omap_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static void serial_omap_add_console_port(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) serial_omap_console_ports[up->port.line] = up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define OMAP_CONSOLE (&serial_omap_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define OMAP_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static inline void serial_omap_add_console_port(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* Enable or disable the rs485 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct uart_omap_port *up = to_uart_omap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* Disable interrupts from this port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mode = up->ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) up->ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) serial_out(up, UART_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Clamp the delays to [0, 100ms] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* store new config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) port->rs485 = *rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (up->rts_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* enable / disable rts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) val = (port->rs485.flags & SER_RS485_ENABLED) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) val = (port->rs485.flags & val) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) gpiod_set_value(up->rts_gpiod, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) up->ier = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* If RS-485 is disabled, make sure the THR interrupt is fired when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * TX FIFO is below the trigger level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (!(port->rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) serial_out(up, UART_OMAP_SCR, up->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static const struct uart_ops serial_omap_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .tx_empty = serial_omap_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .set_mctrl = serial_omap_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .get_mctrl = serial_omap_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .stop_tx = serial_omap_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .start_tx = serial_omap_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .throttle = serial_omap_throttle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .unthrottle = serial_omap_unthrottle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .stop_rx = serial_omap_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_ms = serial_omap_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .break_ctl = serial_omap_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .startup = serial_omap_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .shutdown = serial_omap_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .set_termios = serial_omap_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .pm = serial_omap_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .type = serial_omap_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .release_port = serial_omap_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .request_port = serial_omap_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .config_port = serial_omap_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .verify_port = serial_omap_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .poll_put_char = serial_omap_poll_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .poll_get_char = serial_omap_poll_get_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static struct uart_driver serial_omap_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .driver_name = "OMAP-SERIAL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .dev_name = OMAP_SERIAL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .nr = OMAP_MAX_HSUART_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .cons = OMAP_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static int serial_omap_prepare(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct uart_omap_port *up = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) up->is_suspending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static void serial_omap_complete(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct uart_omap_port *up = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) up->is_suspending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int serial_omap_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct uart_omap_port *up = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) uart_suspend_port(&serial_omap_reg, &up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) flush_work(&up->qos_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) serial_omap_enable_wakeup(up, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) serial_omap_enable_wakeup(up, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static int serial_omap_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct uart_omap_port *up = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) serial_omap_enable_wakeup(up, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) uart_resume_port(&serial_omap_reg, &up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define serial_omap_prepare NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define serial_omap_complete NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) u32 mvr, scheme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u16 revision, major, minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* Check revision register scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) switch (scheme) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) case 0: /* Legacy Scheme: OMAP2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* MINOR_REV[0:4], MAJOR_REV[4:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* New Scheme: OMAP4+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* MINOR_REV[0:5], MAJOR_REV[8:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) OMAP_UART_MVR_MAJ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) minor = (mvr & OMAP_UART_MVR_MIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dev_warn(up->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) "Unknown %s revision, defaulting to highest\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) up->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* highest possible revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) major = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) minor = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* normalize revision for the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) revision = UART_BUILD_REVISION(major, minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) switch (revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) case OMAP_UART_REV_46:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) UART_ERRATA_i291_DMA_FORCEIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) case OMAP_UART_REV_52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) UART_ERRATA_i291_DMA_FORCEIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) case OMAP_UART_REV_63:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct omap_uart_port_info *omap_up_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (!omap_up_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return NULL; /* out of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) of_property_read_u32(dev->of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) &omap_up_info->uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) omap_up_info->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return omap_up_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static int serial_omap_probe_rs485(struct uart_omap_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct serial_rs485 *rs485conf = &up->port.rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) enum gpiod_flags gflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) rs485conf->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) up->rts_gpiod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = uart_get_rs485_mode(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (of_property_read_bool(np, "rs485-rts-active-high")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) rs485conf->flags |= SER_RS485_RTS_ON_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* check for tx enable gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (IS_ERR(up->rts_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ret = PTR_ERR(up->rts_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * FIXME: the code historically ignored any other error than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * -EPROBE_DEFER and just went on without GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) up->rts_gpiod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static int serial_omap_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct uart_omap_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int uartirq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int wakeirq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* The optional wakeirq may be specified in the board dts file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (!uartirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) omap_up_info = of_get_uart_port_info(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pdev->dev.platform_data = omap_up_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) uartirq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (uartirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) up->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) up->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) up->port.type = PORT_OMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) up->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) up->port.irq = uartirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) up->port.regshift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) up->port.fifosize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) up->port.ops = &serial_omap_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ret = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ret = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) goto err_port_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) up->port.line = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) OMAP_MAX_HSUART_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) goto err_port_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) up->wakeirq = wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (!up->wakeirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) dev_info(up->port.dev, "no wakeirq for uart%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ret = serial_omap_probe_rs485(up, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto err_rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) sprintf(up->name, "OMAP UART%d", up->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) up->port.mapbase = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) up->port.membase = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) up->port.flags = omap_up_info->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) up->port.uartclk = omap_up_info->uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) up->port.rs485_config = serial_omap_config_rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (!up->port.uartclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) up->port.uartclk = DEFAULT_CLK_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) "No clock speed specified: using default: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) DEFAULT_CLK_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) platform_set_drvdata(pdev, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (omap_up_info->autosuspend_timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) omap_up_info->autosuspend_timeout = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) device_init_wakeup(up->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) pm_runtime_set_autosuspend_delay(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) omap_up_info->autosuspend_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) pm_runtime_irq_safe(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) omap_serial_fill_features_erratas(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ui[up->port.line] = up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) serial_omap_add_console_port(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = uart_add_one_port(&serial_omap_reg, &up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) goto err_add_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) pm_runtime_mark_last_busy(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) pm_runtime_put_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) err_add_port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) cpu_latency_qos_remove_request(&up->pm_qos_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) device_init_wakeup(up->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) err_rs485:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) err_port_line:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static int serial_omap_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct uart_omap_port *up = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pm_runtime_get_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) uart_remove_one_port(&serial_omap_reg, &up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) pm_runtime_dont_use_autosuspend(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) pm_runtime_put_sync(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) pm_runtime_disable(up->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) cpu_latency_qos_remove_request(&up->pm_qos_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) device_init_wakeup(&dev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * The access to uart register after MDR1 Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * causes UART to corrupt data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * Need a delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * give 10 times as much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) u8 timeout = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) serial_out(up, UART_OMAP_MDR1, mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) UART_FCR_CLEAR_RCVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * TX_FIFO_E bit is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) (UART_LSR_THRE | UART_LSR_DR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* Should *never* happen. we warn and carry on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_crit(up->dev, "Errata i202: timedout %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) serial_in(up, UART_LSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static void serial_omap_restore_context(struct uart_omap_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) serial_out(up, UART_EFR, UART_EFR_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) serial_out(up, UART_LCR, 0x0); /* Operational mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) serial_out(up, UART_IER, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) serial_out(up, UART_DLL, up->dll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) serial_out(up, UART_DLM, up->dlh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) serial_out(up, UART_LCR, 0x0); /* Operational mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) serial_out(up, UART_FCR, up->fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) serial_out(up, UART_MCR, up->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) serial_out(up, UART_OMAP_SCR, up->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) serial_out(up, UART_EFR, up->efr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) serial_out(up, UART_LCR, up->lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) serial_omap_mdr1_errataset(up, up->mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) serial_out(up, UART_OMAP_MDR1, up->mdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) serial_out(up, UART_OMAP_WER, up->wer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static int serial_omap_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct uart_omap_port *up = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (!up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * When using 'no_console_suspend', the console UART must not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * suspended. Since driver suspend is managed by runtime suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * preventing runtime suspend (by returning error) will keep device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * active during suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (up->is_suspending && !console_suspend_enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) uart_console(&up->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) up->context_loss_cnt = serial_omap_get_context_loss_count(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) serial_omap_enable_wakeup(up, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) schedule_work(&up->qos_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static int serial_omap_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) struct uart_omap_port *up = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) int loss_cnt = serial_omap_get_context_loss_count(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) serial_omap_enable_wakeup(up, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (loss_cnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) loss_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) serial_omap_restore_context(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) } else if (up->context_loss_cnt != loss_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) serial_omap_restore_context(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) up->latency = up->calc_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) schedule_work(&up->qos_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static const struct dev_pm_ops serial_omap_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) serial_omap_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .prepare = serial_omap_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .complete = serial_omap_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static const struct of_device_id omap_serial_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) { .compatible = "ti,omap2-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) { .compatible = "ti,omap3-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) { .compatible = "ti,omap4-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) MODULE_DEVICE_TABLE(of, omap_serial_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static struct platform_driver serial_omap_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .probe = serial_omap_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .remove = serial_omap_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .name = OMAP_SERIAL_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .pm = &serial_omap_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .of_match_table = of_match_ptr(omap_serial_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static int __init serial_omap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ret = uart_register_driver(&serial_omap_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ret = platform_driver_register(&serial_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) uart_unregister_driver(&serial_omap_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static void __exit serial_omap_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) platform_driver_unregister(&serial_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) uart_unregister_driver(&serial_omap_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) module_init(serial_omap_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) module_exit(serial_omap_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) MODULE_DESCRIPTION("OMAP High Speed UART driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) MODULE_AUTHOR("Texas Instruments Inc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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