^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Application UART driver for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Freescale STMP37XX/STMP378X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Alphascale ASM9260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: dmitry pervushin <dimka@embeddedalley.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Provide Alphascale ASM9260 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright 2008-2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/tty_driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "serial_mctrl_gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXS_AUART_PORTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXS_AUART_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SET_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLR_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TOG_REG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AUART_CTRL0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AUART_CTRL1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AUART_CTRL2 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AUART_LINECTRL 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AUART_LINECTRL2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AUART_INTR 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AUART_DATA 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AUART_STAT 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AUART_DEBUG 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AUART_VERSION 0x00000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AUART_AUTOBAUD 0x000000a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AUART_CTRL0_SFTRST (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUART_CTRL0_CLKGATE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AUART_CTRL2_DMAONERR (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUART_CTRL2_TXDMAE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUART_CTRL2_RXDMAE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AUART_CTRL2_CTSEN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUART_CTRL2_RTSEN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AUART_CTRL2_RTS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AUART_CTRL2_RXE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AUART_CTRL2_TXE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AUART_CTRL2_UARTEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUART_LINECTRL_SPS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUART_LINECTRL_WLEN_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AUART_LINECTRL_FEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AUART_LINECTRL_STP2 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AUART_LINECTRL_EPS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AUART_LINECTRL_PEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AUART_LINECTRL_BRK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AUART_INTR_RTIEN (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AUART_INTR_TXIEN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AUART_INTR_RXIEN (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AUART_INTR_CTSMIEN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AUART_INTR_RTIS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AUART_INTR_TXIS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AUART_INTR_RXIS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AUART_INTR_CTSMIS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AUART_STAT_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AUART_STAT_CTS (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AUART_STAT_TXFE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AUART_STAT_TXFF (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AUART_STAT_RXFE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AUART_STAT_OERR (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AUART_STAT_BERR (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AUART_STAT_PERR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AUART_STAT_FERR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AUART_STAT_RXCOUNT_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Start of Alphascale asm9260 defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * This list contains only differences of existing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * between imx2x and asm9260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ASM9260_HW_CTRL0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * RW. Tell the UART to execute the RX DMA Command. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * UART will clear this bit at the end of receive execution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* RW. 0 use FIFO for status register; 1 use DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * operation. If this bit is set to 1, a receive timeout will cause the receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * input is idle, then the watchdog counter will decrement each bit-time. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 7-bit-time is added to the programmed value, so a value of zero will set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * note that the counter is reloaded at the end of each frame, so if the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * is 10 bits long and the timeout counter value is zero, then timeout will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * occur (when FIFO is not empty) even if the RX input is not idle. The default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * value is 0x3 (31 bit-time).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* TIMEOUT = (100*7+1)*(1/BAUD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* TX ctrl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ASM9260_HW_CTRL1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * RW. Tell the UART to execute the TX DMA Command. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * UART will clear this bit at the end of transmit execution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ASM9260_HW_CTRL2 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * RW. Receive Interrupt FIFO Level Select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * The trigger points for the receive interrupt are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* RW. Same as RXIFLSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* RW. Set DTR. When this bit is 1, the output is 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ASM9260_BM_CTRL2_DTR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* RW. Loop Back Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ASM9260_BM_CTRL2_LBE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ASM9260_HW_LINECTRL 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * bit is cleared stick parity is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ASM9260_BM_LCTRL_SPS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* RW. Word length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ASM9260_BM_LCTRL_WLEN (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Interrupt register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * contains the interrupt enables and the interrupt status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ASM9260_HW_INTR 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Tx FIFO EMPTY Raw Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ASM9260_BM_INTR_TFEIEN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Overrun Error Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ASM9260_BM_INTR_OEIEN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Break Error Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ASM9260_BM_INTR_BEIEN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Parity Error Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ASM9260_BM_INTR_PEIEN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Framing Error Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ASM9260_BM_INTR_FEIEN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* nUARTDSR Modem Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ASM9260_BM_INTR_DSRMIEN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* nUARTDCD Modem Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ASM9260_BM_INTR_DCDMIEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* nUARTRI Modem Interrupt Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ASM9260_BM_INTR_RIMIEN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Auto-Boud Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ASM9260_BM_INTR_ABTO BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ASM9260_BM_INTR_ABEO BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Tx FIFO EMPTY Raw Interrupt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ASM9260_BM_INTR_TFEIS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ASM9260_BM_INTR_OEIS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Break Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ASM9260_BM_INTR_BEIS BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ASM9260_BM_INTR_PEIS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ASM9260_BM_INTR_FEIS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ASM9260_BM_INTR_DSRMIS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ASM9260_BM_INTR_DCDMIS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ASM9260_BM_INTR_RIMIS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * time. In PIO mode, only one character can be accessed at a time. The status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * register contains the receive data flags and valid bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ASM9260_HW_DATA 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ASM9260_HW_STAT 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* RO. If 1, UARTAPP is present in this product. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ASM9260_BM_STAT_PRESENT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* RO. If 1, HISPEED is present in this product. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ASM9260_BM_STAT_HISPEED BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* RO. Receive FIFO Full. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ASM9260_BM_STAT_RXFULL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* RO. The UART Debug Register contains the state of the DMA signals. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ASM9260_HW_DEBUG 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* DMA Command Run Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* DMA Command End Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* DMA Request Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ASM9260_HW_ILPR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ASM9260_HW_RS485CTRL 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * RW. This bit reverses the polarity of the direction control signal on the RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * (or DTR) pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * If 0, The direction control pin will be driven to logic ‘0’ when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * transmitter has data to be sent. It will be driven to logic ‘1’ after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * last bit of data has been transmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ASM9260_BM_RS485CTRL_ONIV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* RW. Enable Auto Direction Control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* RW. Enable Auto Address Detect (AAD). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ASM9260_BM_RS485CTRL_AADEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* RW. Disable receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ASM9260_HW_RS485ADRMATCH 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Contains the address match value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ASM9260_HW_RS485DLY 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * RW. Contains the direction control (RTS or DTR) delay value. This delay time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * is in periods of the baud clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ASM9260_BM_RS485DLY_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ASM9260_HW_AUTOBAUD 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* WO. Auto-baud time-out interrupt clear bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* WO. End of auto-baud interrupt clear bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ASM9260_BM_AUTOBAUD_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * automatically cleared after auto-baud completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ASM9260_BM_AUTOBAUD_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ASM9260_HW_CTRL3 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * pins 137 and 144.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ASM9260_BM_CTRL3_MSBF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ASM9260_BM_CTRL3_BAUD8 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ASM9260_BM_CTRL3_9BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ASM9260_HW_ISO7816_CTRL 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* RW. Enable High Speed mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ASM9260_BM_ISO7816CTRL_HS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Disable Successive Receive NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Receive NACK Inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* RW. 1 - ISO7816 mode; 0 - USART mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ASM9260_HW_ISO7816_ERRCNT 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Parity error counter. Will be cleared after reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ASM9260_HW_ISO7816_STATUS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Max number of Repetitions Reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* End of Alphascale asm9260 defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct uart_driver auart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) enum mxs_auart_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) IMX23_AUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) IMX28_AUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ASM9260_AUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct vendor_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) const u16 *reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) REG_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) REG_LINECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) REG_LINECTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) REG_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) REG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) REG_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) REG_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) REG_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) REG_AUTOBAUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* The size of the array - must be last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) REG_ARRAY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [REG_CTRL0] = ASM9260_HW_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [REG_CTRL1] = ASM9260_HW_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) [REG_CTRL2] = ASM9260_HW_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [REG_LINECTRL] = ASM9260_HW_LINECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [REG_INTR] = ASM9260_HW_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [REG_DATA] = ASM9260_HW_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [REG_STAT] = ASM9260_HW_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [REG_DEBUG] = ASM9260_HW_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [REG_CTRL0] = AUART_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [REG_CTRL1] = AUART_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [REG_CTRL2] = AUART_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [REG_LINECTRL] = AUART_LINECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [REG_LINECTRL2] = AUART_LINECTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [REG_INTR] = AUART_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [REG_DATA] = AUART_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [REG_STAT] = AUART_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [REG_DEBUG] = AUART_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [REG_VERSION] = AUART_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [REG_AUTOBAUD] = AUART_AUTOBAUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct vendor_data vendor_alphascale_asm9260 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .reg_offset = mxs_asm9260_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct vendor_data vendor_freescale_stmp37xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .reg_offset = mxs_stmp37xx_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct mxs_auart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MXS_AUART_DMA_ENABLED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MXS_AUART_RTSCTS 4 /* bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int mctrl_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) enum mxs_auart_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct vendor_data *vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct scatterlist tx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct dma_chan *tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void *tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct scatterlist rx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dma_chan *rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void *rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct mctrl_gpios *gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int gpio_irq[UART_GPIO_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bool ms_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const struct platform_device_id mxs_auart_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct of_device_id mxs_auart_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .compatible = "fsl,imx28-auart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .data = &mxs_auart_devtype[IMX28_AUART]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .compatible = "fsl,imx23-auart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .data = &mxs_auart_devtype[IMX23_AUART]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .compatible = "alphascale,asm9260-auart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .data = &mxs_auart_devtype[ASM9260_AUART]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }, { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline int is_imx28_auart(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return s->devtype == IMX28_AUART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline int is_asm9260_auart(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return s->devtype == ASM9260_AUART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline bool auart_dma_enabled(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return s->flags & MXS_AUART_DMA_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return uap->vendor->reg_offset[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static unsigned int mxs_read(const struct mxs_auart_port *uap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel_relaxed(val, addr + SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) writel_relaxed(val, addr + CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void mxs_auart_stop_tx(struct uart_port *u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void mxs_auart_tx_chars(struct mxs_auart_port *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void dma_tx_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct mxs_auart_port *s = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct circ_buf *xmit = &s->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* clear the bit used to serialize the DMA tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* wake up the possible processes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uart_write_wakeup(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mxs_auart_tx_chars(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct scatterlist *sgl = &s->tx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct dma_chan *channel = s->tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* [1] : send PIO. Note, the first pio word is CTRL1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pio = AUART_CTRL1_XFER_COUNT(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 1, DMA_TRANS_NONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(s->dev, "step 1 error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* [2] : set DMA buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sg_init_one(sgl, s->tx_dma_buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) desc = dmaengine_prep_slave_sg(channel, sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(s->dev, "step 2 error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* [3] : submit the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) desc->callback = dma_tx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) desc->callback_param = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dma_async_issue_pending(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void mxs_auart_tx_chars(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct circ_buf *xmit = &s->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (auart_dma_enabled(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) void *buffer = s->tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) size = min_t(u32, UART_XMIT_SIZE - i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CIRC_CNT_TO_END(xmit->head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) xmit->tail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) UART_XMIT_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) memcpy(buffer + i, xmit->buf + xmit->tail, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) i += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (i >= UART_XMIT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (uart_tx_stopped(&s->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mxs_auart_stop_tx(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mxs_auart_dma_tx(s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (s->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) s->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mxs_write(s->port.x_char, s, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) s->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) s->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uart_write_wakeup(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (uart_circ_empty(&(s->port.state->xmit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (uart_tx_stopped(&s->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mxs_auart_stop_tx(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void mxs_auart_rx_char(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) c = mxs_read(s, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) stat = mxs_read(s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) s->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (stat & AUART_STAT_BERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) s->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (uart_handle_break(&s->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else if (stat & AUART_STAT_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) s->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } else if (stat & AUART_STAT_FERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) s->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Mask off conditions which should be ingored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) stat &= s->port.read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (stat & AUART_STAT_BERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) } else if (stat & AUART_STAT_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else if (stat & AUART_STAT_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (stat & AUART_STAT_OERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) s->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (uart_handle_sysrq_char(&s->port, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mxs_write(stat, s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void mxs_auart_rx_chars(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) stat = mxs_read(s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (stat & AUART_STAT_RXFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mxs_auart_rx_char(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mxs_write(stat, s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tty_flip_buffer_push(&s->port.state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int mxs_auart_request_port(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int mxs_auart_verify_port(struct uart_port *u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void mxs_auart_config_port(struct uart_port *u, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const char *mxs_auart_type(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return dev_name(s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void mxs_auart_release_port(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 ctrl = mxs_read(s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (mctrl & TIOCM_RTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (uart_cts_enabled(u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ctrl |= AUART_CTRL2_RTSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ctrl |= AUART_CTRL2_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mxs_write(ctrl, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mctrl_gpio_set(s->gpios, mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 mctrl_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mctrl_diff = mctrl ^ s->mctrl_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) s->mctrl_prev = mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) s->port.state != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (mctrl_diff & TIOCM_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) s->port.icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (mctrl_diff & TIOCM_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) s->port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (mctrl_diff & TIOCM_CD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (mctrl_diff & TIOCM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) wake_up_interruptible(&s->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static u32 mxs_auart_get_mctrl(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 stat = mxs_read(s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 mctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (stat & AUART_STAT_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return mctrl_gpio_get(s->gpios, &mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Enable modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void mxs_auart_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct mxs_auart_port *s = to_auart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Interrupt should not be enabled twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (s->ms_irq_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) s->ms_irq_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (s->gpio_irq[UART_GPIO_CTS] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) enable_irq(s->gpio_irq[UART_GPIO_CTS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* TODO: enable AUART_INTR_CTSMIEN otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (s->gpio_irq[UART_GPIO_DSR] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) enable_irq(s->gpio_irq[UART_GPIO_DSR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (s->gpio_irq[UART_GPIO_RI] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) enable_irq(s->gpio_irq[UART_GPIO_RI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (s->gpio_irq[UART_GPIO_DCD] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) enable_irq(s->gpio_irq[UART_GPIO_DCD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * Disable modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static void mxs_auart_disable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct mxs_auart_port *s = to_auart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Interrupt should not be disabled twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!s->ms_irq_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) s->ms_irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (s->gpio_irq[UART_GPIO_CTS] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) disable_irq(s->gpio_irq[UART_GPIO_CTS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* TODO: disable AUART_INTR_CTSMIEN otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (s->gpio_irq[UART_GPIO_DSR] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) disable_irq(s->gpio_irq[UART_GPIO_DSR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (s->gpio_irq[UART_GPIO_RI] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) disable_irq(s->gpio_irq[UART_GPIO_RI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (s->gpio_irq[UART_GPIO_DCD] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) disable_irq(s->gpio_irq[UART_GPIO_DCD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void dma_rx_callback(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct tty_port *port = &s->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) stat = mxs_read(s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) AUART_STAT_PERR | AUART_STAT_FERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) count = stat & AUART_STAT_RXCOUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) tty_insert_flip_string(port, s->rx_dma_buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mxs_write(stat, s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* start the next DMA for RX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mxs_auart_dma_prep_rx(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct scatterlist *sgl = &s->rx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct dma_chan *channel = s->rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 pio[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* [1] : send PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pio[0] = AUART_CTRL0_RXTO_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) | AUART_CTRL0_RXTIMEOUT(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 1, DMA_TRANS_NONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(s->dev, "step 1 error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* [2] : send DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_err(s->dev, "step 2 error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* [3] : submit the DMA, but do not issue it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) desc->callback = dma_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) desc->callback_param = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dma_async_issue_pending(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (s->tx_dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dma_release_channel(s->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) s->tx_dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (s->rx_dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dma_release_channel(s->rx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) s->rx_dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) kfree(s->tx_dma_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) kfree(s->rx_dma_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) s->tx_dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) s->rx_dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static void mxs_auart_dma_exit(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) mxs_auart_dma_exit_channel(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) s->flags &= ~MXS_AUART_DMA_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int mxs_auart_dma_init(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (auart_dma_enabled(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* init for RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!s->rx_dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!s->rx_dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* init for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!s->tx_dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!s->tx_dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* set the flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) s->flags |= MXS_AUART_DMA_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_dbg(s->dev, "enabled the DMA support.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* The DMA buffer is now the FIFO the TTY subsystem can use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) s->port.fifosize = UART_XMIT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mxs_auart_dma_exit_channel(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static void mxs_auart_settermios(struct uart_port *u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 bm, ctrl, ctrl2, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned int cflag, baud, baud_min, baud_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) cflag = termios->c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ctrl = AUART_LINECTRL_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ctrl2 = mxs_read(s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* byte size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) switch (cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) bm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) bm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) bm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) bm = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ctrl |= AUART_LINECTRL_WLEN(bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ctrl |= AUART_LINECTRL_PEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if ((cflag & PARODD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ctrl |= AUART_LINECTRL_EPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (cflag & CMSPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ctrl |= AUART_LINECTRL_SPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u->read_status_mask = AUART_STAT_OERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u->read_status_mask |= AUART_STAT_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u->read_status_mask |= AUART_STAT_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) u->ignore_status_mask |= AUART_STAT_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u->ignore_status_mask |= AUART_STAT_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u->ignore_status_mask |= AUART_STAT_OERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * ignore all characters if CREAD is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (cflag & CREAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ctrl2 |= AUART_CTRL2_RXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ctrl2 &= ~AUART_CTRL2_RXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* figure out the stop bits requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ctrl |= AUART_LINECTRL_STP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* figure out the hardware flow control settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * The DMA has a bug(see errata:2836) in mx23.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * So we can not implement the DMA for auart in mx23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * we can only implement the DMA support for auart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * in mx28.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (is_imx28_auart(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!mxs_auart_dma_init(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* enable DMA tranfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) | AUART_CTRL2_DMAONERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Even if RTS is GPIO line RTSEN can be enabled because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * the pinctrl configuration decides about RTS pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ctrl2 |= AUART_CTRL2_RTSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (CTS_AT_AUART())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ctrl2 |= AUART_CTRL2_CTSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* set baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (is_asm9260_auart(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) baud = uart_get_baud_rate(u, termios, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u->uartclk * 4 / 0x3FFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) div = u->uartclk * 4 / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) baud_min = DIV_ROUND_UP(u->uartclk * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) AUART_LINECTRL_BAUD_DIV_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mxs_write(ctrl, s, REG_LINECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mxs_write(ctrl2, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) uart_update_timeout(u, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* prepare for the DMA RX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (auart_dma_enabled(s) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!mxs_auart_dma_prep_rx(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Disable the normal RX interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mxs_auart_dma_exit(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev_err(s->dev, "We can not start up the DMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* CTS flow-control and modem-status interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (UART_ENABLE_MS(u, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) mxs_auart_enable_ms(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mxs_auart_disable_ms(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void mxs_auart_set_ldisc(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct ktermios *termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (termios->c_line == N_PPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) port->flags |= UPF_HARDPPS_CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) mxs_auart_enable_ms(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) port->flags &= ~UPF_HARDPPS_CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) u32 istat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct mxs_auart_port *s = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u32 mctrl_temp = s->mctrl_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u32 stat = mxs_read(s, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) istat = mxs_read(s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* ack irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) | AUART_INTR_CTSMIS), s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * Dealing with GPIO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (irq == s->gpio_irq[UART_GPIO_CTS] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) irq == s->gpio_irq[UART_GPIO_DCD] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) irq == s->gpio_irq[UART_GPIO_DSR] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) irq == s->gpio_irq[UART_GPIO_RI])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) mxs_auart_modem_status(s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mctrl_gpio_get(s->gpios, &mctrl_temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (istat & AUART_INTR_CTSMIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (CTS_AT_AUART() && s->ms_irq_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) uart_handle_cts_change(&s->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) stat & AUART_STAT_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) istat &= ~AUART_INTR_CTSMIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (!auart_dma_enabled(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) mxs_auart_rx_chars(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (istat & AUART_INTR_TXIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) mxs_auart_tx_chars(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) istat &= ~AUART_INTR_TXIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) for (i = 0; i < 10000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) reg = mxs_read(s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!(reg & AUART_CTRL0_SFTRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static void mxs_auart_reset_assert(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) reg = mxs_read(s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* if already in reset state, keep it untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (reg & AUART_CTRL0_SFTRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) reg = mxs_read(s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* reset is finished when the clock is gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (reg & AUART_CTRL0_CLKGATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_err(s->dev, "Failed to reset the unit.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static int mxs_auart_startup(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = clk_prepare_enable(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (uart_console(u)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* reset the unit to a well known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) mxs_auart_reset_assert(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) mxs_auart_reset_deassert(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* Reset FIFO size (it could have changed if DMA was enabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u->fifosize = MXS_AUART_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * Enable fifo so all four bytes of a DMA word are written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* get initial status of modem lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mctrl_gpio_get(s->gpios, &s->mctrl_prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) s->ms_irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static void mxs_auart_shutdown(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mxs_auart_disable_ms(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (auart_dma_enabled(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mxs_auart_dma_exit(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (uart_console(u)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) AUART_INTR_CTSMIEN, s, REG_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mxs_auart_reset_assert(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) clk_disable_unprepare(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static unsigned int mxs_auart_tx_empty(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if ((mxs_read(s, REG_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static void mxs_auart_start_tx(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* enable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) mxs_auart_tx_chars(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static void mxs_auart_stop_tx(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static void mxs_auart_stop_rx(struct uart_port *u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct mxs_auart_port *s = to_auart_port(u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const struct uart_ops mxs_auart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .tx_empty = mxs_auart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .start_tx = mxs_auart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .stop_tx = mxs_auart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .stop_rx = mxs_auart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .enable_ms = mxs_auart_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .break_ctl = mxs_auart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .set_mctrl = mxs_auart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .get_mctrl = mxs_auart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .startup = mxs_auart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .shutdown = mxs_auart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .set_termios = mxs_auart_settermios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .set_ldisc = mxs_auart_set_ldisc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .type = mxs_auart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .release_port = mxs_auart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .request_port = mxs_auart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .config_port = mxs_auart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .verify_port = mxs_auart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static void mxs_auart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct mxs_auart_port *s = to_auart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) unsigned int to = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!to--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) mxs_write(ch, s, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) auart_console_write(struct console *co, const char *str, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct mxs_auart_port *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) unsigned int old_ctrl0, old_ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) unsigned int to = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (co->index >= MXS_AUART_PORTS || co->index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) s = auart_port[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) clk_enable(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* First save the CR then disable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) old_ctrl2 = mxs_read(s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) old_ctrl0 = mxs_read(s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) uart_console_write(port, str, count, mxs_auart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* Finally, wait for transmitter to become empty ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!to--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * ... and restore the TCR if we waited long enough for the transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * to be idle. This might keep the transmitter enabled although it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * unused, but that is better than to disable it while it is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * transmitting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) mxs_write(old_ctrl0, s, REG_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mxs_write(old_ctrl2, s, REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) clk_disable(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) auart_console_get_options(struct mxs_auart_port *s, int *baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) int *parity, int *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) unsigned int lcr_h, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) lcr_h = mxs_read(s, REG_LINECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) *parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (lcr_h & AUART_LINECTRL_PEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (lcr_h & AUART_LINECTRL_EPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *parity = 'e';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) *parity = 'o';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) *bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) *bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (quot == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) quot = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) *baud = (port->uartclk << 2) / quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) auart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct mxs_auart_port *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * Check whether an invalid uart number has been specified, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * if so, search for the first available port that does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) s = auart_port[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = clk_prepare_enable(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) auart_console_get_options(s, &baud, &parity, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) clk_disable_unprepare(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static struct console auart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .name = "ttyAPP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .write = auart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .setup = auart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .data = &auart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static struct uart_driver auart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .driver_name = "ttyAPP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .dev_name = "ttyAPP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .major = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .nr = MXS_AUART_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .cons = &auart_console,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static void mxs_init_regs(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (is_asm9260_auart(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) s->vendor = &vendor_alphascale_asm9260;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) s->vendor = &vendor_freescale_stmp37xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static int mxs_get_clks(struct mxs_auart_port *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (!is_asm9260_auart(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) s->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return PTR_ERR_OR_ZERO(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) s->clk = devm_clk_get(s->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (IS_ERR(s->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) dev_err(s->dev, "Failed to get \"mod\" clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return PTR_ERR(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) s->clk_ahb = devm_clk_get(s->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (IS_ERR(s->clk_ahb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) dev_err(s->dev, "Failed to get \"ahb\" clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return PTR_ERR(s->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) err = clk_prepare_enable(s->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_err(s->dev, "Failed to enable ahb_clk!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_err(s->dev, "Failed to set rate!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) goto disable_clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) err = clk_prepare_enable(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dev_err(s->dev, "Failed to enable clk!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) goto disable_clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) disable_clk_ahb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) clk_disable_unprepare(s->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * could successfully get all information from dt or a negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int serial_mxs_probe_dt(struct mxs_auart_port *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* no device tree device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) s->port.line = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (of_get_property(np, "uart-has-rtscts", NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) set_bit(MXS_AUART_RTSCTS, &s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) enum mctrl_gpio_idx i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) s->gpios = mctrl_gpio_init_noauto(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (IS_ERR(s->gpios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return PTR_ERR(s->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (test_bit(MXS_AUART_RTSCTS, &s->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) clear_bit(MXS_AUART_RTSCTS, &s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) for (i = 0; i < UART_GPIO_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (gpiod && (gpiod_get_direction(gpiod) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) s->gpio_irq[i] = gpiod_to_irq(gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) s->gpio_irq[i] = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) enum mctrl_gpio_idx i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) for (i = 0; i < UART_GPIO_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (s->gpio_irq[i] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) free_irq(s->gpio_irq[i], s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) int *irq = s->gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) enum mctrl_gpio_idx i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) err = request_irq(irq[i], mxs_auart_irq_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dev_err(s->dev, "%s - Can't get %d irq\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) __func__, irq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * If something went wrong, rollback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * Be careful: i may be unsigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) while (err && (i-- > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (irq[i] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) free_irq(irq[i], s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static int mxs_auart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) of_match_device(mxs_auart_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct mxs_auart_port *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) s->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) s->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ret = serial_mxs_probe_dt(s, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) s->port.line = pdev->id < 0 ? 0 : pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (s->port.line >= ARRAY_SIZE(auart_port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pdev->id_entry = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) s->devtype = pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ret = mxs_get_clks(s, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) goto out_disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) s->port.mapbase = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) s->port.membase = ioremap(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (!s->port.membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) goto out_disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) s->port.ops = &mxs_auart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) s->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) s->port.fifosize = MXS_AUART_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) s->port.uartclk = clk_get_rate(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) s->port.type = PORT_IMX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) mxs_init_regs(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) s->mctrl_prev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) s->port.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) dev_name(&pdev->dev), s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) platform_set_drvdata(pdev, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = mxs_auart_init_gpios(s, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * Get the GPIO lines IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) ret = mxs_auart_request_gpio_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) auart_port[s->port.line] = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) mxs_auart_reset_deassert(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ret = uart_add_one_port(&auart_driver, &s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) goto out_free_qpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* ASM9260 don't have version reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (is_asm9260_auart(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev_info(&pdev->dev, "Found APPUART ASM9260\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) version = mxs_read(s, REG_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) (version >> 24) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) (version >> 16) & 0xff, version & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) out_free_qpio_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) mxs_auart_free_gpio_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) auart_port[pdev->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) iounmap(s->port.membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) out_disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (is_asm9260_auart(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) clk_disable_unprepare(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) clk_disable_unprepare(s->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static int mxs_auart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct mxs_auart_port *s = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) uart_remove_one_port(&auart_driver, &s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) auart_port[pdev->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) mxs_auart_free_gpio_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) iounmap(s->port.membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (is_asm9260_auart(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) clk_disable_unprepare(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) clk_disable_unprepare(s->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static struct platform_driver mxs_auart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .probe = mxs_auart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .remove = mxs_auart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .name = "mxs-auart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .of_match_table = mxs_auart_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static int __init mxs_auart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) r = uart_register_driver(&auart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) r = platform_driver_register(&mxs_auart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) uart_unregister_driver(&auart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static void __exit mxs_auart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) platform_driver_unregister(&mxs_auart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) uart_unregister_driver(&auart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) module_init(mxs_auart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) module_exit(mxs_auart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) MODULE_DESCRIPTION("Freescale MXS application uart driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) MODULE_ALIAS("platform:mxs-auart");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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