^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell Armada-3700 Serial Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wilson Ding <dingwei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UART_STD_RBR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UART_EXT_RBR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UART_STD_TSH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UART_EXT_TSH 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UART_STD_CTRL1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UART_EXT_CTRL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CTRL_SOFT_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CTRL_TXFIFO_RST BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CTRL_RXFIFO_RST BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CTRL_SND_BRK_SEQ BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CTRL_BRK_DET_INT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CTRL_FRM_ERR_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CTRL_PAR_ERR_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTRL_OVR_ERR_INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UART_STD_CTRL2 UART_STD_CTRL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UART_EXT_CTRL2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CTRL_STD_TX_RDY_INT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CTRL_EXT_TX_RDY_INT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CTRL_STD_RX_RDY_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CTRL_EXT_RX_RDY_INT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UART_STAT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STAT_TX_FIFO_EMP BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STAT_TX_FIFO_FUL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STAT_TX_EMP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STAT_STD_TX_RDY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STAT_EXT_TX_RDY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STAT_STD_RX_RDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STAT_EXT_RX_RDY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STAT_BRK_DET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STAT_FRM_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STAT_PAR_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STAT_OVR_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) | STAT_PAR_ERR | STAT_OVR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UART_BRDV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BRDV_BAUD_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UART_OSAMP 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OSAMP_DEFAULT_DIVISOR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OSAMP_DIVISORS_MASK 0x3F3F3F3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MVEBU_NR_UARTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MVEBU_UART_TYPE "mvebu-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRIVER_NAME "mvebu_serial"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Either there is only one summed IRQ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) UART_IRQ_SUM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* ...or there are two separate IRQ for RX and TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) UART_RX_IRQ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) UART_TX_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) UART_IRQ_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Diverging register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct uart_regs_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int rbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int tsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Diverging flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct uart_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int ctrl_tx_rdy_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int ctrl_rx_rdy_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int stat_tx_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int stat_rx_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Driver data, a structure for each UART port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct mvebu_uart_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool is_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct uart_regs_layout regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct uart_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Saved registers during suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct mvebu_uart_pm_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int rbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int tsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int brdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int osamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* MVEBU UART driver structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mvebu_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int irq[UART_IRQ_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned char __iomem *nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mvebu_uart_driver_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #if defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mvebu_uart_pm_regs pm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct mvebu_uart *to_mvuart(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return (struct mvebu_uart *)port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Core UART Driver Operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void mvebu_uart_set_mctrl(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Even if we do not support configuring the modem control lines, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * function must be proided to the serial core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void mvebu_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int ctl = readl(port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ctl &= ~CTRL_TX_RDY_INT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(ctl, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void mvebu_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ctl = readl(port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ctl |= CTRL_TX_RDY_INT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writel(ctl, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void mvebu_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ctl = readl(port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ctl &= ~CTRL_BRK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writel(ctl, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ctl = readl(port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ctl &= ~CTRL_RX_RDY_INT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(ctl, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ctl = readl(port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (brk == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ctl |= CTRL_SND_BRK_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ctl &= ~CTRL_SND_BRK_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(ctl, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned char ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) char flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (status & STAT_RX_RDY(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ch = readl(port->membase + UART_RBR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ch &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (status & STAT_PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (status & STAT_BRK_DET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto ignore_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (status & STAT_OVR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (status & STAT_FRM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto ignore_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (status & port->ignore_status_mask & STAT_PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) status &= ~STAT_RX_RDY(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) status &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (status & STAT_PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) status &= ~port->ignore_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (status & STAT_RX_RDY(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tty_insert_flip_char(tport, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (status & STAT_BRK_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tty_insert_flip_char(tport, 0, TTY_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (status & STAT_FRM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tty_insert_flip_char(tport, 0, TTY_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (status & STAT_OVR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ignore_char:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) status = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(port->x_char, port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mvebu_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (count = 0; count < port->fifosize; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (st & STAT_TX_FIFO_FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mvebu_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct uart_port *port = (struct uart_port *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) STAT_BRK_DET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mvebu_uart_rx_chars(port, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (st & STAT_TX_RDY(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mvebu_uart_tx_chars(port, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct uart_port *port = (struct uart_port *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) STAT_BRK_DET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mvebu_uart_rx_chars(port, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct uart_port *port = (struct uart_port *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (st & STAT_TX_RDY(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mvebu_uart_tx_chars(port, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int mvebu_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct mvebu_uart *mvuart = to_mvuart(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Clear the error bits of state register before IRQ request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret |= STAT_BRK_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) writel(ret, port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ctl = readl(port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ctl |= CTRL_RX_RDY_INT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) writel(ctl, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!mvuart->irq[UART_TX_IRQ]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Old bindings with just one interrupt (UART0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mvebu_uart_isr, port->irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_name(port->dev), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(port->dev, "unable to request IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mvuart->irq[UART_IRQ_SUM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* New bindings with an IRQ for RX and TX (both UART) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mvebu_uart_rx_isr, port->irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_name(port->dev), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(port->dev, "unable to request IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mvuart->irq[UART_RX_IRQ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mvebu_uart_tx_isr, port->irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_name(port->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(port->dev, "unable to request IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mvuart->irq[UART_TX_IRQ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void mvebu_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct mvebu_uart *mvuart = to_mvuart(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(0, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!mvuart->irq[UART_TX_IRQ]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int d_divisor, m_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 brdv, osamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!port->uartclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * The baudrate is derived from the UART clock thanks to two divisors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * > D ("baud generator"): can divide the clock from 2 to 2^10 - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * > M ("fractional divisor"): allows a better accuracy for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * baudrates higher than 230400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * As the derivation of M is rather complicated, the code sticks to its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * default value (x16) when all the prescalers are zeroed, and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * makes use of D to configure the desired baudrate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) m_divisor = OSAMP_DEFAULT_DIVISOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) brdv = readl(port->membase + UART_BRDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) brdv &= ~BRDV_BAUD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) brdv |= d_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writel(brdv, port->membase + UART_BRDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) osamp = readl(port->membase + UART_OSAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) osamp &= ~OSAMP_DIVISORS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) writel(osamp, port->membase + UART_OSAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void mvebu_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int baud, min_baud, max_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) port->ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Maximal divisor is 1023 * 16 when using default (x16) scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Maximum achievable frequency with simple baudrate divisor is 230400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Since the error per bit frame would be of more than 15%, achieving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * higher frequencies would require to implement the fractional divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) max_baud = 230400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (mvebu_uart_baud_rate_set(port, baud)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* No clock available, baudrate cannot be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) baud = uart_get_baud_rate(port, old, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) min_baud, max_baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Only the following flag changes are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) termios->c_iflag &= INPCK | IGNPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) termios->c_cflag &= CREAD | CBAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) termios->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const char *mvebu_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return MVEBU_UART_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void mvebu_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Nothing to do here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int mvebu_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int mvebu_uart_get_poll_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!(st & STAT_RX_RDY(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return readl(port->membase + UART_RBR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!(st & STAT_TX_FIFO_FUL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel(c, port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const struct uart_ops mvebu_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .tx_empty = mvebu_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .set_mctrl = mvebu_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .get_mctrl = mvebu_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .stop_tx = mvebu_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .start_tx = mvebu_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .stop_rx = mvebu_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .break_ctl = mvebu_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .startup = mvebu_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .shutdown = mvebu_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .set_termios = mvebu_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .type = mvebu_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .release_port = mvebu_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .request_port = mvebu_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .poll_get_char = mvebu_uart_get_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .poll_put_char = mvebu_uart_put_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Console Driver Operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Early Console */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void mvebu_uart_putc(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!(st & STAT_TX_FIFO_FUL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* At early stage, DT is not parsed yet, only use UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) writel(c, port->membase + UART_STD_TSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) st = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (st & STAT_TX_FIFO_EMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void mvebu_uart_putc_early_write(struct console *con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uart_console_write(&dev->port, s, n, mvebu_uart_putc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mvebu_uart_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) device->con->write = mvebu_uart_putc_early_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mvebu_uart_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void wait_for_xmitr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) readl_poll_timeout_atomic(port->membase + UART_STAT, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (val & STAT_TX_RDY(port)), 1, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static void wait_for_xmite(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) readl_poll_timeout_atomic(port->membase + UART_STAT, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (val & STAT_TX_EMP), 1, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writel(ch, port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void mvebu_uart_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct uart_port *port = &mvebu_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int ier, intr, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) locked = spin_trylock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) intr = readl(port->membase + UART_INTR(port)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel(0, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) writel(0, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) uart_console_write(port, s, count, mvebu_uart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) wait_for_xmite(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel(ier, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (intr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ctl = intr | readl(port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel(ctl, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int mvebu_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) port = &mvebu_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!port->mapbase || !port->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pr_debug("console on ttyMV%i not present\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct uart_driver mvebu_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct console mvebu_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .name = "ttyMV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .write = mvebu_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .setup = mvebu_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .data = &mvebu_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int __init mvebu_uart_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) register_console(&mvebu_uart_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) console_initcall(mvebu_uart_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct uart_driver mvebu_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .dev_name = "ttyMV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .nr = MVEBU_NR_UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .cons = &mvebu_uart_console,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #if defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int mvebu_uart_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct mvebu_uart *mvuart = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct uart_port *port = mvuart->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) uart_suspend_port(&mvebu_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) device_set_wakeup_enable(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int mvebu_uart_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct mvebu_uart *mvuart = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct uart_port *port = mvuart->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uart_resume_port(&mvebu_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct dev_pm_ops mvebu_uart_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .suspend = mvebu_uart_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .resume = mvebu_uart_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const struct of_device_id mvebu_uart_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Counter to keep track of each UART port id when not using CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int uart_num_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int mvebu_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct mvebu_uart *mvuart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int id, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_err(&pdev->dev, "no registers defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Assume that all UART ports have a DT alias or none has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) id = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (!pdev->dev.of_node || id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pdev->id = uart_num_counter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pdev->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (pdev->id >= MVEBU_NR_UARTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MVEBU_NR_UARTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) port = &mvebu_uart_ports[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) port->type = PORT_MVEBU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) port->ops = &mvebu_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) port->regshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) port->fifosize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) port->iotype = UPIO_MEM32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) port->flags = UPF_FIXED_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) port->line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * IRQ number is not stored in this structure because we may have two of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * them per port (RX and TX). Instead, use the driver UART structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * array so called ->irq[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) port->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) port->irqflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) port->mapbase = reg->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) port->membase = devm_ioremap_resource(&pdev->dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (IS_ERR(port->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return PTR_ERR(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!mvuart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Get controller data depending on the compatible string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mvuart->data = (struct mvebu_uart_driver_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mvuart->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) port->private_data = mvuart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) platform_set_drvdata(pdev, mvuart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Get fixed clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mvuart->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (IS_ERR(mvuart->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return PTR_ERR(mvuart->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (IS_EXTENDED(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_err(&pdev->dev, "unable to get UART clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return PTR_ERR(mvuart->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!clk_prepare_enable(mvuart->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) port->uartclk = clk_get_rate(mvuart->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Manage interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (platform_irq_count(pdev) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Old bindings: no name on the single unamed UART0 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mvuart->irq[UART_IRQ_SUM] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * New bindings: named interrupts (RX, TX) for both UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * only make use of uart-rx and uart-tx interrupts, do not use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * uart-sum of UART0 port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) irq = platform_get_irq_byname(pdev, "uart-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) mvuart->irq[UART_RX_IRQ] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) irq = platform_get_irq_byname(pdev, "uart-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mvuart->irq[UART_TX_IRQ] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* UART Soft Reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) writel(0, port->membase + UART_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return uart_add_one_port(&mvebu_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static struct mvebu_uart_driver_data uart_std_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .is_ext = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .regs.rbr = UART_STD_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .regs.tsh = UART_STD_TSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .regs.ctrl = UART_STD_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .regs.intr = UART_STD_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .flags.stat_tx_rdy = STAT_STD_TX_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .flags.stat_rx_rdy = STAT_STD_RX_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static struct mvebu_uart_driver_data uart_ext_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .is_ext = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .regs.rbr = UART_EXT_RBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .regs.tsh = UART_EXT_TSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .regs.ctrl = UART_EXT_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .regs.intr = UART_EXT_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const struct of_device_id mvebu_uart_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .compatible = "marvell,armada-3700-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .data = (void *)&uart_std_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .compatible = "marvell,armada-3700-uart-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .data = (void *)&uart_ext_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct platform_driver mvebu_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .probe = mvebu_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .name = "mvebu-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .of_match_table = of_match_ptr(mvebu_uart_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #if defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .pm = &mvebu_uart_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int __init mvebu_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = uart_register_driver(&mvebu_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = platform_driver_register(&mvebu_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) uart_unregister_driver(&mvebu_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) arch_initcall(mvebu_uart_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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