^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for msm7k serial device and console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Robert Love <rlove@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UART_MR1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UART_MR1_RX_RDY_CTL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UART_MR1_CTS_CTL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UART_MR2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UART_MR2_ERROR_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UART_MR2_BITS_PER_CHAR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UART_MR2_PARITY_MODE_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UART_MR2_PARITY_MODE_ODD 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UART_MR2_PARITY_MODE_EVEN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UART_MR2_PARITY_MODE_SPACE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UART_MR2_PARITY_MODE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UART_CSR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UART_TF 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UARTDM_TF 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UART_CR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UART_CR_CMD_NULL (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UART_CR_CMD_RESET_RX (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UART_CR_CMD_RESET_TX (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UART_CR_CMD_RESET_ERR (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UART_CR_CMD_START_BREAK (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UART_CR_CMD_STOP_BREAK (6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UART_CR_CMD_RESET_CTS (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UART_CR_CMD_PACKET_MODE (9 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UART_CR_CMD_MODE_RESET (12 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UART_CR_CMD_SET_RFR (13 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UART_CR_CMD_RESET_RFR (14 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UART_CR_CMD_PROTECTION_EN (16 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UART_CR_CMD_FORCE_STALE (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define UART_CR_CMD_RESET_TX_READY (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define UART_CR_TX_DISABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UART_CR_TX_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UART_CR_RX_DISABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UART_CR_RX_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UART_IMR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UART_IMR_TXLEV BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UART_IMR_RXSTALE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UART_IMR_RXLEV BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UART_IMR_DELTA_CTS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UART_IMR_CURRENT_CTS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UART_IMR_RXBREAK_START BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UART_IPR_RXSTALE_LAST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UART_IPR_STALE_LSB 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UART_IPR 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UART_TFWR 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UART_RFWR 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UART_HCR 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define UART_MREG 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UART_NREG 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UART_DREG 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UART_MNDREG 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UART_IRDA 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UART_MISR_MODE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define UART_MISR_RESET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define UART_MISR_EXPORT 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UART_MISR_VAL 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define UART_TEST_CTRL 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define UART_SR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UART_SR_HUNT_CHAR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define UART_SR_RX_BREAK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UART_SR_PAR_FRAME_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define UART_SR_OVERRUN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define UART_SR_TX_EMPTY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UART_SR_TX_READY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UART_SR_RX_FULL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define UART_SR_RX_READY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define UART_RF 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define UARTDM_RF 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define UART_MISR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UART_ISR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define UART_ISR_TX_READY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define UARTDM_RXFS 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define UARTDM_RXFS_BUF_SHIFT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define UARTDM_RXFS_BUF_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define UARTDM_DMEN 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define UARTDM_DMRX 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define UARTDM_NCF_TX 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define UARTDM_RX_TOTAL_SNAP 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define UARTDM_BURST_SIZE 16 /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) UARTDM_1P1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) UARTDM_1P2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) UARTDM_1P3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UARTDM_1P4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct msm_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct msm_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct uart_port uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int is_uartdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int old_snap_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool break_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct msm_dma tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct msm_dma rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel_relaxed(val, port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int msm_read(struct uart_port *port, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return readl_relaxed(port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Setup the MND registers to use the TCXO clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msm_write(port, 0x06, UART_MREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) msm_write(port, 0xF1, UART_NREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) msm_write(port, 0x0F, UART_DREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) msm_write(port, 0x1A, UART_MNDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) port->uartclk = 1843200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Setup the MND registers to use the TCXO clock divided by 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) msm_write(port, 0x18, UART_MREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) msm_write(port, 0xF6, UART_NREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msm_write(port, 0x0F, UART_DREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) msm_write(port, 0x0A, UART_MNDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) port->uartclk = 1843200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void msm_serial_set_mnd_regs(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * These registers don't exist so we change the clk input rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * on uartdm hardware instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (port->uartclk == 19200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) msm_serial_set_mnd_regs_tcxo(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else if (port->uartclk == 4800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) msm_serial_set_mnd_regs_tcxoby4(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void msm_handle_tx(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void msm_start_rx_dma(struct msm_port *msm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct device *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mapped = dma->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dma->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dmaengine_terminate_all(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * DMA Stall happens if enqueue and flush command happens concurrently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * For example before changing the baud rate/protocol configuration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * sending flush command to ADM, disable the channel of UARTDM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Note: should not reset the receiver here immediately as it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * suggested to do disable/reset or reset/disable at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = msm_read(port, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val &= ~dma->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) msm_write(port, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (mapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dma_unmap_single(dev, dma->phys, mapped, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void msm_release_dma(struct msm_port *msm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct msm_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma = &msm_port->tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (dma->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) msm_stop_dma(&msm_port->uart, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dma_release_channel(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) memset(dma, 0, sizeof(*dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (dma->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) msm_stop_dma(&msm_port->uart, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dma_release_channel(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) kfree(dma->virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) memset(dma, 0, sizeof(*dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct device *dev = msm_port->uart.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct dma_slave_config conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct msm_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 crci = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dma = &msm_port->tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* allocate DMA resources, if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dma->chan = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (IS_ERR(dma->chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto no_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) memset(&conf, 0, sizeof(conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) conf.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) conf.device_fc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) conf.dst_addr = base + UARTDM_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) conf.dst_maxburst = UARTDM_BURST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) conf.slave_id = crci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = dmaengine_slave_config(dma->chan, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto rel_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dma->dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (msm_port->is_uartdm < UARTDM_1P4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) rel_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dma_release_channel(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) no_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) memset(dma, 0, sizeof(*dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device *dev = msm_port->uart.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct dma_slave_config conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct msm_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 crci = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* allocate DMA resources, if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dma->chan = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (IS_ERR(dma->chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto no_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!dma->virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto rel_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) memset(&conf, 0, sizeof(conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) conf.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) conf.device_fc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) conf.src_addr = base + UARTDM_RF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) conf.src_maxburst = UARTDM_BURST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) conf.slave_id = crci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = dmaengine_slave_config(dma->chan, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dma->dir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (msm_port->is_uartdm < UARTDM_1P4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) kfree(dma->virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rel_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dma_release_channel(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) no_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) memset(dma, 0, sizeof(*dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static inline void msm_wait_for_xmitr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int timeout = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void msm_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) msm_port->imr &= ~UART_IMR_TXLEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void msm_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct msm_dma *dma = &msm_port->tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Already started in DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (dma->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msm_port->imr |= UART_IMR_TXLEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void msm_reset_dm_count(struct uart_port *port, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) msm_wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) msm_write(port, count, UARTDM_NCF_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) msm_read(port, UARTDM_NCF_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void msm_complete_tx_dma(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct msm_port *msm_port = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct uart_port *port = &msm_port->uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct msm_dma *dma = &msm_port->tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Already stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!dma->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) val = msm_read(port, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val &= ~dma->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) msm_write(port, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (msm_port->is_uartdm > UARTDM_1P3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msm_write(port, UART_CR_TX_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) count = dma->count - state.residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) port->icount.tx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dma->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) xmit->tail += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) xmit->tail &= UART_XMIT_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Restore "Tx FIFO below watermark" interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msm_port->imr |= UART_IMR_TXLEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msm_handle_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct circ_buf *xmit = &msm_port->uart.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct uart_port *port = &msm_port->uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct msm_dma *dma = &msm_port->tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) void *cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cpu_addr = &xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = dma_mapping_error(port->dev, dma->phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) count, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DMA_PREP_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DMA_PREP_FENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!dma->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dma->desc->callback = msm_complete_tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dma->desc->callback_param = msm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dma->cookie = dmaengine_submit(dma->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = dma_submit_error(dma->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Using DMA complete for Tx FIFO reload, no need for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * "Tx FIFO below watermark" one, disable it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msm_port->imr &= ~UART_IMR_TXLEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dma->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) val = msm_read(port, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val |= dma->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (msm_port->is_uartdm < UARTDM_1P4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msm_write(port, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msm_reset_dm_count(port, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (msm_port->is_uartdm > UARTDM_1P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msm_write(port, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dma_async_issue_pending(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dma_unmap_single(port->dev, dma->phys, count, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void msm_complete_rx_dma(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct msm_port *msm_port = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct uart_port *port = &msm_port->uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct msm_dma *dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int count = 0, i, sysrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Already stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!dma->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val = msm_read(port, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val &= ~dma->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msm_write(port, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) port->icount.rx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dma->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (msm_port->break_detected && dma->virt[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msm_port->break_detected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!(port->read_status_mask & UART_SR_RX_BREAK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) tty_insert_flip_char(tport, dma->virt[i], flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) msm_start_rx_dma(msm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void msm_start_rx_dma(struct msm_port *msm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct msm_dma *dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct uart_port *uart = &msm_port->uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (IS_ENABLED(CONFIG_CONSOLE_POLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!dma->chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dma->phys = dma_map_single(uart->dev, dma->virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) UARTDM_RX_SIZE, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = dma_mapping_error(uart->dev, dma->phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto sw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!dma->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma->desc->callback = msm_complete_rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dma->desc->callback_param = msm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dma->cookie = dmaengine_submit(dma->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = dma_submit_error(dma->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Using DMA for FIFO off-load, no need for "Rx FIFO over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * watermark" or "stale" interrupts, disable them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * we need RXSTALE to flush input DMA fifo to memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (msm_port->is_uartdm < UARTDM_1P4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) msm_port->imr |= UART_IMR_RXSTALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) msm_write(uart, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dma->count = UARTDM_RX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dma_async_issue_pending(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val = msm_read(uart, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val |= dma->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (msm_port->is_uartdm < UARTDM_1P4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) msm_write(uart, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (msm_port->is_uartdm > UARTDM_1P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) msm_write(uart, val, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sw_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * receiver must be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) msm_write(uart, UART_CR_RX_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Re-enable RX interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) msm_write(uart, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static void msm_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct msm_dma *dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (dma->chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) msm_stop_dma(port, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void msm_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) msm_port->imr |= UART_IMR_DELTA_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __must_hold(&port->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (misr & UART_IMR_RXSTALE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) msm_port->old_snap_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) msm_port->old_snap_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) count = 4 * (msm_read(port, UART_RFWR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) msm_port->old_snap_state += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* TODO: Precise error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) port->icount.rx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) while (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int sysrq, r_count, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) sr = msm_read(port, UART_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if ((sr & UART_SR_RX_READY) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) msm_port->old_snap_state -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ioread32_rep(port->membase + UARTDM_RF, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) r_count = min_t(int, count, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) for (i = 0; i < r_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (msm_port->break_detected && buf[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) msm_port->break_detected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!(port->read_status_mask & UART_SR_RX_BREAK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) sysrq = uart_handle_sysrq_char(port, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) tty_insert_flip_char(tport, buf[i], flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) count -= r_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (misr & (UART_IMR_RXSTALE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) msm_write(port, 0xFFFFFF, UARTDM_DMRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Try to use DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) msm_start_rx_dma(msm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void msm_handle_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __must_hold(&port->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unsigned int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Handle overrun. My understanding of the hardware is that overrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * is not tied to the RX buffer, so we handle the case out of band.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* and now the main RX loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int sysrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) c = msm_read(port, UART_RF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (sr & UART_SR_RX_BREAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else if (sr & UART_SR_PAR_FRAME_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Mask conditions we're ignorning. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) sr &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (sr & UART_SR_RX_BREAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) else if (sr & UART_SR_PAR_FRAME_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) sysrq = uart_handle_sysrq_char(port, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) tty_insert_flip_char(tport, c, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned int num_chars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) unsigned int tf_pointer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) void __iomem *tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) tf = port->membase + UARTDM_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tf = port->membase + UART_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (tx_count && msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) msm_reset_dm_count(port, tx_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) while (tf_pointer < tx_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) char buf[4] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) num_chars = min(tx_count - tf_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) (unsigned int)sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) num_chars = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) for (i = 0; i < num_chars; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) buf[i] = xmit->buf[xmit->tail + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) iowrite32_rep(tf, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) tf_pointer += num_chars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* disable tx interrupts if nothing more to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) msm_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void msm_handle_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct circ_buf *xmit = &msm_port->uart.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct msm_dma *dma = &msm_port->tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int pio_count, dma_count, dma_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) char buf[4] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void __iomem *tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tf = port->membase + UARTDM_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) tf = port->membase + UART_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) buf[0] = port->x_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) msm_reset_dm_count(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) iowrite32_rep(tf, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) msm_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dma_min = 1; /* Always DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (msm_port->is_uartdm > UARTDM_1P3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dma_count = UARTDM_TX_AIGN(dma_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dma_min = UARTDM_BURST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (dma_count > UARTDM_TX_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dma_count = UARTDM_TX_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (pio_count > port->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pio_count = port->fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!dma->chan || dma_count < dma_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) msm_handle_tx_pio(port, pio_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) err = msm_handle_tx_dma(msm_port, dma_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (err) /* fall back to PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) msm_handle_tx_pio(port, pio_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static void msm_handle_delta_cts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) port->icount.cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) wake_up_interruptible(&port->state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static irqreturn_t msm_uart_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct msm_dma *dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) unsigned int misr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) misr = msm_read(port, UART_MISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) msm_write(port, 0, UART_IMR); /* disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (misr & UART_IMR_RXBREAK_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) msm_port->break_detected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (dma->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) val = UART_CR_CMD_STALE_EVENT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) msm_write(port, val, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val = UART_CR_CMD_RESET_STALE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) msm_write(port, val, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Flush DMA input fifo to memory, this will also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * trigger DMA RX completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dmaengine_terminate_all(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) } else if (msm_port->is_uartdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) msm_handle_rx_dm(port, misr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) msm_handle_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (misr & UART_IMR_TXLEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) msm_handle_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (misr & UART_IMR_DELTA_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) msm_handle_delta_cts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static unsigned int msm_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static unsigned int msm_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static void msm_reset(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* reset everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mr = msm_read(port, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mr &= ~UART_MR1_RX_RDY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) msm_write(port, mr, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Disable DM modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) msm_write(port, 0, UARTDM_DMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) unsigned int mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mr = msm_read(port, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!(mctrl & TIOCM_RTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) mr &= ~UART_MR1_RX_RDY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) msm_write(port, mr, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) mr |= UART_MR1_RX_RDY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) msm_write(port, mr, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static void msm_break_ctl(struct uart_port *port, int break_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (break_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct msm_baud_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u16 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u8 rxstale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct msm_baud_map *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) msm_find_best_baud(struct uart_port *port, unsigned int baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned long *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned int divisor, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) const struct msm_baud_map *entry, *end, *best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const struct msm_baud_map table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { 1, 0xff, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { 2, 0xee, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { 3, 0xdd, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { 4, 0xcc, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { 6, 0xbb, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { 8, 0xaa, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { 12, 0x99, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { 16, 0x88, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { 24, 0x77, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { 32, 0x66, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { 48, 0x55, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { 96, 0x44, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { 192, 0x33, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) { 384, 0x22, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) { 768, 0x11, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { 1536, 0x00, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) best = table; /* Default to smallest divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) target = clk_round_rate(msm_port->clk, 16 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) end = table + ARRAY_SIZE(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) entry = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) while (entry < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (entry->divisor <= divisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) result = target / entry->divisor / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) diff = abs(result - baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Keep track of best entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) best = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) best_rate = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (result == baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) } else if (entry->divisor > divisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) old = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) target = clk_round_rate(msm_port->clk, old + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * The rate didn't get any faster so we can't do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * better at dividing it down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (target == old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* Start the divisor search over at this new rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) entry = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) *rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) unsigned long *saved_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) unsigned int rxstale, watermark, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) const struct msm_baud_map *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) unsigned long flags, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) flags = *saved_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) entry = msm_find_best_baud(port, baud, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) clk_set_rate(msm_port->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) baud = rate / 16 / entry->divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) *saved_flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) port->uartclk = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) msm_write(port, entry->code, UART_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* RX stale watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) rxstale = entry->rxstale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) watermark = UART_IPR_STALE_LSB & rxstale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (msm_port->is_uartdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) watermark |= UART_IPR_RXSTALE_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) mask = UART_IPR_STALE_TIMEOUT_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) watermark |= mask & (rxstale << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) msm_write(port, watermark, UART_IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* set RX watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) watermark = (port->fifosize * 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) msm_write(port, watermark, UART_RFWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* set TX watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) msm_write(port, 10, UART_TFWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) msm_reset(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Enable RX and TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* turn on RX and CTS interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) msm_write(port, msm_port->imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (msm_port->is_uartdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) msm_write(port, 0xFFFFFF, UARTDM_DMRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static void msm_init_clock(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) clk_prepare_enable(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) clk_prepare_enable(msm_port->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) msm_serial_set_mnd_regs(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int msm_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) unsigned int data, rfr_level, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) snprintf(msm_port->name, sizeof(msm_port->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "msm_serial%d", port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) msm_init_clock(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (likely(port->fifosize > 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) rfr_level = port->fifosize - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) rfr_level = port->fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* set automatic RFR level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) data = msm_read(port, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) mask = UART_MR1_AUTO_RFR_LEVEL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) data &= ~UART_MR1_AUTO_RFR_LEVEL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) data |= mask & (rfr_level << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) msm_write(port, data, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (msm_port->is_uartdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) msm_port->name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) msm_release_dma(msm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) clk_disable_unprepare(msm_port->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) clk_disable_unprepare(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static void msm_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) msm_port->imr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) msm_write(port, 0, UART_IMR); /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) msm_release_dma(msm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) clk_disable_unprepare(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct msm_dma *dma = &msm_port->rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) unsigned int baud, mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (dma->chan) /* Terminate if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) msm_stop_dma(port, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* calculate and set baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) baud = msm_set_baud_rate(port, baud, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* calculate parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) mr = msm_read(port, UART_MR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) mr &= ~UART_MR2_PARITY_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) mr |= UART_MR2_PARITY_MODE_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) else if (termios->c_cflag & CMSPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) mr |= UART_MR2_PARITY_MODE_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) mr |= UART_MR2_PARITY_MODE_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* calculate bits per char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mr &= ~UART_MR2_BITS_PER_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) mr |= UART_MR2_BITS_PER_CHAR_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mr |= UART_MR2_BITS_PER_CHAR_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) mr |= UART_MR2_BITS_PER_CHAR_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) mr |= UART_MR2_BITS_PER_CHAR_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* calculate stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mr |= UART_MR2_STOP_BIT_LEN_TWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mr |= UART_MR2_STOP_BIT_LEN_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* set parity, bits per char, and stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) msm_write(port, mr, UART_MR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* calculate and set hardware flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) mr = msm_read(port, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mr |= UART_MR1_CTS_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) mr |= UART_MR1_RX_RDY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) msm_write(port, mr, UART_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* Configure status bits to ignore based on termio flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) port->read_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) port->read_status_mask |= UART_SR_RX_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* Try to use DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) msm_start_rx_dma(msm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static const char *msm_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return "MSM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static void msm_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct resource *uart_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (unlikely(!uart_resource))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) size = resource_size(uart_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) release_mem_region(port->mapbase, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static int msm_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct resource *uart_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (unlikely(!uart_resource))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) size = resource_size(uart_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (!request_mem_region(port->mapbase, size, "msm_serial"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) port->membase = ioremap(port->mapbase, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!port->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto fail_release_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) fail_release_port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) release_mem_region(port->mapbase, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static void msm_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) port->type = PORT_MSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret = msm_request_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (unlikely(port->irq != ser->irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static void msm_power(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) clk_prepare_enable(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) clk_prepare_enable(msm_port->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) clk_disable_unprepare(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) clk_disable_unprepare(msm_port->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) pr_err("msm_serial: Unknown PM state %d\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static int msm_poll_get_char_single(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return msm_read(port, rf_reg) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static int msm_poll_get_char_dm(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static u32 slop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) unsigned char *sp = (unsigned char *)&slop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* Check if a previous read had more than one char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) c = sp[sizeof(slop) - count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* Or if FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * If RX packing buffer has less than a word, force stale to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * push contents into RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) count = msm_read(port, UARTDM_RXFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) slop = msm_read(port, UARTDM_RF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) c = sp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) msm_write(port, 0xFFFFFF, UARTDM_DMRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) UART_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) c = NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* FIFO has a word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) slop = msm_read(port, UARTDM_RF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) c = sp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) count = sizeof(slop) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static int msm_poll_get_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) imr = msm_read(port, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) msm_write(port, 0, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) c = msm_poll_get_char_dm(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) c = msm_poll_get_char_single(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) msm_write(port, imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static void msm_poll_put_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) struct msm_port *msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) imr = msm_read(port, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) msm_write(port, 0, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (msm_port->is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) msm_reset_dm_count(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* Wait until FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /* Write a character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Wait until FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) msm_write(port, imr, UART_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static struct uart_ops msm_uart_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .tx_empty = msm_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .set_mctrl = msm_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .get_mctrl = msm_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .stop_tx = msm_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .start_tx = msm_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .stop_rx = msm_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .enable_ms = msm_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .break_ctl = msm_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .startup = msm_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .shutdown = msm_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .set_termios = msm_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .type = msm_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .release_port = msm_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .request_port = msm_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .config_port = msm_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .verify_port = msm_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .pm = msm_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .poll_get_char = msm_poll_get_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .poll_put_char = msm_poll_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static struct msm_port msm_uart_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .ops = &msm_uart_pops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .flags = UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .fifosize = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .line = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .ops = &msm_uart_pops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .flags = UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .fifosize = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .line = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .ops = &msm_uart_pops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .flags = UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .fifosize = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .line = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define UART_NR ARRAY_SIZE(msm_uart_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static inline struct uart_port *msm_get_port_from_line(unsigned int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return &msm_uart_ports[line].uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #ifdef CONFIG_SERIAL_MSM_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static void __msm_console_write(struct uart_port *port, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) unsigned int count, bool is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) int num_newlines = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) bool replaced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) void __iomem *tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) tf = port->membase + UARTDM_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) tf = port->membase + UART_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* Account for newlines that will get a carriage return added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (s[i] == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) num_newlines++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) count += num_newlines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (port->sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) locked = spin_trylock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) msm_reset_dm_count(port, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) while (i < count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned int num_chars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) char buf[4] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (is_uartdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) num_chars = min(count - i, (unsigned int)sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) num_chars = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) for (j = 0; j < num_chars; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) char c = *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (c == '\n' && !replaced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) buf[j] = '\r';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) replaced = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (j < num_chars) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) buf[j] = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) s++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) replaced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) iowrite32_rep(tf, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) i += num_chars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static void msm_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct msm_port *msm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) BUG_ON(co->index < 0 || co->index >= UART_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) port = msm_get_port_from_line(co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) __msm_console_write(port, s, count, msm_port->is_uartdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int msm_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (unlikely(co->index >= UART_NR || co->index < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) port = msm_get_port_from_line(co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (unlikely(!port->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) msm_init_clock(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pr_info("msm_serial: console setup on port #%d\n", port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) msm_serial_early_write(struct console *con, const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) __msm_console_write(&dev->port, s, n, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) device->con->write = msm_serial_early_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) msm_serial_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) __msm_console_write(&dev->port, s, n, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) msm_serial_early_console_setup_dm(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) device->con->write = msm_serial_early_write_dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) msm_serial_early_console_setup_dm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static struct uart_driver msm_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static struct console msm_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .name = "ttyMSM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .write = msm_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .setup = msm_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .data = &msm_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define MSM_CONSOLE (&msm_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define MSM_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static struct uart_driver msm_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .driver_name = "msm_serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .dev_name = "ttyMSM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .nr = UART_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .cons = MSM_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static const struct of_device_id msm_uartdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static int msm_serial_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct msm_port *msm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct resource *resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int irq, line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) line = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (line < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) line = atomic_inc_return(&msm_uart_next_id) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (unlikely(line < 0 || line >= UART_NR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) port = msm_get_port_from_line(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) msm_port = UART_TO_MSM(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) id = of_match_device(msm_uartdm_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) msm_port->is_uartdm = (unsigned long)id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) msm_port->is_uartdm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) msm_port->clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (IS_ERR(msm_port->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return PTR_ERR(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (msm_port->is_uartdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (IS_ERR(msm_port->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return PTR_ERR(msm_port->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) port->uartclk = clk_get_rate(msm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (unlikely(!resource))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) port->mapbase = resource->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (unlikely(irq < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) port->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) platform_set_drvdata(pdev, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return uart_add_one_port(&msm_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static int msm_serial_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct uart_port *port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) uart_remove_one_port(&msm_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const struct of_device_id msm_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) { .compatible = "qcom,msm-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) { .compatible = "qcom,msm-uartdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) MODULE_DEVICE_TABLE(of, msm_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static int __maybe_unused msm_serial_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct msm_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) uart_suspend_port(&msm_uart_driver, &port->uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static int __maybe_unused msm_serial_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) struct msm_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) uart_resume_port(&msm_uart_driver, &port->uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static const struct dev_pm_ops msm_serial_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static struct platform_driver msm_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .remove = msm_serial_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .probe = msm_serial_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .name = "msm_serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .pm = &msm_serial_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .of_match_table = msm_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static int __init msm_serial_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ret = uart_register_driver(&msm_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ret = platform_driver_register(&msm_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) uart_unregister_driver(&msm_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pr_info("msm_serial: driver initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static void __exit msm_serial_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) platform_driver_unregister(&msm_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) uart_unregister_driver(&msm_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) module_init(msm_serial_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) module_exit(msm_serial_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) MODULE_AUTHOR("Robert Love <rlove@google.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) MODULE_DESCRIPTION("Driver for msm7x serial device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags