^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPS2 UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Vladimir Murzin <vladimir.murzin@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TODO: support for SysRq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SERIAL_NAME "ttyMPS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_NAME "mps2-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAKE_NAME(x) (DRIVER_NAME # x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UARTn_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UARTn_STATE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UARTn_STATE_TX_FULL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UARTn_STATE_RX_FULL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UARTn_STATE_TX_OVERRUN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UARTn_STATE_RX_OVERRUN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UARTn_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UARTn_CTRL_TX_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UARTn_CTRL_RX_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UARTn_CTRL_TX_INT_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UARTn_CTRL_RX_INT_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UARTn_INT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UARTn_INT_TX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UARTn_INT_RX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UARTn_INT_TX_OVERRUN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UARTn_INT_RX_OVERRUN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UARTn_BAUDDIV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UARTn_BAUDDIV_MASK GENMASK(20, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Helpers to make typical enable/disable operations more readable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) UARTn_CTRL_TX_INT_ENABLE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) UARTn_CTRL_RX_INT_ENABLE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MPS2_MAX_PORTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UART_PORT_COMBINED_IRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mps2_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return container_of(port, struct mps2_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mps2_uart_port *mps_port = to_mps2_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writeb(val, mps_port->port.membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct mps2_uart_port *mps_port = to_mps2_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return readb(mps_port->port.membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mps2_uart_port *mps_port = to_mps2_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel_relaxed(val, mps_port->port.membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned int mps2_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 status = mps2_uart_read8(port, UARTn_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void mps2_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 control = mps2_uart_read8(port, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) control &= ~UARTn_CTRL_TX_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mps2_uart_write8(port, control, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void mps2_uart_tx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mps2_uart_write8(port, port->x_char, UARTn_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (uart_circ_empty(xmit) || uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mps2_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void mps2_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 control = mps2_uart_read8(port, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) control |= UARTn_CTRL_TX_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mps2_uart_write8(port, control, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * We've just unmasked the TX IRQ and now slow-starting via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * polling; if there is enough data to fill up the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * write buffer in one go, the TX IRQ should assert, at which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * point we switch to fully interrupt-driven TX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mps2_uart_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void mps2_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 control = mps2_uart_read8(port, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) control &= ~UARTn_CTRL_RX_GRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mps2_uart_write8(port, control, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void mps2_uart_rx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static irqreturn_t mps2_uart_rxirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct uart_port *port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 irqflag = mps2_uart_read8(port, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (unlikely(!(irqflag & UARTn_INT_RX)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mps2_uart_rx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static irqreturn_t mps2_uart_txirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct uart_port *port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 irqflag = mps2_uart_read8(port, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (unlikely(!(irqflag & UARTn_INT_TX)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mps2_uart_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) irqreturn_t handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct uart_port *port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 irqflag = mps2_uart_read8(port, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (irqflag & UARTn_INT_RX_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * It's never been seen in practice and it never *should* happen since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * we check if there is enough room in TX buffer before sending data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * So we keep this check in case something suspicious has happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (irqflag & UARTn_INT_TX_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static irqreturn_t mps2_uart_combinedirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (mps2_uart_rxirq(irq, data) == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (mps2_uart_txirq(irq, data) == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (mps2_uart_oerrirq(irq, data) == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mps2_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct mps2_uart_port *mps_port = to_mps2_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 control = mps2_uart_read8(port, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mps2_uart_write8(port, control, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = request_irq(port->irq, mps2_uart_combinedirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MAKE_NAME(-combined), mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(port->dev, "failed to register combinedirq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MAKE_NAME(-overrun), mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MAKE_NAME(-rx), mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto err_free_oerrirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MAKE_NAME(-tx), mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(port->dev, "failed to register txirq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto err_free_rxirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mps2_uart_write8(port, control, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err_free_rxirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) free_irq(mps_port->rx_irq, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) err_free_oerrirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) free_irq(port->irq, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void mps2_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct mps2_uart_port *mps_port = to_mps2_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 control = mps2_uart_read8(port, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mps2_uart_write8(port, control, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!(mps_port->flags & UART_PORT_COMBINED_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) free_irq(mps_port->rx_irq, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) free_irq(mps_port->tx_irq, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) free_irq(port->irq, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int baud, bauddiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) termios->c_cflag &= ~(CRTSCTS | CMSPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) termios->c_cflag &= ~CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) termios->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) termios->c_cflag &= ~PARENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) termios->c_cflag &= ~CSTOPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) baud = uart_get_baud_rate(port, termios, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DIV_ROUND_CLOSEST(port->uartclk, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const char *mps2_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void mps2_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int mps2_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void mps2_uart_config_port(struct uart_port *port, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) port->type = PORT_MPS2UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct uart_ops mps2_uart_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .tx_empty = mps2_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .set_mctrl = mps2_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .get_mctrl = mps2_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .stop_tx = mps2_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .start_tx = mps2_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .stop_rx = mps2_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .break_ctl = mps2_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .startup = mps2_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .shutdown = mps2_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .set_termios = mps2_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .type = mps2_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .release_port = mps2_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .request_port = mps2_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .config_port = mps2_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .verify_port = mps2_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static DEFINE_IDR(ports_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void mps2_uart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mps2_uart_write8(port, ch, UARTn_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct mps2_uart_port *mps_port = idr_find(&ports_idr, co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct uart_port *port = &mps_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uart_console_write(port, s, cnt, mps2_uart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int mps2_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct mps2_uart_port *mps_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mps_port = idr_find(&ports_idr, co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!mps_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct uart_driver mps2_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct console mps2_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = SERIAL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .write = mps2_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .setup = mps2_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .data = &mps2_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void mps2_early_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writeb((unsigned char)ch, port->membase + UARTn_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void mps2_early_write(struct console *con, const char *s, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uart_console_write(&dev->port, s, n, mps2_early_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int __init mps2_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) device->con->write = mps2_early_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define MPS2_SERIAL_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct uart_driver mps2_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .dev_name = SERIAL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .nr = MPS2_MAX_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .cons = MPS2_SERIAL_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mps2_of_get_port(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct mps2_uart_port *mps_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) id = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) id = idr_alloc_cyclic(&ports_idr, (void *)mps_port, 0, MPS2_MAX_PORTS, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) id = idr_alloc(&ports_idr, (void *)mps_port, id, MPS2_MAX_PORTS, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Only combined irq is presesnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (platform_irq_count(pdev) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mps_port->flags |= UART_PORT_COMBINED_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mps_port->port.line = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int mps2_init_port(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct mps2_uart_port *mps_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (IS_ERR(mps_port->port.membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return PTR_ERR(mps_port->port.membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mps_port->port.mapbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mps_port->port.mapsize = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mps_port->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mps_port->port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mps_port->port.fifosize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mps_port->port.ops = &mps2_uart_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mps_port->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mps_port->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(mps_port->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return PTR_ERR(mps_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = clk_prepare_enable(mps_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mps_port->port.uartclk = clk_get_rate(mps_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk_disable_unprepare(mps_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mps_port->port.irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mps_port->rx_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mps_port->tx_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mps_port->port.irq = platform_get_irq(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int mps2_serial_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct mps2_uart_port *mps_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mps_port = devm_kzalloc(&pdev->dev, sizeof(struct mps2_uart_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!mps_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = mps2_of_get_port(pdev, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = mps2_init_port(pdev, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) platform_set_drvdata(pdev, mps_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct of_device_id mps2_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { .compatible = "arm,mps2-uart", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static struct platform_driver mps2_serial_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .probe = mps2_serial_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .of_match_table = of_match_ptr(mps2_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int __init mps2_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = uart_register_driver(&mps2_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = platform_driver_register(&mps2_serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) uart_unregister_driver(&mps2_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) arch_initcall(mps2_uart_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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