^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * FIXME According to the usermanual the status bits in the status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * are only updated when the peripherals access the FIFO and not when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * CPU access them. So since we use this bits to know when we stop writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and reading, they may not be updated in-time and a race condition may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * exists. But I haven't be able to prove this and I don't care. But if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * any problem arises, it might worth checking. The TX/RX FIFO Stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * registers should be used in addition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Update: Actually, they seem updated ... At least the bits we use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Maintainer : Sylvain Munaut <tnt@246tNt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Some of the code has been inspired/copied from the 2.4 code written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * by Dale Farnsworth <dfarnsworth@mvista.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Copyright (C) 2008 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * John Rigby <jrigby@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Added support for MPC5121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright (C) 2006 Secret Lab Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Grant Likely <grant.likely@secretlab.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Copyright (C) 2003 MontaVista, Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/mpc52xx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* We've been assigned a range on the "Low-density serial ports" major */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SERIAL_PSC_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SERIAL_PSC_MINOR 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Rem: - We use the read_status_mask as a shadow of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * psc->mpc52xx_psc_imr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * - It's important that is array is all zero on start as we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * use it to know if it's initialized or not ! If it's not sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * it's cleared, then a memset(...,0,...) should be added to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * the console_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* lookup table for matching device nodes to index numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void mpc52xx_uart_of_enumerate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Forward declaration of the interruption handling routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PSC fifo operations for isolating differences between 52xx and 512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct psc_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void (*fifo_init)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int (*raw_rx_rdy)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int (*raw_tx_rdy)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int (*rx_rdy)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int (*tx_rdy)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int (*tx_empty)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void (*stop_rx)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void (*start_tx)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void (*stop_tx)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void (*rx_clr_irq)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void (*tx_clr_irq)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void (*write_char)(struct uart_port *port, unsigned char c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned char (*read_char)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void (*cw_disable_ints)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void (*cw_restore_ints)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int (*set_baudrate)(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct ktermios *old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int (*clock_alloc)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void (*clock_relse)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int (*clock)(struct uart_port *port, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int (*fifoc_init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void (*fifoc_uninit)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void (*get_irq)(struct uart_port *, struct device_node *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irqreturn_t (*handle_irq)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 (*get_status)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 (*get_ipcr)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void (*command)(struct uart_port *port, u8 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*set_rts)(struct uart_port *port, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*enable_ms)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void (*set_sicr)(struct uart_port *port, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void (*set_imr)(struct uart_port *port, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 (*get_mr1)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* setting the prescaler and divisor reg is common for all chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 prescaler, unsigned int divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* select prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) out_8(&psc->ctur, divisor >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) out_8(&psc->ctlr, divisor & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static u16 mpc52xx_psc_get_status(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return in_be16(&PSC(port)->mpc52xx_psc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return in_8(&PSC(port)->mpc52xx_psc_ipcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out_8(&PSC(port)->command, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) out_8(&PSC(port)->mode, mr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) out_8(&PSC(port)->mode, mr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void mpc52xx_psc_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mpc52xx_psc __iomem *psc = PSC(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* clear D_*-bits by reading them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) in_8(&psc->mpc52xx_psc_ipcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* enable CTS and DCD as IPC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) out_be32(&PSC(port)->sicr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) out_be16(&PSC(port)->mpc52xx_psc_imr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return in_8(&PSC(port)->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifdef CONFIG_PPC_MPC52xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void mpc52xx_psc_fifo_init(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct mpc52xx_psc __iomem *psc = PSC(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) out_8(&fifo->rfcntl, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) out_be16(&fifo->rfalarm, 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) out_8(&fifo->tfcntl, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) out_be16(&fifo->tfalarm, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return in_be16(&PSC(port)->mpc52xx_psc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) & MPC52xx_PSC_SR_RXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return in_be16(&PSC(port)->mpc52xx_psc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) & MPC52xx_PSC_SR_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int mpc52xx_psc_rx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return in_be16(&PSC(port)->mpc52xx_psc_isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) & port->read_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) & MPC52xx_PSC_IMR_RXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int mpc52xx_psc_tx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return in_be16(&PSC(port)->mpc52xx_psc_isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) & port->read_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) & MPC52xx_PSC_IMR_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int mpc52xx_psc_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void mpc52xx_psc_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void mpc52xx_psc_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void mpc52xx_psc_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) baud = uart_get_baud_rate(port, new, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) port->uartclk / (32 * 0xffff) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) port->uartclk / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) divisor = (port->uartclk + 16 * baud) / (32 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* enable the /32 prescaler and set the divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u16 prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * ipb freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) baud = uart_get_baud_rate(port, new, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) port->uartclk / (32 * 0xffff) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) port->uartclk / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) divisor = (port->uartclk + 2 * baud) / (4 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* select the proper prescaler and set the divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * prefer high prescaler for more tolerance on low baudrates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (divisor > 0xffff || baud <= 115200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) divisor = (divisor + 4) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) prescaler = 0xdd00; /* /32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) prescaler = 0xff00; /* /4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mpc52xx_set_divisor(PSC(port), prescaler, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) port->irqflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) port->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* 52xx specific interrupt handler. The caller holds the port lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return mpc5xxx_uart_process_int(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct psc_ops mpc52xx_psc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .fifo_init = mpc52xx_psc_fifo_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .rx_rdy = mpc52xx_psc_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .tx_rdy = mpc52xx_psc_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .tx_empty = mpc52xx_psc_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .stop_rx = mpc52xx_psc_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .start_tx = mpc52xx_psc_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .stop_tx = mpc52xx_psc_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .write_char = mpc52xx_psc_write_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .read_char = mpc52xx_psc_read_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .set_baudrate = mpc5200_psc_set_baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .get_irq = mpc52xx_psc_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .handle_irq = mpc52xx_psc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .get_status = mpc52xx_psc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .get_ipcr = mpc52xx_psc_get_ipcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .command = mpc52xx_psc_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .set_mode = mpc52xx_psc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .set_rts = mpc52xx_psc_set_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .enable_ms = mpc52xx_psc_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .set_sicr = mpc52xx_psc_set_sicr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .set_imr = mpc52xx_psc_set_imr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .get_mr1 = mpc52xx_psc_get_mr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct psc_ops mpc5200b_psc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .fifo_init = mpc52xx_psc_fifo_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .rx_rdy = mpc52xx_psc_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .tx_rdy = mpc52xx_psc_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .tx_empty = mpc52xx_psc_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .stop_rx = mpc52xx_psc_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .start_tx = mpc52xx_psc_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .stop_tx = mpc52xx_psc_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .write_char = mpc52xx_psc_write_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .read_char = mpc52xx_psc_read_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .set_baudrate = mpc5200b_psc_set_baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .get_irq = mpc52xx_psc_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .handle_irq = mpc52xx_psc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .get_status = mpc52xx_psc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .get_ipcr = mpc52xx_psc_get_ipcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .command = mpc52xx_psc_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .set_mode = mpc52xx_psc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .set_rts = mpc52xx_psc_set_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .enable_ms = mpc52xx_psc_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .set_sicr = mpc52xx_psc_set_sicr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .set_imr = mpc52xx_psc_set_imr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .get_mr1 = mpc52xx_psc_get_mr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif /* CONFIG_PPC_MPC52xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* PSC FIFO Controller for mpc512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct psc_fifoc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 fifoc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 fifoc_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 fifoc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 fifoc_axe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 fifoc_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct psc_fifoc __iomem *psc_fifoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static unsigned int psc_fifoc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct clk *psc_fifoc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void mpc512x_psc_fifo_init(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* /32 prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) out_be32(&FIFO_512x(port)->txalarm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) out_be32(&FIFO_512x(port)->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) out_be32(&FIFO_512x(port)->rxalarm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) out_be32(&FIFO_512x(port)->rximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int mpc512x_psc_rx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return in_be32(&FIFO_512x(port)->rxsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) & in_be32(&FIFO_512x(port)->rximr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) & MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int mpc512x_psc_tx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return in_be32(&FIFO_512x(port)->txsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) & in_be32(&FIFO_512x(port)->tximr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) & MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int mpc512x_psc_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return in_be32(&FIFO_512x(port)->txsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) & MPC512x_PSC_FIFO_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void mpc512x_psc_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long rx_fifo_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void mpc512x_psc_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned long tx_fifo_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void mpc512x_psc_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned long tx_fifo_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) out_8(&FIFO_512x(port)->txdata_8, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static unsigned char mpc512x_psc_read_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return in_8(&FIFO_512x(port)->rxdata_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) port->read_status_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) in_be32(&FIFO_512x(port)->tximr) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) in_be32(&FIFO_512x(port)->rximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) out_be32(&FIFO_512x(port)->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) out_be32(&FIFO_512x(port)->rximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) out_be32(&FIFO_512x(port)->tximr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) (port->read_status_mask >> 16) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * Furthermore, it states that "After reset, the prescaler by 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * for the UART mode is selected", but the reset register value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * 0x0000 which means a /32 prescaler. This is wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * In reality using /32 prescaler doesn't work, as it is not supported!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Chapter 4.1 PSC in UART Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Calculate with a /16 prescaler here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* uartclk contains the ips freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) baud = uart_get_baud_rate(port, new, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) port->uartclk / (16 * 0xffff) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) divisor = (port->uartclk + 8 * baud) / (16 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* enable the /16 prescaler and set the divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Init PSC FIFO Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int __init mpc512x_psc_fifoc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* default error code, potentially overwritten by clock calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "fsl,mpc5121-psc-fifo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pr_err("%s: Can't find FIFOC node\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* backwards compat with device trees that lack clock specs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk = clk_get_sys(np->name, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pr_err("%s: Can't lookup FIFO clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto out_ofnode_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (clk_prepare_enable(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pr_err("%s: Can't enable FIFO clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) goto out_ofnode_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) psc_fifoc_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) psc_fifoc = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!psc_fifoc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pr_err("%s: Can't map FIFOC\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) psc_fifoc_irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (psc_fifoc_irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pr_err("%s: Can't get FIFOC irq\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) iounmap(psc_fifoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_disable_unprepare(psc_fifoc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) clk_put(psc_fifoc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) out_ofnode_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void __exit mpc512x_psc_fifoc_uninit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) iounmap(psc_fifoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* disable the clock, errors are not fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (psc_fifoc_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk_disable_unprepare(psc_fifoc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_put(psc_fifoc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) psc_fifoc_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* 512x specific interrupt handler. The caller holds the port lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned long fifoc_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int psc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Read pending PSC FIFOC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) fifoc_int = in_be32(&psc_fifoc->fifoc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Check if it is an interrupt for this port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) psc_num = (port->mapbase & 0xf00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (test_bit(psc_num, &fifoc_int) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) test_bit(psc_num + 16, &fifoc_int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return mpc5xxx_uart_process_int(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* called from within the .request_port() callback (allocation) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int mpc512x_psc_alloc_clock(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int psc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) psc_num = (port->mapbase & 0xf00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) clk = devm_clk_get(port->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(port->dev, "Failed to get MCLK!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(port->dev, "Failed to enable MCLK!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) psc_mclk_clk[psc_num] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) clk = devm_clk_get(port->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_err(port->dev, "Failed to get IPG clock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(port->dev, "Failed to enable IPG clock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) psc_ipg_clk[psc_num] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (psc_mclk_clk[psc_num]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) clk_disable_unprepare(psc_mclk_clk[psc_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) psc_mclk_clk[psc_num] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (psc_ipg_clk[psc_num]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) clk_disable_unprepare(psc_ipg_clk[psc_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) psc_ipg_clk[psc_num] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* called from within the .release_port() callback (release) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void mpc512x_psc_relse_clock(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int psc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) psc_num = (port->mapbase & 0xf00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) clk = psc_mclk_clk[psc_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) psc_mclk_clk[psc_num] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (psc_ipg_clk[psc_num]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clk_disable_unprepare(psc_ipg_clk[psc_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) psc_ipg_clk[psc_num] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* implementation of the .clock() callback (enable/disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int psc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct clk *psc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (uart_console(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) psc_num = (port->mapbase & 0xf00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) psc_clk = psc_mclk_clk[psc_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!psc_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(port->dev, "Failed to get PSC clock entry!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = clk_enable(psc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(port->dev, "Failed to enable MCLK!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) clk_disable(psc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) port->irqflags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) port->irq = psc_fifoc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static void mpc5125_psc_fifo_init(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* /32 prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) out_be32(&FIFO_5125(port)->txalarm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) out_be32(&FIFO_5125(port)->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) out_be32(&FIFO_5125(port)->rxalarm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) out_be32(&FIFO_5125(port)->rximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int mpc5125_psc_rx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return in_be32(&FIFO_5125(port)->rxsr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int mpc5125_psc_tx_rdy(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return in_be32(&FIFO_5125(port)->txsr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int mpc5125_psc_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void mpc5125_psc_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned long rx_fifo_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static void mpc5125_psc_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) unsigned long tx_fifo_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static void mpc5125_psc_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned long tx_fifo_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) out_8(&FIFO_5125(port)->txdata_8, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static unsigned char mpc5125_psc_read_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return in_8(&FIFO_5125(port)->rxdata_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) port->read_status_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) in_be32(&FIFO_5125(port)->tximr) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) in_be32(&FIFO_5125(port)->rximr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) out_be32(&FIFO_5125(port)->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) out_be32(&FIFO_5125(port)->rximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) out_be32(&FIFO_5125(port)->tximr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) (port->read_status_mask >> 16) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 prescaler, unsigned int divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* select prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) out_8(&psc->mpc52xx_psc_clock_select, prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) out_8(&psc->ctur, divisor >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) out_8(&psc->ctlr, divisor & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Calculate with a /16 prescaler here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* uartclk contains the ips freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) baud = uart_get_baud_rate(port, new, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) port->uartclk / (16 * 0xffff) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) divisor = (port->uartclk + 8 * baud) / (16 * baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* enable the /16 prescaler and set the divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * MPC5125 have compatible PSC FIFO Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * Special init not needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static u16 mpc5125_psc_get_status(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) out_8(&PSC_5125(port)->command, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) out_8(&PSC_5125(port)->mr1, mr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) out_8(&PSC_5125(port)->mr2, mr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void mpc5125_psc_set_rts(struct uart_port *port, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (state & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void mpc5125_psc_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct mpc5125_psc __iomem *psc = PSC_5125(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* clear D_*-bits by reading them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) in_8(&psc->mpc52xx_psc_ipcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* enable CTS and DCD as IPC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) out_be32(&PSC_5125(port)->sicr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static u8 mpc5125_psc_get_mr1(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return in_8(&PSC_5125(port)->mr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const struct psc_ops mpc5125_psc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .fifo_init = mpc5125_psc_fifo_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .rx_rdy = mpc5125_psc_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .tx_rdy = mpc5125_psc_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .tx_empty = mpc5125_psc_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .stop_rx = mpc5125_psc_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .start_tx = mpc5125_psc_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .stop_tx = mpc5125_psc_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .rx_clr_irq = mpc5125_psc_rx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .tx_clr_irq = mpc5125_psc_tx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .write_char = mpc5125_psc_write_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .read_char = mpc5125_psc_read_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .cw_disable_ints = mpc5125_psc_cw_disable_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .cw_restore_ints = mpc5125_psc_cw_restore_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .set_baudrate = mpc5125_psc_set_baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .clock_alloc = mpc512x_psc_alloc_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .clock_relse = mpc512x_psc_relse_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .clock = mpc512x_psc_endis_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .fifoc_init = mpc512x_psc_fifoc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .fifoc_uninit = mpc512x_psc_fifoc_uninit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .get_irq = mpc512x_psc_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .handle_irq = mpc512x_psc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .get_status = mpc5125_psc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .get_ipcr = mpc5125_psc_get_ipcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .command = mpc5125_psc_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .set_mode = mpc5125_psc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .set_rts = mpc5125_psc_set_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .enable_ms = mpc5125_psc_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .set_sicr = mpc5125_psc_set_sicr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .set_imr = mpc5125_psc_set_imr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .get_mr1 = mpc5125_psc_get_mr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const struct psc_ops mpc512x_psc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .fifo_init = mpc512x_psc_fifo_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .rx_rdy = mpc512x_psc_rx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .tx_rdy = mpc512x_psc_tx_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .tx_empty = mpc512x_psc_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .stop_rx = mpc512x_psc_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .start_tx = mpc512x_psc_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .stop_tx = mpc512x_psc_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .rx_clr_irq = mpc512x_psc_rx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .tx_clr_irq = mpc512x_psc_tx_clr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .write_char = mpc512x_psc_write_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .read_char = mpc512x_psc_read_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .cw_disable_ints = mpc512x_psc_cw_disable_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .cw_restore_ints = mpc512x_psc_cw_restore_ints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .set_baudrate = mpc512x_psc_set_baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .clock_alloc = mpc512x_psc_alloc_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .clock_relse = mpc512x_psc_relse_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .clock = mpc512x_psc_endis_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .fifoc_init = mpc512x_psc_fifoc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .fifoc_uninit = mpc512x_psc_fifoc_uninit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .get_irq = mpc512x_psc_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .handle_irq = mpc512x_psc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .get_status = mpc52xx_psc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .get_ipcr = mpc52xx_psc_get_ipcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .command = mpc52xx_psc_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .set_mode = mpc52xx_psc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .set_rts = mpc52xx_psc_set_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .enable_ms = mpc52xx_psc_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .set_sicr = mpc52xx_psc_set_sicr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .set_imr = mpc52xx_psc_set_imr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .get_mr1 = mpc52xx_psc_get_mr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #endif /* CONFIG_PPC_MPC512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const struct psc_ops *psc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* UART operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mpc52xx_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) psc_ops->set_rts(port, mctrl & TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) mpc52xx_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned int ret = TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u8 status = psc_ops->get_ipcr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!(status & MPC52xx_PSC_CTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!(status & MPC52xx_PSC_DCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) mpc52xx_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* port->lock taken by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) psc_ops->stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) mpc52xx_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* port->lock taken by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) psc_ops->start_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) mpc52xx_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* port->lock taken by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) psc_ops->stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mpc52xx_uart_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) psc_ops->enable_ms(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ctl == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) psc_ops->command(port, MPC52xx_PSC_START_BRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mpc52xx_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (psc_ops->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = psc_ops->clock(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Request IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = request_irq(port->irq, mpc52xx_uart_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) port->irqflags, "mpc52xx_psc_uart", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Reset/activate the port, clear and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) psc_ops->command(port, MPC52xx_PSC_RST_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) psc_ops->command(port, MPC52xx_PSC_RST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * According to Freescale's support the RST_TX command can produce a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * spike on the TX pin. So they recommend to delay "for one character".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * One millisecond should be enough for everyone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) psc_ops->fifo_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) mpc52xx_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Shut down the port. Leave TX active if on a console port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) psc_ops->command(port, MPC52xx_PSC_RST_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!uart_console(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) psc_ops->command(port, MPC52xx_PSC_RST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) port->read_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) psc_ops->set_imr(port, port->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (psc_ops->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) psc_ops->clock(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) psc_ops->cw_disable_ints(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Release interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) unsigned char mr1, mr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Prepare what we're gonna write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) mr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) switch (new->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (new->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (new->c_cflag & CMSPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mr1 |= MPC52xx_PSC_MODE_PARFORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* With CMSPAR, PARODD also means high parity (same as termios) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) mr1 |= (new->c_cflag & PARODD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mr1 |= MPC52xx_PSC_MODE_PARNONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (new->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) MPC52xx_PSC_MODE_ONE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (new->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mr1 |= MPC52xx_PSC_MODE_RXRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) mr2 |= MPC52xx_PSC_MODE_TXCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* Get the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* Do our best to flush TX & RX, so we don't lose anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* But we don't wait indefinitely ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) j = 5000000; /* Maximum wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* FIXME Can't receive chars since set_termios might be called at early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * boot for the console, all stuff is not yet ready to receive at that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * time and that just makes the kernel oops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) while (!mpc52xx_uart_tx_empty(port) && --j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (!j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) printk(KERN_ERR "mpc52xx_uart.c: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) "Unable to flush RX & TX fifos in-time in set_termios."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "Some chars may have been lost.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* Reset the TX & RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) psc_ops->command(port, MPC52xx_PSC_RST_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) psc_ops->command(port, MPC52xx_PSC_RST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Send new mode settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) psc_ops->set_mode(port, mr1, mr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) baud = psc_ops->set_baudrate(port, new, old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Update the per-port timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (UART_ENABLE_MS(port, new->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mpc52xx_uart_enable_ms(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* Reenable TX & RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* We're all set, release the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) mpc52xx_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * We keep using PORT_MPC52xx for historic reasons although it applies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * for MPC512x, too, but print "MPC5xxx" to not irritate users
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) mpc52xx_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (psc_ops->clock_relse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) psc_ops->clock_relse(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* remapped by us ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mpc52xx_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (port->flags & UPF_IOREMAP) /* Need to remap ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) port->membase = ioremap(port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) sizeof(struct mpc52xx_psc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto out_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (psc_ops->clock_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) err = psc_ops->clock_alloc(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) goto out_mapregion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) out_mapregion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) out_membase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mpc52xx_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if ((flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) && (mpc52xx_uart_request_port(port) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) port->type = PORT_MPC52xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if ((ser->irq != port->irq) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) (ser->io_type != UPIO_MEM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) (ser->baud_base != port->uartclk) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) (ser->iomem_base != (void *)port->mapbase) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) (ser->hub6 != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const struct uart_ops mpc52xx_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .tx_empty = mpc52xx_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .set_mctrl = mpc52xx_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .get_mctrl = mpc52xx_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .stop_tx = mpc52xx_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .start_tx = mpc52xx_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .stop_rx = mpc52xx_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .enable_ms = mpc52xx_uart_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .break_ctl = mpc52xx_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .startup = mpc52xx_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .shutdown = mpc52xx_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .set_termios = mpc52xx_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* .pm = mpc52xx_uart_pm, Not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .type = mpc52xx_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .release_port = mpc52xx_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .request_port = mpc52xx_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .config_port = mpc52xx_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .verify_port = mpc52xx_uart_verify_port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* Interrupt handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mpc52xx_uart_int_rx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) unsigned char ch, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* While we can read, do so ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) while (psc_ops->raw_rx_rdy(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* Get the char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ch = psc_ops->read_char(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* Handle sysreq char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* Store it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) status = psc_ops->get_status(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (status & (MPC52xx_PSC_SR_PE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) MPC52xx_PSC_SR_FE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) MPC52xx_PSC_SR_RB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (status & MPC52xx_PSC_SR_RB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) uart_handle_break(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) } else if (status & MPC52xx_PSC_SR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) else if (status & MPC52xx_PSC_SR_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* Clear error condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) tty_insert_flip_char(tport, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (status & MPC52xx_PSC_SR_OE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * Overrun is special, since it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * reported immediately, and doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * affect the current character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return psc_ops->raw_rx_rdy(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) mpc52xx_uart_int_tx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* Process out of band chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) psc_ops->write_char(port, port->x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Nothing to do ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mpc52xx_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Send chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) while (psc_ops->raw_tx_rdy(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) psc_ops->write_char(port, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Maybe we're done after all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) mpc52xx_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) mpc5xxx_uart_process_int(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned long pass = ISR_PASS_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned int keepgoing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* While we have stuff to do, we continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* If we don't find anything to do, we stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) keepgoing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) psc_ops->rx_clr_irq(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (psc_ops->rx_rdy(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) keepgoing |= mpc52xx_uart_int_rx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) psc_ops->tx_clr_irq(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (psc_ops->tx_rdy(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) keepgoing |= mpc52xx_uart_int_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) status = psc_ops->get_ipcr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (status & MPC52xx_PSC_D_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (status & MPC52xx_PSC_D_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Limit number of iteration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!(--pass))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) keepgoing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) } while (keepgoing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) mpc52xx_uart_int(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ret = psc_ops->handle_irq(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* Console ( if applicable ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) mpc52xx_console_get_options(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) int *baud, int *parity, int *bits, int *flow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) unsigned char mr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* Read the mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) mr1 = psc_ops->get_mr1(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* CT{U,L}R are write-only ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* Parse them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) case MPC52xx_PSC_MODE_5_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) *bits = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) case MPC52xx_PSC_MODE_6_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) *bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) case MPC52xx_PSC_MODE_7_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) *bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) case MPC52xx_PSC_MODE_8_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) *bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (mr1 & MPC52xx_PSC_MODE_PARNONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) *parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct uart_port *port = &mpc52xx_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) psc_ops->cw_disable_ints(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* Wait the TX buffer to be empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) j = 5000000; /* Maximum wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) while (!mpc52xx_uart_tx_empty(port) && --j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* Write all the chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) for (i = 0; i < count; i++, s++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* Line return handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (*s == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) psc_ops->write_char(port, '\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* Send the char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) psc_ops->write_char(port, *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* Wait the TX buffer to be empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) j = 20000; /* Maximum wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) while (!mpc52xx_uart_tx_empty(port) && --j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* Restore interrupt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) psc_ops->cw_restore_ints(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) mpc52xx_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct uart_port *port = &mpc52xx_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct device_node *np = mpc52xx_uart_nodes[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) unsigned int uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) co, co->index, options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) pr_debug("PSC%x out of range\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pr_debug("PSC%x not found in device tree\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) pr_debug("Console on ttyPSC%x is %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) co->index, mpc52xx_uart_nodes[co->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* Fetch register locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pr_debug("Could not get resources for PSC%x\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) uartclk = mpc5xxx_get_bus_frequency(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (uartclk == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) pr_debug("Could not find uart clock frequency!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Basic port init. Needed since we use some uart_??? func before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * real init for early access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) port->uartclk = uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) port->ops = &mpc52xx_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) port->mapbase = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) port->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (port->membase == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) (void *)port->mapbase, port->membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) port->irq, port->uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Setup the port parameters accoding to options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) baud, bits, parity, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static struct uart_driver mpc52xx_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static struct console mpc52xx_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .name = "ttyPSC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .write = mpc52xx_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .setup = mpc52xx_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .data = &mpc52xx_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) mpc52xx_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) mpc52xx_uart_of_enumerate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) register_console(&mpc52xx_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) console_initcall(mpc52xx_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define MPC52xx_PSC_CONSOLE &mpc52xx_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define MPC52xx_PSC_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* UART Driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static struct uart_driver mpc52xx_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .driver_name = "mpc52xx_psc_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .dev_name = "ttyPSC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .major = SERIAL_PSC_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .minor = SERIAL_PSC_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .nr = MPC52xx_PSC_MAXNUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .cons = MPC52xx_PSC_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* OF Platform Driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static const struct of_device_id mpc52xx_uart_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #ifdef CONFIG_PPC_MPC52xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* binding used by old lite5200 device trees: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* binding used by efika: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static int mpc52xx_uart_of_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) int idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) unsigned int uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct uart_port *port = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Check validity & presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (idx >= MPC52xx_PSC_MAXNUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pr_debug("Found %pOF assigned to ttyPSC%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) mpc52xx_uart_nodes[idx], idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* set the uart clock to the input clock of the psc, the different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * prescalers are taken into account in the set_baudrate() methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * of the respective chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (uartclk == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* Init the port structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) port = &mpc52xx_uart_ports[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) port->uartclk = uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) port->fifosize = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) port->flags = UPF_BOOT_AUTOCONF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) (uart_console(port) ? 0 : UPF_IOREMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) port->line = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) port->ops = &mpc52xx_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) port->dev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* Search for IRQ and mapbase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ret = of_address_to_resource(op->dev.of_node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) port->mapbase = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (!port->mapbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) psc_ops->get_irq(port, op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (port->irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_dbg(&op->dev, "Could not get irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) (void *)port->mapbase, port->irq, port->uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* Add the port to the uart sub-system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ret = uart_add_one_port(&mpc52xx_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) platform_set_drvdata(op, (void *)port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) mpc52xx_uart_of_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) struct uart_port *port = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) uart_remove_one_port(&mpc52xx_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct uart_port *port = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) uart_suspend_port(&mpc52xx_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) mpc52xx_uart_of_resume(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct uart_port *port = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) uart_resume_port(&mpc52xx_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) mpc52xx_uart_of_assign(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* Find the first free PSC number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (mpc52xx_uart_nodes[i] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) of_node_get(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) mpc52xx_uart_nodes[i] = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) mpc52xx_uart_of_enumerate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static int enum_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (enum_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* Assign index to each PSC in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) for_each_matching_node(np, mpc52xx_uart_of_match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) match = of_match_node(mpc52xx_uart_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) psc_ops = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) mpc52xx_uart_of_assign(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) enum_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (mpc52xx_uart_nodes[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) pr_debug("%pOF assigned to ttyPSC%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) mpc52xx_uart_nodes[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static struct platform_driver mpc52xx_uart_of_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .probe = mpc52xx_uart_of_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .remove = mpc52xx_uart_of_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .suspend = mpc52xx_uart_of_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .resume = mpc52xx_uart_of_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .name = "mpc52xx-psc-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .of_match_table = mpc52xx_uart_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) mpc52xx_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ret = uart_register_driver(&mpc52xx_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) __FILE__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) mpc52xx_uart_of_enumerate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * Map the PSC FIFO Controller and init if on MPC512x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (psc_ops && psc_ops->fifoc_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ret = psc_ops->fifoc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ret = platform_driver_register(&mpc52xx_uart_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) __FILE__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) goto err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) err_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (psc_ops && psc_ops->fifoc_uninit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) psc_ops->fifoc_uninit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) uart_unregister_driver(&mpc52xx_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) mpc52xx_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (psc_ops->fifoc_uninit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) psc_ops->fifoc_uninit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) platform_driver_unregister(&mpc52xx_uart_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) uart_unregister_driver(&mpc52xx_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) module_init(mpc52xx_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) module_exit(mpc52xx_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags