^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USIO_NAME "mlb-usio-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USIO_UART_DEV_NAME "ttyUSI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MLB_USIO_REG_SMR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MLB_USIO_REG_SCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MLB_USIO_REG_ESCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MLB_USIO_REG_SSR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MLB_USIO_REG_DR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MLB_USIO_REG_BGR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MLB_USIO_REG_FCR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MLB_USIO_REG_FBYTE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MLB_USIO_SMR_SOE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MLB_USIO_SMR_SBL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MLB_USIO_SCR_TXE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MLB_USIO_SCR_RXE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MLB_USIO_SCR_TBIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MLB_USIO_SCR_TIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MLB_USIO_SCR_RIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MLB_USIO_SCR_UPCL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MLB_USIO_ESCR_L_8BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MLB_USIO_ESCR_L_5BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MLB_USIO_ESCR_L_6BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MLB_USIO_ESCR_L_7BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MLB_USIO_ESCR_P BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MLB_USIO_ESCR_PEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MLB_USIO_ESCR_FLWEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MLB_USIO_SSR_TBI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MLB_USIO_SSR_TDRE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MLB_USIO_SSR_RDRF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MLB_USIO_SSR_ORE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MLB_USIO_SSR_FRE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MLB_USIO_SSR_PE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MLB_USIO_SSR_REC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MLB_USIO_SSR_BRK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MLB_USIO_FCR_FE1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MLB_USIO_FCR_FE2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MLB_USIO_FCR_FCL1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MLB_USIO_FCR_FCL2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MLB_USIO_FCR_FSET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MLB_USIO_FCR_FTIE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MLB_USIO_FCR_FDRQ BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MLB_USIO_FCR_FRIIE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void mlb_usio_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void mlb_usio_tx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writeb(readb(port->membase + MLB_USIO_REG_SCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writew(port->x_char, port->membase + MLB_USIO_REG_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mlb_usio_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) count = port->fifosize -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mlb_usio_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void mlb_usio_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!(fcr & MLB_USIO_FCR_FDRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mlb_usio_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void mlb_usio_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void mlb_usio_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writeb(readb(port->membase + MLB_USIO_REG_SCR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void mlb_usio_rx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct tty_port *ttyport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) char ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int max_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) while (max_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) status = readb(port->membase + MLB_USIO_REG_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!(status & MLB_USIO_SSR_RDRF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MLB_USIO_SSR_PE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ch = readw(port->membase + MLB_USIO_REG_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) uart_insert_char(port, status, MLB_USIO_SSR_ORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (status & MLB_USIO_SSR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (status & MLB_USIO_SSR_ORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) status &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (status & MLB_USIO_SSR_BRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (status & MLB_USIO_SSR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (status & MLB_USIO_SSR_FRE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uart_insert_char(port, status, MLB_USIO_SSR_ORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writeb(readb(port->membase + MLB_USIO_REG_SSR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MLB_USIO_SSR_REC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) port->membase + MLB_USIO_REG_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writew(readw(port->membase + MLB_USIO_REG_FCR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) tty_flip_buffer_push(ttyport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mlb_usio_rx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mlb_usio_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static unsigned int mlb_usio_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int mlb_usio_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const char *portname = to_platform_device(port->dev)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret, index = port->line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned char escr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0, portname, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0, portname, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) free_irq(mlb_usio_irq[index][RX], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) escr = readb(port->membase + MLB_USIO_REG_ESCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) escr |= MLB_USIO_ESCR_FLWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writeb(0, port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writeb(escr, port->membase + MLB_USIO_REG_ESCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writew(0, port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writew(0, port->membase + MLB_USIO_REG_FBYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void mlb_usio_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int index = port->line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) free_irq(mlb_usio_irq[index][RX], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) free_irq(mlb_usio_irq[index][TX], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void mlb_usio_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct ktermios *termios, struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int escr, smr = MLB_USIO_SMR_SOE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long flags, baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) escr = MLB_USIO_ESCR_L_5BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) escr = MLB_USIO_ESCR_L_6BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) escr = MLB_USIO_ESCR_L_7BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) escr = MLB_USIO_ESCR_L_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) smr |= MLB_USIO_SMR_SBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) escr |= MLB_USIO_ESCR_PEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) escr |= MLB_USIO_ESCR_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Set hard flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (termios->c_cflag & CRTSCTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) escr |= MLB_USIO_ESCR_FLWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (baud > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) quot = port->uartclk / baud - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) quot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MLB_USIO_SSR_TDRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) port->ignore_status_mask |= MLB_USIO_SSR_ORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writeb(0, port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writew(0, port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writeb(smr, port->membase + MLB_USIO_REG_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) writeb(escr, port->membase + MLB_USIO_REG_ESCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writew(quot, port->membase + MLB_USIO_REG_BGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writew(0, port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) port->membase + MLB_USIO_REG_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writew(0, port->membase + MLB_USIO_REG_FBYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char *mlb_usio_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void mlb_usio_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) port->type = PORT_MLB_USIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct uart_ops mlb_usio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .tx_empty = mlb_usio_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .set_mctrl = mlb_usio_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .get_mctrl = mlb_usio_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .stop_tx = mlb_usio_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .start_tx = mlb_usio_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .stop_rx = mlb_usio_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .enable_ms = mlb_usio_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .break_ctl = mlb_usio_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .startup = mlb_usio_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .shutdown = mlb_usio_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .set_termios = mlb_usio_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .type = mlb_usio_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .config_port = mlb_usio_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void mlb_usio_console_putchar(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writew(c, port->membase + MLB_USIO_REG_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void mlb_usio_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct uart_port *port = &mlb_usio_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uart_console_write(port, s, count, mlb_usio_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int __init mlb_usio_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) port = &mlb_usio_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) flow = 'r';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct uart_driver mlb_usio_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct console mlb_usio_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = USIO_UART_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .write = mlb_usio_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .setup = mlb_usio_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .data = &mlb_usio_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int __init mlb_usio_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) register_console(&mlb_usio_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) console_initcall(mlb_usio_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void mlb_usio_early_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct earlycon_device *dev = co->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int __init mlb_usio_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) device->con->write = mlb_usio_early_console_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mlb_usio_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define USIO_CONSOLE (&mlb_usio_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define USIO_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct uart_driver mlb_usio_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .driver_name = USIO_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .dev_name = USIO_UART_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .cons = USIO_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .nr = CONFIG_SERIAL_MILBEAUT_USIO_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int mlb_usio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk *clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(&pdev->dev, "Missing clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(&pdev->dev, "Clock enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) of_property_read_u32(pdev->dev.of_node, "index", &index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) port = &mlb_usio_ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) port->private_data = (void *)clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_err(&pdev->dev, "Missing regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) port->membase = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = platform_get_irq_byname(pdev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mlb_usio_irq[index][RX] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = platform_get_irq_byname(pdev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mlb_usio_irq[index][TX] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) port->irq = mlb_usio_irq[index][RX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) port->uartclk = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) port->fifosize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) port->iotype = UPIO_MEM32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) port->line = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) port->ops = &mlb_usio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = uart_add_one_port(&mlb_usio_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int mlb_usio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct uart_port *port = &mlb_usio_ports[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct clk *clk = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) uart_remove_one_port(&mlb_usio_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct of_device_id mlb_usio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { .compatible = "socionext,milbeaut-usio-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static struct platform_driver mlb_usio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .probe = mlb_usio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .remove = mlb_usio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = USIO_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .of_match_table = mlb_usio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int __init mlb_usio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int ret = uart_register_driver(&mlb_usio_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pr_err("%s: uart registration failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = platform_driver_register(&mlb_usio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uart_unregister_driver(&mlb_usio_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pr_err("%s: drv registration failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void __exit mlb_usio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) platform_driver_unregister(&mlb_usio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) uart_unregister_driver(&mlb_usio_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) module_init(mlb_usio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) module_exit(mlb_usio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MODULE_AUTHOR("SOCIONEXT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags