^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * mcf.c -- Freescale ColdFire UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/nettel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Some boards implement the DTR/DCD lines using GPIO lines, most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * don't. Dummy out the access macros for those that don't. Those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * that do should define these macros somewhere in there board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * specific inlude files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if !defined(mcf_getppdcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define mcf_getppdcd(p) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #if !defined(mcf_getppdtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define mcf_getppdtr(p) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #if !defined(mcf_setppdtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define mcf_setppdtr(p, v) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Local per-uart structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct mcf_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int sigs; /* Local copy of line sigs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned char imr; /* Local IMR mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static unsigned int mcf_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned int mcf_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int sigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0 : TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) sigs |= (pp->sigs & TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return sigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pp->sigs = sigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (sigs & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void mcf_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Enable Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Manually assert RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pp->imr |= MCFUART_UIR_TXREADY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writeb(pp->imr, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void mcf_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pp->imr &= ~MCFUART_UIR_TXREADY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writeb(pp->imr, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void mcf_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pp->imr &= ~MCFUART_UIR_RXREADY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writeb(pp->imr, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void mcf_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int mcf_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Reset UART, get it into known state... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Enable the UART transmitter and receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Enable RX interrupts now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pp->imr = MCFUART_UIR_RXREADY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writeb(pp->imr, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void mcf_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Disable all interrupts now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pp->imr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writeb(pp->imr, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Disable UART transmitter and receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int baud, baudclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #if defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int baudfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char mr1, mr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) baud = uart_get_baud_rate(port, termios, old, 0, 230400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #if defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) baudclk = (MCF_BUSCLK / baud) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case CS5: mr1 |= MCFUART_MR1_CS5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case CS6: mr1 |= MCFUART_MR1_CS6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case CS7: mr1 |= MCFUART_MR1_CS7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) default: mr1 |= MCFUART_MR1_CS8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (termios->c_cflag & CMSPAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mr1 |= MCFUART_MR1_PARITYMARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mr1 |= MCFUART_MR1_PARITYSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mr1 |= MCFUART_MR1_PARITYODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mr1 |= MCFUART_MR1_PARITYEVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mr1 |= MCFUART_MR1_PARITYNONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * FIXME: port->read_status_mask and port->ignore_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * need to be initialized based on termios settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mr2 |= MCFUART_MR2_STOP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mr2 |= MCFUART_MR2_STOP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mr1 |= MCFUART_MR1_RXRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mr2 |= MCFUART_MR2_TXCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg(port->dev, "Setting UART to RS485\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mr2 |= MCFUART_MR2_TXRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writeb(mr1, port->membase + MCFUART_UMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writeb(mr2, port->membase + MCFUART_UMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #if defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) port->membase + MCFUART_UCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void mcf_rx_chars(struct mcf_uart *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct uart_port *port = &pp->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned char status, ch, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ch = readb(port->membase + MCFUART_URB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (status & MCFUART_USR_RXERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writeb(MCFUART_UCR_CMDRESETERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (status & MCFUART_USR_RXBREAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else if (status & MCFUART_USR_RXPARITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else if (status & MCFUART_USR_RXOVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else if (status & MCFUART_USR_RXFRAMING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) status &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (status & MCFUART_USR_RXBREAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) else if (status & MCFUART_USR_RXPARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else if (status & MCFUART_USR_RXFRAMING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void mcf_tx_chars(struct mcf_uart *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct uart_port *port = &pp->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Send special char - probably flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writeb(port->x_char, port->membase + MCFUART_UTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (xmit->head == xmit->tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (xmit->head == xmit->tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pp->imr &= ~MCFUART_UIR_TXREADY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writeb(pp->imr, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Disable TX to negate RTS automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (port->rs485.flags & SER_RS485_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writeb(MCFUART_UCR_TXDISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) port->membase + MCFUART_UCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static irqreturn_t mcf_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct uart_port *port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) isr = readb(port->membase + MCFUART_UISR) & pp->imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (isr & MCFUART_UIR_RXREADY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mcf_rx_chars(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (isr & MCFUART_UIR_TXREADY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mcf_tx_chars(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void mcf_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) port->type = PORT_MCF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) port->fifosize = MCFUART_TXFIFOSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Clear mask, so no surprise interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writeb(0, port->membase + MCFUART_UIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "interrupt vector=%d\n", port->line, port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const char *mcf_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int mcf_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* UARTs always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void mcf_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Nothing to release... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Enable or disable the RS485 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned char mr1, mr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Get mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mr1 = readb(port->membase + MCFUART_UMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mr2 = readb(port->membase + MCFUART_UMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (rs485->flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_dbg(port->dev, "Setting UART to RS485\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Automatically negate RTS after TX completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mr2 |= MCFUART_MR2_TXRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_dbg(port->dev, "Setting UART to RS232\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mr2 &= ~MCFUART_MR2_TXRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writeb(mr1, port->membase + MCFUART_UMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writeb(mr2, port->membase + MCFUART_UMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) port->rs485 = *rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Define the basic serial functions we support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct uart_ops mcf_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .tx_empty = mcf_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .get_mctrl = mcf_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .set_mctrl = mcf_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .start_tx = mcf_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .stop_tx = mcf_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .stop_rx = mcf_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .break_ctl = mcf_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .startup = mcf_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .shutdown = mcf_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .set_termios = mcf_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .type = mcf_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .request_port = mcf_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .release_port = mcf_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .config_port = mcf_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .verify_port = mcf_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct mcf_uart mcf_ports[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #if defined(CONFIG_SERIAL_MCF_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int __init early_mcf_setup(struct mcf_platform_uart *platp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) port = &mcf_ports[i].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) port->line = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) port->type = PORT_MCF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) port->mapbase = platp[i].mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) port->membase = (platp[i].membase) ? platp[i].membase :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (unsigned char __iomem *) port->mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) port->iotype = SERIAL_IO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) port->irq = platp[i].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) port->uartclk = MCF_BUSCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) port->rs485_config = mcf_config_rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) port->ops = &mcf_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void mcf_console_putc(struct console *co, const char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct uart_port *port = &(mcf_ports + co->index)->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for (i = 0; (i < 0x10000); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writeb(c, port->membase + MCFUART_UTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (i = 0; (i < 0x10000); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void mcf_console_write(struct console *co, const char *s, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (; (count); count--, s++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mcf_console_putc(co, *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (*s == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mcf_console_putc(co, '\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int __init mcf_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int baud = CONFIG_SERIAL_MCF_BAUDRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) port = &mcf_ports[co->index].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (port->membase == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct uart_driver mcf_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static struct console mcf_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .write = mcf_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .setup = mcf_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .data = &mcf_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int __init mcf_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) register_console(&mcf_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) console_initcall(mcf_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define MCF_CONSOLE &mcf_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MCF_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif /* CONFIG_SERIAL_MCF_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Define the mcf UART driver structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct uart_driver mcf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .driver_name = "mcf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .dev_name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .major = TTY_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .minor = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .nr = MCF_MAXPORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .cons = MCF_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int mcf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) port = &mcf_ports[i].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) port->line = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) port->type = PORT_MCF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) port->mapbase = platp[i].mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) port->membase = (platp[i].membase) ? platp[i].membase :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) (unsigned char __iomem *) platp[i].mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) port->iotype = SERIAL_IO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) port->irq = platp[i].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) port->uartclk = MCF_BUSCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) port->ops = &mcf_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) port->rs485_config = mcf_config_rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MCF_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uart_add_one_port(&mcf_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int mcf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (i = 0; (i < MCF_MAXPORTS); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) port = &mcf_ports[i].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) uart_remove_one_port(&mcf_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct platform_driver mcf_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .probe = mcf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .remove = mcf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .name = "mcfuart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int __init mcf_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) printk("ColdFire internal UART serial driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) rc = uart_register_driver(&mcf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rc = platform_driver_register(&mcf_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uart_unregister_driver(&mcf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void __exit mcf_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) platform_driver_unregister(&mcf_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uart_unregister_driver(&mcf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) module_init(mcf_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) module_exit(mcf_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MODULE_DESCRIPTION("Freescale ColdFire UART driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MODULE_ALIAS("platform:mcfuart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /****************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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