^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on max3107.c, by Aavamobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAX310X_NAME "max310x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX310X_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX310X_MINOR 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX310X_UART_NRMAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* MAX310X register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX310X_RHR_REG (0x00) /* RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX310X_THR_REG (0x00) /* TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX310X_REG_05 (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX310X_MODE1_REG (0x09) /* MODE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX310X_LCR_REG (0x0b) /* LCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAX310X_XON1_REG (0x14) /* XON1 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAX310X_XON2_REG (0x15) /* XON2 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX310X_REG_1F (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Extended registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* IRQ register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* LSR register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Special character register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* MODE1 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* MODE2 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* LCR register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Word length bits table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * 00 -> 5 bit words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 01 -> 6 bit words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 10 -> 7 bit words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 11 -> 8 bit words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * STOP length bit table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 0 -> 1 stop bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * 1 -> 1-1.5 stop bits if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * word length is 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * 2 stop bits otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* IRDA register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Flow control trigger level register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* FIFO interrupt trigger level register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Flow control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * are used in conjunction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * XOFF2 for definition of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * special character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * SWFLOW bits 1 & 0 table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * 00 -> no transmitter flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * 01 -> receiver compares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * XON2 and XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * and controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * 10 -> receiver compares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * XON1 and XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * and controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * 11 -> receiver compares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * XON1, XON2, XOFF1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * XOFF2 and controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * SWFLOW bits 3 & 2 table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 00 -> no received flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * 01 -> transmitter generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * XON2 and XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 10 -> transmitter generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * XON1 and XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 11 -> transmitter generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * XON1, XON2, XOFF1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* PLL configuration register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Baud rate generator configuration register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Clock source register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Global commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MAX310X_EXTREG_ENBL (0xce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MAX310X_EXTREG_DSBL (0xcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Misc definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MAX310X_FIFO_SIZE (128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MAX310x_REV_MASK (0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MAX310X_WRITE_BIT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* MAX3107 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MAX3107_REV_ID (0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* MAX3109 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MAX3109_REV_ID (0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* MAX14830 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MAX14830_REV_ID (0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct max310x_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) char name[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 mode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int (*detect)(struct device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void (*power)(struct uart_port *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct max310x_one {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct work_struct tx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct work_struct md_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct work_struct rs_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 wr_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 rd_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 rx_buf[MAX310X_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define to_max310x_port(_port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) container_of(_port, struct max310x_one, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct max310x_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct max310x_devtype *devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct max310x_one p[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct uart_driver max310x_uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .driver_name = MAX310X_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .dev_name = "ttyMAX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .major = MAX310X_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .minor = MAX310X_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .nr = MAX310X_UART_NRMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static u8 max310x_port_read(struct uart_port *port, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct max310x_port *s = dev_get_drvdata(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) regmap_read(s->regmap, port->iobase + reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct max310x_port *s = dev_get_drvdata(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regmap_write(s->regmap, port->iobase + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct max310x_port *s = dev_get_drvdata(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int max3107_detect(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "%s ID 0x%02x does not match\n", s->devtype->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int max3108_detect(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* MAX3108 have not REV ID register, we just check default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * from clocksource register to make sure everything works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(dev, "%s not present\n", s->devtype->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int max3109_detect(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MAX310X_EXTREG_ENBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "%s ID 0x%02x does not match\n", s->devtype->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void max310x_power(struct uart_port *port, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) max310x_port_update(port, MAX310X_MODE1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MAX310X_MODE1_FORCESLEEP_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int max14830_detect(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MAX310X_EXTREG_ENBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "%s ID 0x%02x does not match\n", s->devtype->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void max14830_power(struct uart_port *port, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) max310x_port_update(port, MAX310X_BRGCFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MAX14830_BRGCFG_CLKDIS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct max310x_devtype max3107_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "MAX3107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .nr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .detect = max3107_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .power = max310x_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct max310x_devtype max3108_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .name = "MAX3108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .nr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .detect = max3108_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .power = max310x_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct max310x_devtype max3109_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .name = "MAX3109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .nr = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .detect = max3109_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .power = max310x_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct max310x_devtype max14830_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "MAX14830",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .nr = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .mode1 = MAX310X_MODE1_IRQSEL_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .detect = max14830_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .power = max14830_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) switch (reg & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case MAX310X_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case MAX310X_LSR_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case MAX310X_SPCHR_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case MAX310X_STS_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case MAX310X_TXFIFOLVL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case MAX310X_RXFIFOLVL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) switch (reg & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case MAX310X_RHR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case MAX310X_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case MAX310X_LSR_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case MAX310X_SPCHR_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case MAX310X_STS_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case MAX310X_TXFIFOLVL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case MAX310X_RXFIFOLVL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case MAX310X_GPIODATA_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case MAX310X_BRGDIVLSB_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case MAX310X_REG_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case MAX310X_REG_1F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static bool max310x_reg_precious(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) switch (reg & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case MAX310X_RHR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case MAX310X_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case MAX310X_SPCHR_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case MAX310X_STS_IRQSTS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int max310x_set_baud(struct uart_port *port, int baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Calculate the integer divisor first. Select a proper mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * in case if the requested baud is too high for the pre-defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * clocks frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) div = port->uartclk / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (div < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Mode x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) c = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mode = MAX310X_BRGCFG_4XMODE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else if (div < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Mode x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) c = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mode = MAX310X_BRGCFG_2XMODE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) c = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Calculate the divisor in accordance with the fraction coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) div /= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) F = c*baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Calculate the baud rate fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (div > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) frac = (16*(port->uartclk % F)) / F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Return the actual baud rate we just programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return (16*port->uartclk) / (c*(16*div + frac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int max310x_update_best_err(unsigned long f, long *besterr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Use baudrate 115200 for calculate error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) long err = f % (460800 * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if ((*besterr < 0) || (*besterr > err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *besterr = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned long freq, bool xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int div, clksrc, pllcfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) long besterr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned long fdiv, fmul, bestfreq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* First, update error without PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) max310x_update_best_err(freq, &besterr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Try all possible PLL dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (div = 1; (div <= 63) && besterr; div++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) fdiv = DIV_ROUND_CLOSEST(freq, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Try multiplier 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fmul = fdiv * 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if ((fdiv >= 500000) && (fdiv <= 800000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!max310x_update_best_err(fmul, &besterr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pllcfg = (0 << 6) | div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bestfreq = fmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Try multiplier 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) fmul = fdiv * 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if ((fdiv >= 850000) && (fdiv <= 1200000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!max310x_update_best_err(fmul, &besterr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pllcfg = (1 << 6) | div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bestfreq = fmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Try multiplier 96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fmul = fdiv * 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if ((fdiv >= 425000) && (fdiv <= 1000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!max310x_update_best_err(fmul, &besterr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pllcfg = (2 << 6) | div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) bestfreq = fmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Try multiplier 144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) fmul = fdiv * 144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if ((fdiv >= 390000) && (fdiv <= 667000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!max310x_update_best_err(fmul, &besterr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pllcfg = (3 << 6) | div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) bestfreq = fmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Configure clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Configure PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (pllcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) clksrc |= MAX310X_CLKSRC_PLL_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Wait for crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!(val & MAX310X_STS_CLKREADY_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_warn(dev, "clock is not stable yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return (int)bestfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct max310x_one *one = to_max310x_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct spi_transfer xfer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .tx_buf = &one->wr_header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .len = sizeof(one->wr_header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .tx_buf = txbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct max310x_one *one = to_max310x_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct spi_transfer xfer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .tx_buf = &one->rd_header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .len = sizeof(one->rd_header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .rx_buf = rxbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct max310x_one *one = to_max310x_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned int sts, ch, flag, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* We are just reading, happily ignoring any error conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Break condition, parity checking, framing errors -- they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * are all ignored. That means that we can do a batch-read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * There is a small opportunity for race if the RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * overruns while we're reading the buffer; the datasheets says
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * that the LSR register applies to the "current" character.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * That's also the reason why we cannot do batched reads when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * asked to check the individual statuses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) max310x_batch_read(port, one->rx_buf, rxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) port->icount.rx += rxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sts &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (sts & MAX310X_LSR_RXOVR_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) for (i = 0; i < (rxlen - 1); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * Handle the overrun case for the last character only, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * the RxFIFO overflow happens after it is pushed to the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * tail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) one->rx_buf[rxlen-1], flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (unlikely(rxlen >= port->fifosize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) port->icount.buf_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Ensure sanity of RX level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) rxlen = port->fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) while (rxlen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ch = max310x_port_read(port, MAX310X_RHR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (unlikely(sts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (sts & MAX310X_LSR_RXBRK_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else if (sts & MAX310X_LSR_RXPAR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else if (sts & MAX310X_LSR_FRERR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else if (sts & MAX310X_LSR_RXOVR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) sts &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (sts & MAX310X_LSR_RXBRK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else if (sts & MAX310X_LSR_RXPAR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) else if (sts & MAX310X_LSR_FRERR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) else if (sts & MAX310X_LSR_RXOVR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) flag = TTY_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (sts & port->ignore_status_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static void max310x_handle_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned int txlen, to_send, until_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (unlikely(port->x_char)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) max310x_port_write(port, MAX310X_THR_REG, port->x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (uart_circ_empty(xmit) || uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Get length of data pending in circular buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) to_send = uart_circ_chars_pending(xmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (likely(to_send)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Limit to size of TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) txlen = port->fifosize - txlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) to_send = (to_send > txlen) ? txlen : to_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (until_end < to_send) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* It's a circ buffer -- wrap around.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * We could do that in one SPI transaction, but meh. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) max310x_batch_write(port, xmit->buf, to_send - until_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* Add data to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) port->icount.tx += to_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void max310x_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct max310x_one *one = to_max310x_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) schedule_work(&one->tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct uart_port *port = &s->p[portno].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) irqreturn_t res = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned int ists, lsr, rxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Read IRQ status & RX FIFO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!ists && !rxlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) res = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ists & MAX310X_IRQ_CTS_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) uart_handle_cts_change(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) !!(lsr & MAX310X_LSR_CTS_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (rxlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) max310x_handle_rx(port, rxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ists & MAX310X_IRQ_TXEMPTY_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) max310x_start_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static irqreturn_t max310x_ist(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct max310x_port *s = (struct max310x_port *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (s->devtype->nr > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned int val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) WARN_ON_ONCE(regmap_read(s->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MAX310X_GLOBALIRQ_REG, &val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val = ((1 << s->devtype->nr) - 1) & ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (max310x_port_irq(s, 0) == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void max310x_tx_proc(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) max310x_handle_tx(&one->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static unsigned int max310x_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return lvl ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static unsigned int max310x_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* DCD and DSR are not wired and CTS/RTS is handled automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * so just indicate DSR and CAR asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static void max310x_md_proc(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) max310x_port_update(&one->port, MAX310X_MODE2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MAX310X_MODE2_LOOPBACK_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) (one->port.mctrl & TIOCM_LOOP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MAX310X_MODE2_LOOPBACK_BIT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct max310x_one *one = to_max310x_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) schedule_work(&one->md_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static void max310x_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) max310x_port_update(port, MAX310X_LCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MAX310X_LCR_TXBREAK_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static void max310x_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned int lcr = 0, flow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Mask termios capabilities we don't support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) termios->c_cflag &= ~CMSPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Word size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) lcr = MAX310X_LCR_LENGTH0_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) lcr = MAX310X_LCR_LENGTH1_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) lcr |= MAX310X_LCR_PARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!(termios->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) lcr |= MAX310X_LCR_EVENPARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Update LCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) max310x_port_write(port, MAX310X_LCR_REG, lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Set read status mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MAX310X_LSR_FRERR_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Set status ignore mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (termios->c_iflag & IGNBRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (!(termios->c_cflag & CREAD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MAX310X_LSR_RXOVR_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MAX310X_LSR_FRERR_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MAX310X_LSR_RXBRK_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Configure flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Disable transmitter before enabling AutoCTS or auto transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) max310x_port_update(port, MAX310X_MODE1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) MAX310X_MODE1_TXDIS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) MAX310X_MODE1_TXDIS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Enable AUTORTS and AUTOCTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MAX310X_FLOWCTRL_AUTORTS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (termios->c_iflag & IXON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MAX310X_FLOWCTRL_SWFLOWEN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (termios->c_iflag & IXOFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) port->status |= UPSTAT_AUTOXOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MAX310X_FLOWCTRL_SWFLOWEN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Enable transmitter after disabling AutoCTS and auto transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) max310x_port_update(port, MAX310X_MODE1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MAX310X_MODE1_TXDIS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Get baud rate generator configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) baud = uart_get_baud_rate(port, termios, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) port->uartclk / 16 / 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) port->uartclk / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Setup baudrate generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) baud = max310x_set_baud(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Update timeout according to new baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void max310x_rs_proc(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned int delay, mode1 = 0, mode2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) delay = (one->port.rs485.delay_rts_before_send << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) one->port.rs485.delay_rts_after_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (one->port.rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) max310x_port_update(&one->port, MAX310X_MODE1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) max310x_port_update(&one->port, MAX310X_MODE2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) MAX310X_MODE2_ECHOSUPR_BIT, mode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int max310x_rs485_config(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct serial_rs485 *rs485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct max310x_one *one = to_max310x_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if ((rs485->delay_rts_before_send > 0x0f) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) (rs485->delay_rts_after_send > 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) SER_RS485_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) memset(rs485->padding, 0, sizeof(rs485->padding));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) port->rs485 = *rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) schedule_work(&one->rs_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int max310x_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct max310x_port *s = dev_get_drvdata(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) s->devtype->power(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Configure MODE1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) max310x_port_update(port, MAX310X_MODE1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Configure MODE2 register & Reset FIFOs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) max310x_port_write(port, MAX310X_MODE2_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) max310x_port_update(port, MAX310X_MODE2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) MAX310X_MODE2_FIFORST_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clamp(port->rs485.delay_rts_after_send, 0U, 15U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) max310x_port_update(port, MAX310X_MODE1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) MAX310X_MODE1_TRNSCVCTRL_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) MAX310X_MODE1_TRNSCVCTRL_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) max310x_port_update(port, MAX310X_MODE2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) MAX310X_MODE2_ECHOSUPR_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) MAX310X_MODE2_ECHOSUPR_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* Configure flow control levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Flow control halt level 96, resume level 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) max310x_port_write(port, MAX310X_FLOWLVL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Clear IRQ status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) max310x_port_read(port, MAX310X_IRQSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Enable RX, TX, CTS change interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static void max310x_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct max310x_port *s = dev_get_drvdata(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) max310x_port_write(port, MAX310X_IRQEN_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) s->devtype->power(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static const char *max310x_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct max310x_port *s = dev_get_drvdata(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int max310x_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static void max310x_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) port->type = PORT_MAX310X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (s->irq != port->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static void max310x_null_void(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const struct uart_ops max310x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .tx_empty = max310x_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .set_mctrl = max310x_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .get_mctrl = max310x_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .stop_tx = max310x_null_void,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .start_tx = max310x_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .stop_rx = max310x_null_void,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .break_ctl = max310x_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .startup = max310x_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .shutdown = max310x_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .set_termios = max310x_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .type = max310x_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .request_port = max310x_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .release_port = max310x_null_void,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .config_port = max310x_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .verify_port = max310x_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int __maybe_unused max310x_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) for (i = 0; i < s->devtype->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) uart_suspend_port(&max310x_uart, &s->p[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) s->devtype->power(&s->p[i].port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int __maybe_unused max310x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) for (i = 0; i < s->devtype->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) s->devtype->power(&s->p[i].port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) uart_resume_port(&max310x_uart, &s->p[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct max310x_port *s = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct uart_port *port = &s->p[offset / 4].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) val = max310x_port_read(port, MAX310X_GPIODATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return !!((val >> 4) & (1 << (offset % 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct max310x_port *s = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct uart_port *port = &s->p[offset / 4].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) value ? 1 << (offset % 4) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct max310x_port *s = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct uart_port *port = &s->p[offset / 4].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int max310x_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct max310x_port *s = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct uart_port *port = &s->p[offset / 4].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) value ? 1 << (offset % 4) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) 1 << (offset % 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct max310x_port *s = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct uart_port *port = &s->p[offset / 4].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) max310x_port_update(port, MAX310X_GPIOCFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) 1 << ((offset % 4) + 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) 1 << ((offset % 4) + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) max310x_port_update(port, MAX310X_GPIOCFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 1 << ((offset % 4) + 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct regmap *regmap, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) int i, ret, fmin, fmax, freq, uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct clk *clk_osc, *clk_xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct max310x_port *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) bool xtal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* Alloc port structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_err(dev, "Error allocating port structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) clk_osc = devm_clk_get(dev, "osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) clk_xtal = devm_clk_get(dev, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!IS_ERR(clk_osc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) s->clk = clk_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) fmin = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) fmax = 35000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) } else if (!IS_ERR(clk_xtal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) s->clk = clk_xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) fmin = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) fmax = 4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) xtal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(dev, "Cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ret = clk_prepare_enable(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) freq = clk_get_rate(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Check frequency limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (freq < fmin || freq > fmax) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) s->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) s->devtype = devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_set_drvdata(dev, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* Check device to ensure we are talking to what we expect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret = devtype->detect(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) for (i = 0; i < devtype->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) unsigned int offs = i << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Reset port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) MAX310X_MODE2_RST_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* Clear port reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Wait for port startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) regmap_read(s->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) MAX310X_BRGDIVLSB_REG + offs, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) } while (ret != 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) regmap_write(s->regmap, MAX310X_MODE1_REG + offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) devtype->mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) for (i = 0; i < devtype->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (line == MAX310X_UART_NRMAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) goto out_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Initialize port data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) s->p[i].port.line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) s->p[i].port.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) s->p[i].port.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) s->p[i].port.type = PORT_MAX310X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) s->p[i].port.iotype = UPIO_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) s->p[i].port.iobase = i * 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) s->p[i].port.membase = (void __iomem *)~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) s->p[i].port.uartclk = uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) s->p[i].port.rs485_config = max310x_rs485_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) s->p[i].port.ops = &max310x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Clear IRQ status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* Initialize queue for start TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* Initialize queue for changing LOOPBACK mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) INIT_WORK(&s->p[i].md_work, max310x_md_proc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* Initialize queue for changing RS485 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Initialize SPI-transfer buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) MAX310X_WRITE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Register port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) s->p[i].port.dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) goto out_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) set_bit(line, max310x_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* Go to suspend mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) devtype->power(&s->p[i].port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Setup GPIO cotroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) s->gpio.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) s->gpio.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) s->gpio.label = devtype->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) s->gpio.direction_input = max310x_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) s->gpio.get = max310x_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) s->gpio.direction_output= max310x_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) s->gpio.set = max310x_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) s->gpio.set_config = max310x_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) s->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) s->gpio.ngpio = devtype->nr * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) s->gpio.can_sleep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = devm_gpiochip_add_data(dev, &s->gpio, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) goto out_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Setup interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_err(dev, "Unable to reguest IRQ %i\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) out_uart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) for (i = 0; i < devtype->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (s->p[i].port.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) uart_remove_one_port(&max310x_uart, &s->p[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) clear_bit(s->p[i].port.line, max310x_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) clk_disable_unprepare(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static int max310x_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct max310x_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) for (i = 0; i < s->devtype->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) cancel_work_sync(&s->p[i].tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) cancel_work_sync(&s->p[i].md_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) cancel_work_sync(&s->p[i].rs_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) uart_remove_one_port(&max310x_uart, &s->p[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) clear_bit(s->p[i].port.line, max310x_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) s->devtype->power(&s->p[i].port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) clk_disable_unprepare(s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) { .compatible = "maxim,max3107", .data = &max3107_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) { .compatible = "maxim,max3108", .data = &max3108_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) { .compatible = "maxim,max3109", .data = &max3109_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) { .compatible = "maxim,max14830", .data = &max14830_devtype },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) MODULE_DEVICE_TABLE(of, max310x_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static struct regmap_config regcfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .write_flag_mask = MAX310X_WRITE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .writeable_reg = max310x_reg_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .volatile_reg = max310x_reg_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .precious_reg = max310x_reg_precious,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #ifdef CONFIG_SPI_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int max310x_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct max310x_devtype *devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* Setup SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) spi->mode = spi->mode ? : SPI_MODE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (spi->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) of_match_device(max310x_dt_ids, &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) devtype = (struct max310x_devtype *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) const struct spi_device_id *id_entry = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) devtype = (struct max310x_devtype *)id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) regcfg.max_register = devtype->nr * 0x20 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) regmap = devm_regmap_init_spi(spi, ®cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return max310x_probe(&spi->dev, devtype, regmap, spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static int max310x_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return max310x_remove(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const struct spi_device_id max310x_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { "max3107", (kernel_ulong_t)&max3107_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) { "max3108", (kernel_ulong_t)&max3108_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) { "max3109", (kernel_ulong_t)&max3109_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { "max14830", (kernel_ulong_t)&max14830_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) MODULE_DEVICE_TABLE(spi, max310x_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static struct spi_driver max310x_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .name = MAX310X_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .of_match_table = of_match_ptr(max310x_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .pm = &max310x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .probe = max310x_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .remove = max310x_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .id_table = max310x_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static int __init max310x_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret = uart_register_driver(&max310x_uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #ifdef CONFIG_SPI_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ret = spi_register_driver(&max310x_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) uart_unregister_driver(&max310x_uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) module_init(max310x_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static void __exit max310x_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #ifdef CONFIG_SPI_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) spi_unregister_driver(&max310x_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) uart_unregister_driver(&max310x_uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) module_exit(max310x_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) MODULE_DESCRIPTION("MAX310X serial driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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