^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to use polling for flow control. TX empty IRQ is unusable, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * writing conf clears FIFO buffer and we cannot have this interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * always asking us for attention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Example platform data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static struct plat_max3100 max3100_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .loopback = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .crystal = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .poll_time = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct spi_board_info spi_board_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .modalias = "max3100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .platform_data = &max3100_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .irq = IRQ_EINT12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .max_speed_hz = 5*1000*1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The initial minor number is 209 in the low-density serial port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * mknod /dev/ttyMAX0 c 204 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX3100_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX3100_MINOR 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* 4 MAX3100s should be enough for everyone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_MAX3100 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/freezer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/serial_max3100.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAX3100_C (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX3100_D (0<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAX3100_W (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX3100_RX (0<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAX3100_WC (MAX3100_W | MAX3100_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAX3100_RC (MAX3100_RX | MAX3100_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAX3100_WD (MAX3100_W | MAX3100_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAX3100_RD (MAX3100_RX | MAX3100_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAX3100_CMD (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MAX3100_T (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAX3100_R (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX3100_FEN (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX3100_SHDN (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX3100_TM (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX3100_RM (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAX3100_PM (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAX3100_RAM (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX3100_IR (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAX3100_ST (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX3100_PE (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAX3100_L (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX3100_BAUD (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MAX3100_TE (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAX3100_RAFE (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX3100_RTS (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX3100_CTS (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX3100_PT (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MAX3100_DATA (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAX3100_RT (MAX3100_R | MAX3100_T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* the following simulate a status reg for ignore_status_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAX3100_STATUS_PE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAX3100_STATUS_FE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX3100_STATUS_OE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct max3100_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int cts; /* last CTS received for flow ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int tx_empty; /* last TX empty bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spinlock_t conf_lock; /* shared data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int conf_commit; /* need to make changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int conf; /* configuration for the MAX31000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * (bits 0-7, bits 8-11 are irqs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int rts_commit; /* need to change rts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int rts; /* rts status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int baud; /* current baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int parity; /* keeps track if we should send parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAX3100_PARITY_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAX3100_PARITY_ODD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAX3100_7BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int rx_enabled; /* if we should rx chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int irq; /* irq assigned to the max3100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int minor; /* minor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int loopback; /* 1 if we are in loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* for handling irqs: need workqueue since we do spi_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct workqueue_struct *workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* set to 1 to make the workhandler exit as soon as possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int force_end_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* need to know we are suspending to avoid deadlock on workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int suspending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* hook for suspending MAX3100 via dedicated pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*max3100_hw_suspend) (int suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* poll time (in ms) for ctrl lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* and its timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static DEFINE_MUTEX(max3100s_lock); /* race on probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int max3100_do_parity(struct max3100_port *s, u16 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (s->parity & MAX3100_PARITY_ODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) parity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) parity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (s->parity & MAX3100_7BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) c &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) c &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) parity = parity ^ (hweight8(c) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int max3100_check_parity(struct max3100_port *s, u16 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return max3100_do_parity(s, c) == ((c >> 8) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void max3100_calc_parity(struct max3100_port *s, u16 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (s->parity & MAX3100_7BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *c &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *c &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (s->parity & MAX3100_PARITY_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *c |= max3100_do_parity(s, *c) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void max3100_work(struct work_struct *w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void max3100_dowork(struct max3100_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!s->force_end_work && !freezing(current) && !s->suspending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) queue_work(s->workqueue, &s->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void max3100_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct max3100_port *s = from_timer(s, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (s->port.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mod_timer(&s->timer, jiffies + s->poll_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct spi_message message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u16 etx, erx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct spi_transfer tran = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .tx_buf = &etx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .rx_buf = &erx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) etx = cpu_to_be16(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) spi_message_init(&message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spi_message_add_tail(&tran, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) status = spi_sync(s->spi, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_warn(&s->spi->dev, "error while calling spi_sync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *rx = be16_to_cpu(erx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) s->tx_empty = (*rx & MAX3100_T) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int max3100_handlerx(struct max3100_port *s, u16 rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int ch, flg, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret = 0, cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (rx & MAX3100_R && s->rx_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (rx & MAX3100_RAFE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) s->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) flg = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) status |= MAX3100_STATUS_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (s->parity & MAX3100_PARITY_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (max3100_check_parity(s, rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) s->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) flg = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) s->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) flg = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) status |= MAX3100_STATUS_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) s->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) flg = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cts = (rx & MAX3100_CTS) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (s->cts != cts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) s->cts = cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void max3100_work(struct work_struct *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct max3100_port *s = container_of(w, struct max3100_port, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int rxchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u16 tx, rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int conf, cconf, crts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct circ_buf *xmit = &s->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rxchars = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_lock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) conf = s->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cconf = s->conf_commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) s->conf_commit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) crts = s->rts_commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) s->rts_commit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_unlock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (cconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) max3100_sr(s, MAX3100_WC | conf, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (crts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) max3100_sr(s, MAX3100_WD | MAX3100_TE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (s->rts ? MAX3100_RTS : 0), &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rxchars += max3100_handlerx(s, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) max3100_sr(s, MAX3100_RD, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rxchars += max3100_handlerx(s, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (rx & MAX3100_T) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tx = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (s->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tx = s->port.x_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) s->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) s->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } else if (!uart_circ_empty(xmit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) !uart_tx_stopped(&s->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tx = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) xmit->tail = (xmit->tail + 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) s->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (tx != 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) max3100_calc_parity(s, &tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) max3100_sr(s, tx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) rxchars += max3100_handlerx(s, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rxchars > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) tty_flip_buffer_push(&s->port.state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) rxchars = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uart_write_wakeup(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } while (!s->force_end_work &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) !freezing(current) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ((rx & MAX3100_R) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (!uart_circ_empty(xmit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) !uart_tx_stopped(&s->port))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (rxchars > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tty_flip_buffer_push(&s->port.state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static irqreturn_t max3100_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct max3100_port *s = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void max3100_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (s->poll_time > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mod_timer(&s->timer, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void max3100_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void max3100_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) s->rx_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) spin_lock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) s->conf &= ~MAX3100_RM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) s->conf_commit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_unlock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static unsigned int max3100_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* may not be truly up-to-date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return s->tx_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static unsigned int max3100_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* may not be truly up-to-date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* always assert DCD and DSR since these lines are not wired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int rts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rts = (mctrl & TIOCM_RTS) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) spin_lock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (s->rts != rts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) s->rts = rts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) s->rts_commit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spin_unlock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) max3100_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int baud = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 param_new, param_mask, parity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) cflag = termios->c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) param_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) baud = tty_termios_baud_rate(termios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) param_new = s->conf & MAX3100_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (baud) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (s->crystal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) baud = s->baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) param_new = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case 600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) param_new = 14 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) param_new = 13 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 2400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) param_new = 12 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case 4800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) param_new = 11 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 9600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) param_new = 10 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case 19200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) param_new = 9 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case 38400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) param_new = 8 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case 57600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) param_new = 1 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 115200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) param_new = 0 + s->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case 230400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (s->crystal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) param_new = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) baud = s->baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) baud = s->baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) s->baud = baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) param_mask |= MAX3100_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if ((cflag & CSIZE) == CS8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) param_new &= ~MAX3100_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) parity &= ~MAX3100_7BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) param_new |= MAX3100_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) parity |= MAX3100_7BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) cflag = (cflag & ~CSIZE) | CS7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) param_mask |= MAX3100_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) param_new |= MAX3100_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) param_new &= ~MAX3100_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) param_mask |= MAX3100_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) param_new |= MAX3100_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) parity |= MAX3100_PARITY_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) param_new &= ~MAX3100_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) parity &= ~MAX3100_PARITY_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) param_mask |= MAX3100_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) parity |= MAX3100_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) parity &= ~MAX3100_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* mask termios capabilities we don't support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cflag &= ~CMSPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) termios->c_cflag = cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) s->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) s->port.ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MAX3100_STATUS_PE | MAX3100_STATUS_FE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MAX3100_STATUS_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* we are sending char from a workqueue so enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) s->port.state->port.low_latency = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (s->poll_time > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) del_timer_sync(&s->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_lock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) s->conf = (s->conf & ~param_mask) | (param_new & param_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) s->conf_commit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) s->parity = parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) spin_unlock(&s->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (UART_ENABLE_MS(&s->port, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) max3100_enable_ms(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void max3100_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (s->suspending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) s->force_end_work = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (s->poll_time > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) del_timer_sync(&s->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (s->workqueue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) flush_workqueue(s->workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) destroy_workqueue(s->workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) s->workqueue = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (s->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) free_irq(s->irq, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* set shutdown mode to save power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (s->max3100_hw_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) s->max3100_hw_suspend(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u16 tx, rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tx = MAX3100_WC | MAX3100_SHDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) max3100_sr(s, tx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int max3100_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) char b[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) s->conf = MAX3100_RM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) s->baud = s->crystal ? 230400 : 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) s->rx_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (s->suspending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) s->force_end_work = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) s->parity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) s->rts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) sprintf(b, "max3100-%d", s->minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) s->workqueue = create_freezable_workqueue(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!s->workqueue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_warn(&s->spi->dev, "cannot create workqueue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) INIT_WORK(&s->work, max3100_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (request_irq(s->irq, max3100_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) IRQF_TRIGGER_FALLING, "max3100", s) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) s->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) destroy_workqueue(s->workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) s->workqueue = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (s->loopback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u16 tx, rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tx = 0x4001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) max3100_sr(s, tx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (s->max3100_hw_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) s->max3100_hw_suspend(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) s->conf_commit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* wait for clock to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) max3100_enable_ms(&s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char *max3100_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void max3100_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void max3100_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) s->port.type = PORT_MAX3100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int max3100_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void max3100_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int max3100_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static void max3100_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct max3100_port *s = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct max3100_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct uart_ops max3100_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .tx_empty = max3100_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .set_mctrl = max3100_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .get_mctrl = max3100_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .stop_tx = max3100_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .start_tx = max3100_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .stop_rx = max3100_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .enable_ms = max3100_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .break_ctl = max3100_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .startup = max3100_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .shutdown = max3100_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .set_termios = max3100_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .type = max3100_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .release_port = max3100_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .request_port = max3100_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .config_port = max3100_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .verify_port = max3100_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static struct uart_driver max3100_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .driver_name = "ttyMAX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .dev_name = "ttyMAX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .major = MAX3100_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .minor = MAX3100_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .nr = MAX_MAX3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int uart_driver_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int max3100_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int i, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct plat_max3100 *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u16 tx, rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mutex_lock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!uart_driver_registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uart_driver_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) retval = uart_register_driver(&max3100_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) printk(KERN_ERR "Couldn't register max3100 uart driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mutex_unlock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) for (i = 0; i < MAX_MAX3100; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!max3100s[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (i == MAX_MAX3100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_warn(&spi->dev, "too many MAX3100 chips\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mutex_unlock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!max3100s[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_warn(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "kmalloc for max3100 structure %d failed!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mutex_unlock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) max3100s[i]->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) max3100s[i]->irq = spi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_lock_init(&max3100s[i]->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) spi_set_drvdata(spi, max3100s[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) max3100s[i]->crystal = pdata->crystal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) max3100s[i]->loopback = pdata->loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) max3100s[i]->poll_time = msecs_to_jiffies(pdata->poll_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) max3100s[i]->poll_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) max3100s[i]->minor = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) timer_setup(&max3100s[i]->timer, max3100_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) max3100s[i]->port.irq = max3100s[i]->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) max3100s[i]->port.fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) max3100s[i]->port.ops = &max3100_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) max3100s[i]->port.line = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) max3100s[i]->port.type = PORT_MAX3100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) max3100s[i]->port.dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_warn(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "uart_add_one_port failed for line %d with error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) i, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* set shutdown mode to save power. Will be woken-up on open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (max3100s[i]->max3100_hw_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) max3100s[i]->max3100_hw_suspend(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) tx = MAX3100_WC | MAX3100_SHDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) max3100_sr(max3100s[i], tx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mutex_unlock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int max3100_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct max3100_port *s = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mutex_lock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* find out the index for the chip we are removing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) for (i = 0; i < MAX_MAX3100; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (max3100s[i] == s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) kfree(max3100s[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) max3100s[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) WARN_ON(i == MAX_MAX3100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* check if this is the last chip we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) for (i = 0; i < MAX_MAX3100; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (max3100s[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_unlock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pr_debug("removing max3100 driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) uart_unregister_driver(&max3100_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mutex_unlock(&max3100s_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int max3100_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct max3100_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) disable_irq(s->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) s->suspending = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) uart_suspend_port(&max3100_uart_driver, &s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (s->max3100_hw_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) s->max3100_hw_suspend(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* no HW suspend, so do SW one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u16 tx, rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) tx = MAX3100_WC | MAX3100_SHDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) max3100_sr(s, tx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int max3100_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct max3100_port *s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_dbg(&s->spi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (s->max3100_hw_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) s->max3100_hw_suspend(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) uart_resume_port(&max3100_uart_driver, &s->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) s->suspending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) enable_irq(s->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) s->conf_commit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (s->workqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) max3100_dowork(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define MAX3100_PM_OPS (&max3100_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MAX3100_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static struct spi_driver max3100_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .name = "max3100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .pm = MAX3100_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .probe = max3100_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .remove = max3100_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) module_spi_driver(max3100_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MODULE_DESCRIPTION("MAX3100 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MODULE_ALIAS("spi:max3100");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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