^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Infineon IFAP DC COM CPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2007 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/lantiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PORT_LTQ_ASC 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAXPORTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UART_DUMMY_UER_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRVNAME "lantiq,asc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LTQ_ASC_TBUF (0x0020 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LTQ_ASC_RBUF (0x0024 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LTQ_ASC_TBUF 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LTQ_ASC_RBUF 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LTQ_ASC_FSTAT 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LTQ_ASC_WHBSTATE 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LTQ_ASC_STATE 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LTQ_ASC_IRNCR 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LTQ_ASC_CLC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LTQ_ASC_ID 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LTQ_ASC_PISEL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LTQ_ASC_TXFCON 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LTQ_ASC_RXFCON 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LTQ_ASC_CON 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LTQ_ASC_BG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LTQ_ASC_IRNREN 0x00F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ASC_IRNREN_TX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ASC_IRNREN_RX 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ASC_IRNREN_ERR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ASC_IRNREN_TX_BUF 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ASC_IRNCR_TIR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ASC_IRNCR_RIR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ASC_IRNCR_EIR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ASC_IRNCR_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ASCOPT_CSIZE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TXFIFO_FL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RXFIFO_FL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ASCCLC_DISS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ASCCLC_RMCMASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ASCCLC_RMCOFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ASCCON_M_8ASYNC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ASCCON_M_7ASYNC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ASCCON_ODD 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ASCCON_STP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ASCCON_BRS 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ASCCON_FDE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ASCCON_R 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ASCCON_FEN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ASCCON_ROEN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ASCCON_TOEN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ASCSTATE_PE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ASCSTATE_FE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ASCSTATE_ROE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ASCWHBSTATE_CLRREN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ASCWHBSTATE_SETREN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ASCWHBSTATE_CLRPE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ASCWHBSTATE_CLRFE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ASCWHBSTATE_CLRROE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ASCTXFCON_TXFEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASCTXFCON_TXFFLU 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ASCTXFCON_TXFITLMASK 0x3F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ASCTXFCON_TXFITLOFF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ASCRXFCON_RXFEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ASCRXFCON_RXFFLU 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ASCRXFCON_RXFITLMASK 0x3F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ASCRXFCON_RXFITLOFF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ASCFSTAT_RXFFLMASK 0x003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ASCFSTAT_TXFFLMASK 0x3F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ASCFSTAT_TXFREEMASK 0x3F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ASCFSTAT_TXFREEOFF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void lqasc_tx_chars(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct ltq_uart_port *lqasc_port[MAXPORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct uart_driver lqasc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ltq_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int (*request_irq)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void (*free_irq)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ltq_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* clock used to derive divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk *freqclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* clock gating of the ASC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int common_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spinlock_t lock; /* exclusive access for multi core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct ltq_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 tmp = __raw_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __raw_writel((tmp & ~clear) | set, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return container_of(port, struct ltq_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) lqasc_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) lqasc_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) lqasc_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) lqasc_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) lqasc_rx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int ch = 0, rsr = 0, fifocnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ASCFSTAT_RXFFLMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) while (fifocnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ch = readb(port->membase + LTQ_ASC_RBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Note that the error handling code is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * out of the main execution path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (rsr & ASCSTATE_ANY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (rsr & ASCSTATE_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) asc_update_bits(0, ASCWHBSTATE_CLRPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) port->membase + LTQ_ASC_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } else if (rsr & ASCSTATE_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) asc_update_bits(0, ASCWHBSTATE_CLRFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) port->membase + LTQ_ASC_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (rsr & ASCSTATE_ROE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) asc_update_bits(0, ASCWHBSTATE_CLRROE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) port->membase + LTQ_ASC_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rsr &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (rsr & ASCSTATE_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else if (rsr & ASCSTATE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if ((rsr & port->ignore_status_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tty_insert_flip_char(tport, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (rsr & ASCSTATE_ROE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Overrun is special, since it's reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * immediately, and doesn't affect the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ch != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lqasc_tx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) lqasc_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writeb(port->state->xmit.buf[port->state->xmit.tail],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) port->membase + LTQ_ASC_TBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) lqasc_tx_int(int irq, void *_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct uart_port *port = (struct uart_port *)_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) lqasc_start_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) lqasc_err_int(int irq, void *_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct uart_port *port = (struct uart_port *)_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) lqasc_rx_int(int irq, void *_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct uart_port *port = (struct uart_port *)_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) lqasc_rx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static irqreturn_t lqasc_irq(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct uart_port *port = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) stat = readl(port->membase + LTQ_ASC_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!(stat & ASC_IRNCR_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (stat & ASC_IRNCR_TIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) lqasc_tx_int(irq, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (stat & ASC_IRNCR_RIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) lqasc_rx_int(irq, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (stat & ASC_IRNCR_EIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) lqasc_err_int(irq, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) lqasc_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ASCFSTAT_TXFFLMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return status ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) lqasc_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) lqasc_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) lqasc_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!IS_ERR(ltq_port->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_prepare_enable(ltq_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) port->uartclk = clk_get_rate(ltq_port->freqclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) port->membase + LTQ_ASC_CLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __raw_writel(0, port->membase + LTQ_ASC_PISEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __raw_writel(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) port->membase + LTQ_ASC_TXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __raw_writel(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) port->membase + LTQ_ASC_RXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* make sure other settings are written to hardware before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * setting enable bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ASCCON_ROEN, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) retval = ltq_port->soc->request_irq(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) port->membase + LTQ_ASC_IRNREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lqasc_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ltq_port->soc->free_irq(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __raw_writel(0, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) port->membase + LTQ_ASC_RXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) port->membase + LTQ_ASC_TXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!IS_ERR(ltq_port->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk_disable_unprepare(ltq_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) lqasc_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct ktermios *new, struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int con = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cflag = new->c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) iflag = new->c_iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) switch (cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) con = ASCCON_M_7ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) new->c_cflag &= ~ CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) new->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) con = ASCCON_M_8ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) con |= ASCCON_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!(cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) con &= ~ASCCON_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) con |= ASCCON_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) port->read_status_mask = ASCSTATE_ROE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) port->ignore_status_mask |= ASCSTATE_ROE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if ((cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) port->ignore_status_mask |= UART_DUMMY_UER_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* set error signals - framing, parity and overrun, enable receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* set up CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Set baud rate - take a divider of 2 into account */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) divisor = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) divisor = divisor / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* disable the baudrate generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* make sure the fractional divider is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* set up to use divisor of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* now we can write the new baudrate into the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __raw_writel(divisor, port->membase + LTQ_ASC_BG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* turn the baudrate generator back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* enable rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Don't rewrite B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (tty_termios_baud_rate(new))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tty_termios_encode_baud_rate(new, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uart_update_timeout(port, cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const char*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) lqasc_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (port->type == PORT_LTQ_ASC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return DRVNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) lqasc_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) devm_iounmap(&pdev->dev, port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) lqasc_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(&pdev->dev, "cannot obtain I/O memory region");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) res = devm_request_mem_region(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) size, dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_err(&pdev->dev, "cannot request I/O memory region");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) port->membase = devm_ioremap(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) port->mapbase, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (port->membase == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) lqasc_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) port->type = PORT_LTQ_ASC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) lqasc_request_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) lqasc_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ser->irq < 0 || ser->irq >= NR_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ser->baud_base < 9600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct uart_ops lqasc_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .tx_empty = lqasc_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .set_mctrl = lqasc_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .get_mctrl = lqasc_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .stop_tx = lqasc_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .start_tx = lqasc_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .stop_rx = lqasc_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .break_ctl = lqasc_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .startup = lqasc_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .shutdown = lqasc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .set_termios = lqasc_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .type = lqasc_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .release_port = lqasc_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .request_port = lqasc_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .config_port = lqasc_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .verify_port = lqasc_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) lqasc_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int fifofree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) } while (fifofree == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writeb(ch, port->membase + LTQ_ASC_TBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void lqasc_serial_port_write(struct uart_port *port, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) uart_console_write(port, s, count, lqasc_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) lqasc_console_write(struct console *co, const char *s, u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ltq_uart_port *ltq_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (co->index >= MAXPORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ltq_port = lqasc_port[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!ltq_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spin_lock_irqsave(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) lqasc_serial_port_write(<q_port->port, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spin_unlock_irqrestore(<q_port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) lqasc_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct ltq_uart_port *ltq_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (co->index >= MAXPORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ltq_port = lqasc_port[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!ltq_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) port = <q_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!IS_ERR(ltq_port->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clk_prepare_enable(ltq_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) port->uartclk = clk_get_rate(ltq_port->freqclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static struct console lqasc_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .name = "ttyLTQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .write = lqasc_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .setup = lqasc_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .data = &lqasc_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) lqasc_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) register_console(&lqasc_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) console_initcall(lqasc_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void lqasc_serial_early_console_write(struct console *co,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct earlycon_device *dev = co->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) lqasc_serial_port_write(&dev->port, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) lqasc_serial_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) device->con->write = lqasc_serial_early_console_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define LANTIQ_SERIAL_CONSOLE (&lqasc_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define LANTIQ_SERIAL_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static struct uart_driver lqasc_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .driver_name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .dev_name = "ttyLTQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .major = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .nr = MAXPORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .cons = LANTIQ_SERIAL_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct uart_port *port = <q_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct resource irqres[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = of_irq_to_resource_table(dev->of_node, irqres, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "failed to get IRQs for serial port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ltq_port->tx_irq = irqres[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ltq_port->rx_irq = irqres[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ltq_port->err_irq = irqres[2].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) port->irq = irqres[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int request_irq_lantiq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 0, "asc_tx", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(port->dev, "failed to request asc_tx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 0, "asc_rx", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(port->dev, "failed to request asc_rx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) retval = request_irq(ltq_port->err_irq, lqasc_err_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 0, "asc_err", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(port->dev, "failed to request asc_err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) free_irq(ltq_port->rx_irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) free_irq(ltq_port->tx_irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void free_irq_lantiq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) free_irq(ltq_port->tx_irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) free_irq(ltq_port->rx_irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) free_irq(ltq_port->err_irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct uart_port *port = <q_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = of_irq_get(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(dev, "failed to fetch IRQ for serial port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ltq_port->common_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) port->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int request_irq_intel(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "asc_irq", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_err(port->dev, "failed to request asc_irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static void free_irq_intel(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) free_irq(ltq_port->common_irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int lqasc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct ltq_uart_port *ltq_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct resource *mmres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!mmres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "failed to get memory for serial port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!ltq_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) port = <q_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ltq_port->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* get serial id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) line = of_alias_get_id(node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (line < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (IS_ENABLED(CONFIG_LANTIQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) line = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (lqasc_port[line]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_err(&pdev->dev, "port %d already allocated\n", line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) port->iotype = SERIAL_IO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) port->ops = &lqasc_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) port->fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) port->type = PORT_LTQ_ASC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) port->line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* unused, just to be backward-compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) port->mapbase = mmres->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ltq_port->freqclk = clk_get_fpi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (IS_ERR(ltq_port->freqclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pr_err("failed to get fpi clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* not all asc ports have clock gates, lets ignore the return code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ltq_port->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) spin_lock_init(<q_port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) lqasc_port[line] = ltq_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) platform_set_drvdata(pdev, ltq_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = uart_add_one_port(&lqasc_reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int lqasc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct uart_port *port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return uart_remove_one_port(&lqasc_reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const struct ltq_soc_data soc_data_lantiq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .fetch_irq = fetch_irq_lantiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .request_irq = request_irq_lantiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .free_irq = free_irq_lantiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct ltq_soc_data soc_data_intel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .fetch_irq = fetch_irq_intel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .request_irq = request_irq_intel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .free_irq = free_irq_intel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct of_device_id ltq_asc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { .compatible = "lantiq,asc", .data = &soc_data_lantiq },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { .compatible = "intel,lgm-asc", .data = &soc_data_intel },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MODULE_DEVICE_TABLE(of, ltq_asc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static struct platform_driver lqasc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .probe = lqasc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .remove = lqasc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .of_match_table = ltq_asc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) init_lqasc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = uart_register_driver(&lqasc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = platform_driver_register(&lqasc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) uart_unregister_driver(&lqasc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static void __exit exit_lqasc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) platform_driver_unregister(&lqasc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) uart_unregister_driver(&lqasc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) module_init(init_lqasc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) module_exit(exit_lqasc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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