^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2003 Digi International (www.digi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 IBM Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact Information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Scott H Kilau <Scott_Kilau@digi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Wendy Xiong <wendyx@us.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __JSM_DRIVER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __JSM_DRIVER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h> /* To pick up the varions Linux types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Debugging levels can be set using debug insmod variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * They can also be compiled out completely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DBG_INIT = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DBG_BASIC = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DBG_CORE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DBG_OPEN = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DBG_CLOSE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DBG_READ = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DBG_WRITE = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DBG_IOCTL = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DBG_PROC = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DBG_PARAM = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DBG_PSCAN = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DBG_EVENT = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DBG_DRAIN = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DBG_MSIGS = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DBG_MGMT = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DBG_INTR = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DBG_CARR = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define jsm_dbg(nlevel, pdev, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (DBG_##nlevel & jsm_debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAXLINES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAXPORTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX_STOPS_SENT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Board ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_CLASSIC_4 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_CLASSIC_8 0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_CLASSIC_4_422 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_CLASSIC_8_422 0x00D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_NEO_4 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DEVICE_ID_NEO_1_422 0x00CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_DEVICE_ID_NEO_1_422_485 0x00CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_NEO_2_422_485 0x00CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCIE_DEVICE_ID_NEO_8 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCIE_DEVICE_ID_NEO_4 0x00F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Board type definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define T_NEO 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define T_CLASSIC 0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define T_PCIBUS 0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Board State Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BD_RUNNING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BD_REASON 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BD_NOTFOUND 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BD_NOIOPORT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BD_NOMEM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BD_NOBIOS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BD_NOFEP 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BD_FAILED 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BD_ALLOCATED 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BD_TRIBOOT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BD_BADKME 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* 4 extra for alignment play space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WRITEBUFLEN ((4096) + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define JSM_VERSION "jsm: 1.2-1-INKERNEL"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define JSM_PARTNUM "40002438_A-INKERNEL"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct jsm_board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct jsm_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Per board operations structure *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct board_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_handler_t intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void (*uart_init)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void (*uart_off)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void (*param)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void (*assert_modem_signals)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void (*flush_uart_write)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void (*flush_uart_read)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void (*disable_receiver)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void (*enable_receiver)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void (*send_break)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*clear_break)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*send_start_character)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void (*send_stop_character)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Per-board information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct jsm_board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int boardnum; /* Board number: 0-32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int type; /* Type of board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 rev; /* PCI revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 maxports; /* MAX ports this board can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * the interrupt routine from each other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 nasync; /* Number of ports on card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 irq; /* Interrupt request number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 membase; /* Start of base memory of the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u64 membase_end; /* End of base memory of the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 __iomem *re_map_membase;/* Remapped memory of the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u64 iobase; /* Start of io base of the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u64 iobase_end; /* End of io base of the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 bd_uart_offset; /* Space between each UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 bd_dividend; /* Board/UARTs specific dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct board_ops *bd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct list_head jsm_board_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Device flag definitions for ch_flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CH_PRON 0x0001 /* Printer on string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CH_STOP 0x0002 /* Output is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CH_STOPI 0x0004 /* Input is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CH_CD 0x0008 /* Carrier is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CH_FCAR 0x0010 /* Carrier forced on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CH_HANGUP 0x0020 /* Hangup received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CH_OPENING 0x0080 /* Port in fragile open state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CH_CLOSING 0x0100 /* Port in fragile close state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CH_BREAK_SENDING 0x1000 /* Break is being sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Our Read/Error queue sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RQUEUEMASK 0x1FFF /* 8 K - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EQUEUEMASK 0x1FFF /* 8 K - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RQUEUESIZE (RQUEUEMASK + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EQUEUESIZE RQUEUESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Channel information structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct jsm_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct uart_port uart_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct jsm_board *ch_bd; /* Board structure pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spinlock_t ch_lock; /* provide for serialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) wait_queue_head_t ch_flags_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 ch_portnum; /* Port number, 0 offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 ch_open_count; /* open count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 ch_flags; /* Channel flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u64 ch_close_delay; /* How long we should drop RTS/DTR for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) tcflag_t ch_c_iflag; /* channel iflags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) tcflag_t ch_c_cflag; /* channel cflags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tcflag_t ch_c_oflag; /* channel oflags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tcflag_t ch_c_lflag; /* channel lflags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 ch_stopc; /* Stop character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 ch_startc; /* Start character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 ch_mostat; /* FEP output modem status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 ch_mistat; /* FEP input modem status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Pointers to the "mapped" UART structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 ch_cached_lsr; /* Cached value of the LSR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 ch_r_head; /* Head location of the read queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 ch_r_tail; /* Tail location of the read queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 ch_e_head; /* Head location of the error queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 ch_e_tail; /* Tail location of the error queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u64 ch_rxcount; /* total of data received so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u64 ch_txcount; /* total of data transmitted so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 ch_r_tlevel; /* Receive Trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 ch_t_tlevel; /* Transmit Trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 ch_r_watermark; /* Receive Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 ch_stops_sent; /* How many times I have sent a stop character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * to try to stop the other guy sending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 ch_err_parity; /* Count of parity errors on channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u64 ch_err_frame; /* Count of framing errors on channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u64 ch_err_break; /* Count of breaks on channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u64 ch_err_overrun; /* Count of overruns on channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u64 ch_xon_sends; /* Count of xons transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u64 ch_xoff_sends; /* Count of xoffs transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Per channel/port Classic UART structures *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Base Structure Entries Usage Meanings to Host *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * W = read write R = read only *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * U = Unused. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct cls_uart_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 txrx; /* WR RHR/THR - Holding Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 ier; /* WR IER - Interrupt Enable Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 lcr; /* WR LCR - Line Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 mcr; /* WR MCR - Modem Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 lsr; /* WR LSR - Line Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 msr; /* WR MSR - Modem Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 spr; /* WR SPR - Scratch Pad Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Where to read the interrupt register (8bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define UART_16654_FCR_TXTRIGGER_8 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define UART_16654_FCR_TXTRIGGER_16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define UART_16654_FCR_TXTRIGGER_32 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define UART_16654_FCR_TXTRIGGER_56 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define UART_16654_FCR_RXTRIGGER_8 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define UART_16654_FCR_RXTRIGGER_16 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define UART_16654_FCR_RXTRIGGER_56 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define UART_16654_FCR_RXTRIGGER_60 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * These are the EXTENDED definitions for the Exar 654's Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Enable Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Per channel/port NEO UART structure *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Base Structure Entries Usage Meanings to Host *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * W = read write R = read only *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * U = Unused. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct neo_uart_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 txrx; /* WR RHR/THR - Holding Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 ier; /* WR IER - Interrupt Enable Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 lcr; /* WR LCR - Line Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 mcr; /* WR MCR - Modem Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 lsr; /* WR LSR - Line Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 msr; /* WR MSR - Modem Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 spr; /* WR SPR - Scratch Pad Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 fctr; /* WR FCTR - Feature Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 efr; /* WR EFR - Enhanced Function Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Where to read the extended interrupt register (32bits instead of 8bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define UART_17158_POLL_ADDR_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * These are the redefinitions for the FCTR on the XR17C158, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Exar made them different than their earlier design. (XR16C854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* These are only applicable when table D is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define UART_17158_FCTR_RTS_NODELAY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define UART_17158_FCTR_RTS_4DELAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define UART_17158_FCTR_RTS_6DELAY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define UART_17158_FCTR_RTS_8DELAY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define UART_17158_FCTR_RTS_12DELAY 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define UART_17158_FCTR_RTS_16DELAY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define UART_17158_FCTR_RTS_20DELAY 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define UART_17158_FCTR_RTS_24DELAY 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define UART_17158_FCTR_RTS_28DELAY 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define UART_17158_FCTR_RTS_32DELAY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define UART_17158_FCTR_RTS_36DELAY 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define UART_17158_FCTR_RTS_40DELAY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define UART_17158_FCTR_RTS_44DELAY 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define UART_17158_FCTR_RTS_48DELAY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define UART_17158_FCTR_RTS_52DELAY 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define UART_17158_FCTR_RTS_IRDA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define UART_17158_FCTR_RS485 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define UART_17158_FCTR_TRGA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define UART_17158_FCTR_TRGB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define UART_17158_FCTR_TRGC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define UART_17158_FCTR_TRGD 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* 17158 trigger table selects.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define UART_17158_FCTR_BIT6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define UART_17158_FCTR_BIT7 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* 17158 TX/RX memmapped buffer offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define UART_17158_RX_FIFOSIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define UART_17158_TX_FIFOSIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* 17158 Extended IIR's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * These are the extended interrupts that get sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * back to us from the UART's 32bit interrupt register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define UART_17158_TXRDY 0x3 /* TX Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define UART_17158_MSR 0x4 /* Modem State Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * These are the EXTENDED definitions for the 17C158's Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Enable Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Our Global Variables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) extern struct uart_driver jsm_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) extern struct board_ops jsm_neo_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) extern struct board_ops jsm_cls_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) extern int jsm_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Prototypes for non-static functions used in more than one module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int jsm_tty_init(struct jsm_board *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int jsm_uart_port_init(struct jsm_board *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int jsm_remove_uart_port(struct jsm_board *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void jsm_input(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void jsm_check_queue_flow_control(struct jsm_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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