^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Motorola/Freescale IMX serial ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sascha Hauer <sascha@saschahauer.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004 Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rational.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_data/serial-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "serial_mctrl_gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define URXD0 0x0 /* Receiver Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define URTX0 0x40 /* Transmitter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UCR1 0x80 /* Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UCR2 0x84 /* Control Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UCR3 0x88 /* Control Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UCR4 0x8c /* Control Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UFCR 0x90 /* FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USR1 0x94 /* Status Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USR2 0x98 /* Status Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UESC 0x9c /* Escape Character Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UTIM 0xa0 /* Escape Timer Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UBIR 0xa4 /* BRM Incremental Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UBMR 0xa8 /* BRM Modulator Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UBRC 0xac /* Baud Rate Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX21_ONEMS 0xb0 /* One Millisecond register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* UART Control Register Bit Fields.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define URXD_DUMMY_READ (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define URXD_CHARRDY (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define URXD_ERR (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define URXD_OVRRUN (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define URXD_FRMERR (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define URXD_BRK (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define URXD_PRERR (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define URXD_RX_DATA (0xFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UCR1_IREN (1<<7) /* Infrared interface enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UCR1_SNDBRK (1<<4) /* Send break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UCR1_DOZE (1<<1) /* Doze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UCR1_UARTEN (1<<0) /* UART enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UCR2_CTSC (1<<13) /* CTS pin control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UCR2_CTS (1<<12) /* Clear to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UCR2_ESCEN (1<<11) /* Escape enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UCR2_PREN (1<<8) /* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UCR2_PROE (1<<7) /* Parity odd/even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UCR2_STPB (1<<6) /* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UCR2_WS (1<<5) /* Word size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UCR2_TXEN (1<<2) /* Transmitter enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define UCR2_RXEN (1<<1) /* Receiver enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UCR2_SRST (1<<0) /* SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UCR3_PARERREN (1<<12) /* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UCR3_DSR (1<<10) /* Data set ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UCR3_DCD (1<<9) /* Data carrier detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define UCR3_RI (1<<8) /* Ring indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define UCR3_BPEN (1<<0) /* Preset registers enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define UCR4_INVR (1<<9) /* Inverted infrared reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define UCR4_IRSC (1<<5) /* IR special case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USR1_RTSS (1<<14) /* RTS pin status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USR1_RTSD (1<<12) /* RTS delta */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USR1_DTRD (1<<7) /* DTR Delta */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define USR2_IDLE (1<<12) /* Idle condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USR2_RIIN (1<<9) /* Ring Indicator Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USR2_WAKE (1<<7) /* Wake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USR2_TXDC (1<<3) /* Transmitter complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USR2_BRCD (1<<2) /* Break condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define USR2_ORE (1<<1) /* Overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USR2_RDR (1<<0) /* Recv data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define UTS_FRCPERR (1<<13) /* Force parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define UTS_LOOP (1<<12) /* Loop tx and rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define UTS_TXFULL (1<<4) /* TxFIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define UTS_RXFULL (1<<3) /* RxFIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define UTS_SOFTRST (1<<0) /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* We've been assigned a range on the "Low-density serial ports" major */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SERIAL_IMX_MAJOR 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MINOR_START 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DEV_NAME "ttymxc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * This determines how often we check the modem status signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * for any change. They generally aren't connected to an IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * so we have to poll them. We also check immediately before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * filling the TX fifo incase CTS has been dropped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCTRL_TIMEOUT (250*HZ/1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRIVER_NAME "IMX-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define UART_NR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) enum imx_uart_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IMX1_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IMX21_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IMX53_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IMX6Q_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* device type dependent stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct imx_uart_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned uts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum imx_uart_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) enum imx_tx_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) WAIT_AFTER_RTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) WAIT_AFTER_SEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct imx_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int old_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int have_rtscts:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int have_rtsgpio:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int dte_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int inverted_tx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int inverted_rx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct imx_uart_data *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct mctrl_gpios *gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* shadow registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int ucr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int ufcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* DMA fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int dma_is_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int dma_is_rxing:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int dma_is_txing:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct dma_chan *dma_chan_rx, *dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct scatterlist rx_sgl, tx_sgl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct circ_buf rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int rx_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dma_cookie_t rx_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int dma_tx_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int saved_reg[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bool context_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum imx_tx_state tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct hrtimer trigger_start_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct hrtimer trigger_stop_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct imx_port_ucrs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int ucr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct imx_uart_data imx_uart_devdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [IMX1_UART] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .uts_reg = IMX1_UTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .devtype = IMX1_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [IMX21_UART] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .uts_reg = IMX21_UTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .devtype = IMX21_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [IMX53_UART] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .uts_reg = IMX21_UTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .devtype = IMX53_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [IMX6Q_UART] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .uts_reg = IMX21_UTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .devtype = IMX6Q_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct platform_device_id imx_uart_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "imx1-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "imx21-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "imx53-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "imx6q-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct of_device_id imx_uart_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case UCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sport->ucr1 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case UCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sport->ucr2 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case UCR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sport->ucr3 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case UCR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sport->ucr4 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case UFCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) sport->ufcr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(val, sport->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case UCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return sport->ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case UCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * UCR2_SRST is the only bit in the cached registers that might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * differ from the value that was last written. As it only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * automatically becomes one after being cleared, reread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * conditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!(sport->ucr2 & UCR2_SRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) sport->ucr2 = readl(sport->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return sport->ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case UCR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return sport->ucr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case UCR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return sport->ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case UFCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return sport->ufcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return readl(sport->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return sport->devdata->uts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static inline int imx_uart_is_imx1(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return sport->devdata->devtype == IMX1_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline int imx_uart_is_imx21(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return sport->devdata->devtype == IMX21_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline int imx_uart_is_imx53(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return sport->devdata->devtype == IMX53_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static inline int imx_uart_is_imx6q(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return sport->devdata->devtype == IMX6Q_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Save and restore functions for UCR1, UCR2 and UCR3 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void imx_uart_ucrs_save(struct imx_port *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct imx_port_ucrs *ucr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* save control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ucr->ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ucr->ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ucr->ucr3 = imx_uart_readl(sport, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void imx_uart_ucrs_restore(struct imx_port *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct imx_port_ucrs *ucr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* restore control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) imx_uart_writel(sport, ucr->ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) imx_uart_writel(sport, ucr->ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) imx_uart_writel(sport, ucr->ucr3, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* called with port.lock taken and irqs caller dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sport->port.mctrl |= TIOCM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mctrl_gpio_set(sport->gpios, sport->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* called with port.lock taken and irqs caller dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *ucr2 &= ~UCR2_CTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *ucr2 |= UCR2_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sport->port.mctrl &= ~TIOCM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mctrl_gpio_set(sport->gpios, sport->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) long sec = msec / MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) long nsec = (msec % MSEC_PER_SEC) * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ktime_t t = ktime_set(sec, nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hrtimer_start(hrt, t, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void imx_uart_start_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int ucr1, ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ucr2 |= UCR2_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ucr1 |= UCR1_RRDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ucr2 |= UCR2_ATEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Write UCR2 first as it includes RXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void imx_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 ucr1, ucr4, usr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (sport->tx_state == OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * We are maybe in the SMP context, so if the DMA TX thread is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * on other cpu, we have to wait for it to finish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (sport->dma_is_txing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) usr2 = imx_uart_readl(sport, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!(usr2 & USR2_TXDC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* The shifter is still busy, so retry once TC triggers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ucr4 &= ~UCR4_TCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* in rs485 mode disable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (sport->tx_state == SEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sport->tx_state = WAIT_AFTER_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) start_hrtimer_ms(&sport->trigger_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) port->rs485.delay_rts_after_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (sport->tx_state == WAIT_AFTER_RTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) sport->tx_state == WAIT_AFTER_SEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) hrtimer_try_to_cancel(&sport->trigger_start_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) imx_uart_rts_active(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) imx_uart_rts_inactive(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) imx_uart_start_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sport->tx_state = OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) sport->tx_state = OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void imx_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 ucr1, ucr2, ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ucr1 &= ~UCR1_RRDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ucr2 &= ~UCR2_ATEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ucr4 &= ~UCR4_OREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ucr2 &= ~UCR2_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void imx_uart_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mod_timer(&sport->timer, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mctrl_gpio_enable_ms(sport->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void imx_uart_dma_tx(struct imx_port *sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static inline void imx_uart_transmit_buffer(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct circ_buf *xmit = &sport->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (sport->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Send next char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) imx_uart_writel(sport, sport->port.x_char, URTX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) sport->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) imx_uart_stop_tx(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * We've just sent a X-char Ensure the TX DMA is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * and the TX IRQ is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ucr1 &= ~UCR1_TRDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (sport->dma_is_txing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ucr1 |= UCR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) imx_uart_dma_tx(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) while (!uart_circ_empty(xmit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* send xmit->buf[xmit->tail]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * out the port here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) uart_write_wakeup(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) imx_uart_stop_tx(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void imx_uart_dma_tx_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct imx_port *sport = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct scatterlist *sgl = &sport->tx_sgl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct circ_buf *xmit = &sport->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ucr1 &= ~UCR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* update the stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sport->port.icount.tx += sport->tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sport->dma_is_txing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uart_write_wakeup(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) imx_uart_dma_tx(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ucr4 |= UCR4_TCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void imx_uart_dma_tx(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct circ_buf *xmit = &sport->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct scatterlist *sgl = sport->tx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct dma_chan *chan = sport->dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct device *dev = sport->port.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 ucr1, ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (sport->dma_is_txing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ucr4 &= ~UCR4_TCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) sport->tx_bytes = uart_circ_chars_pending(xmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (xmit->tail < xmit->head || xmit->head == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) sport->dma_tx_nents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) sport->dma_tx_nents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) sg_init_table(sgl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) sg_set_buf(sgl, xmit->buf + xmit->tail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) UART_XMIT_SIZE - xmit->tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) sg_set_buf(sgl + 1, xmit->buf, xmit->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(dev, "DMA mapping error for TX.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) desc = dmaengine_prep_slave_sg(chan, sgl, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(dev, "We cannot prepare for the TX slave dma!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) desc->callback = imx_uart_dma_tx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) desc->callback_param = sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uart_circ_chars_pending(xmit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ucr1 |= UCR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* fire it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) sport->dma_is_txing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void imx_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * We cannot simply do nothing here if sport->tx_state == SEND already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * because UCR1_TXMPTYEN might already have been cleared in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * imx_uart_stop_tx(), but tx_state is still SEND.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (sport->tx_state == OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) imx_uart_rts_active(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) imx_uart_rts_inactive(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) imx_uart_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sport->tx_state = WAIT_AFTER_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) start_hrtimer_ms(&sport->trigger_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) port->rs485.delay_rts_before_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (sport->tx_state == WAIT_AFTER_SEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) || sport->tx_state == WAIT_AFTER_RTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) hrtimer_try_to_cancel(&sport->trigger_stop_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Enable transmitter and shifter empty irq only if DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * is off. In the DMA case this is done in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * tx-callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ucr4 |= UCR4_TCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) sport->tx_state = SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) sport->tx_state = SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (sport->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* We have X-char to send, so enable TX IRQ and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * disable TX DMA to let TX interrupt to send X-char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ucr1 &= ~UCR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ucr1 |= UCR1_TRDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!uart_circ_empty(&port->state->xmit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) !uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) imx_uart_dma_tx(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct imx_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 usr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) imx_uart_writel(sport, USR1_RTSD, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uart_handle_cts_change(&sport->port, !!usr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct imx_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) spin_lock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = __imx_uart_rtsint(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) spin_unlock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static irqreturn_t imx_uart_txint(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct imx_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) spin_lock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) imx_uart_transmit_buffer(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) spin_unlock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct imx_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned int rx, flg, ignored = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct tty_port *port = &sport->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) while (imx_uart_readl(sport, USR2) & USR2_RDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 usr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) flg = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) sport->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) rx = imx_uart_readl(sport, URXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) usr2 = imx_uart_readl(sport, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (usr2 & USR2_BRCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) imx_uart_writel(sport, USR2_BRCD, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (uart_handle_break(&sport->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (unlikely(rx & URXD_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (rx & URXD_BRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sport->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) else if (rx & URXD_PRERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) sport->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else if (rx & URXD_FRMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) sport->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (rx & URXD_OVRRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) sport->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (rx & sport->port.ignore_status_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (++ignored > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rx &= (sport->port.read_status_mask | 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (rx & URXD_BRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) flg = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) else if (rx & URXD_PRERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) flg = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) else if (rx & URXD_FRMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) flg = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (rx & URXD_OVRRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) flg = TTY_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) sport->port.sysrq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (tty_insert_flip_char(port, rx, flg) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) sport->port.icount.buf_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct imx_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) spin_lock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = __imx_uart_rxint(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) spin_unlock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static void imx_uart_clear_rx_errors(struct imx_port *sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * We have a modem side uart, so the meanings of RTS and CTS are inverted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned int tmp = TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned usr1 = imx_uart_readl(sport, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unsigned usr2 = imx_uart_readl(sport, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (usr1 & USR1_RTSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) tmp |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* in DCE mode DCDIN is always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!(usr2 & USR2_DCDIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) tmp |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (sport->dte_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) tmp |= TIOCM_RI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * Handle any change of modem status signal since we were last called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static void imx_uart_mctrl_check(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unsigned int status, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) status = imx_uart_get_hwmctrl(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) changed = status ^ sport->old_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (changed == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) sport->old_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (changed & TIOCM_RI && status & TIOCM_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) sport->port.icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (changed & TIOCM_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) sport->port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (changed & TIOCM_CAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (changed & TIOCM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static irqreturn_t imx_uart_int(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct imx_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * IRQs might not be disabled upon entering this interrupt handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * e.g. when interrupt handlers are forced to be threaded. To support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * this scenario as well, disable IRQs when acquiring the spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) usr1 = imx_uart_readl(sport, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) usr2 = imx_uart_readl(sport, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ucr3 = imx_uart_readl(sport, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * Even if a condition is true that can trigger an irq only handle it if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * the respective irq source is enabled. This prevents some undesired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * actions, for example if a character that sits in the RX FIFO and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * should be fetched via DMA is tried to be fetched using PIO. Or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * receiver is currently off and so reading from URXD0 results in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * exception. So just mask the (raw) status bits for disabled irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if ((ucr1 & UCR1_RRDYEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) usr1 &= ~USR1_RRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if ((ucr2 & UCR2_ATEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) usr1 &= ~USR1_AGTIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if ((ucr1 & UCR1_TRDYEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) usr1 &= ~USR1_TRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if ((ucr4 & UCR4_TCEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) usr2 &= ~USR2_TXDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if ((ucr3 & UCR3_DTRDEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) usr1 &= ~USR1_DTRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if ((ucr1 & UCR1_RTSDEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) usr1 &= ~USR1_RTSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if ((ucr3 & UCR3_AWAKEN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) usr1 &= ~USR1_AWAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if ((ucr4 & UCR4_OREN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) usr2 &= ~USR2_ORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) imx_uart_writel(sport, USR1_AGTIM, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) __imx_uart_rxint(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) imx_uart_transmit_buffer(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (usr1 & USR1_DTRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) imx_uart_writel(sport, USR1_DTRD, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) imx_uart_mctrl_check(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (usr1 & USR1_RTSD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) __imx_uart_rtsint(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (usr1 & USR1_AWAKE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) imx_uart_writel(sport, USR1_AWAKE, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (usr2 & USR2_ORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sport->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) imx_uart_writel(sport, USR2_ORE, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * Return TIOCSER_TEMT when transmitter is not busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static unsigned int imx_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* If the TX DMA is working, return 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (sport->dma_is_txing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static unsigned int imx_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unsigned int ret = imx_uart_get_hwmctrl(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mctrl_gpio_get(sport->gpios, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 ucr3, uts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (!(port->rs485.flags & SER_RS485_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u32 ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * Turn off autoRTS if RTS is lowered and restore autoRTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * setting if RTS is raised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (mctrl & TIOCM_RTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ucr2 |= UCR2_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * UCR2_IRTS is unset if and only if the port is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * configured for CRTSCTS, so we use inverted UCR2_IRTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * to get the state to restore to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!(ucr2 & UCR2_IRTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ucr2 |= UCR2_CTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!(mctrl & TIOCM_DTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ucr3 |= UCR3_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) imx_uart_writel(sport, ucr3, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) uts |= UTS_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mctrl_gpio_set(sport->gpios, mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * Interrupts always disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static void imx_uart_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (break_state != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ucr1 |= UCR1_SNDBRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * This is our per-port timeout handler, for checking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * modem status signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static void imx_uart_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct imx_port *sport = from_timer(sport, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (sport->port.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) imx_uart_mctrl_check(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * There are two kinds of RX DMA interrupts(such as in the MX6Q):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * [1] the RX DMA buffer is full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * [2] the aging timer expires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * Condition [2] is triggered when a character has been sitting in the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * for at least 8 byte durations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static void imx_uart_dma_rx_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct imx_port *sport = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct dma_chan *chan = sport->dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct scatterlist *sgl = &sport->rx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct tty_port *port = &sport->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct circ_buf *rx_ring = &sport->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) unsigned int w_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) unsigned int r_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) unsigned int bd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (status == DMA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) imx_uart_clear_rx_errors(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * The state-residue variable represents the empty space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * relative to the entire buffer. Taking this in consideration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * the head is always calculated base on the buffer total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * length - DMA transaction residue. The UART script from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * SDMA firmware will jump to the next buffer descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Taking this in consideration the tail is always at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * beginning of the buffer descriptor that contains the head.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Calculate the head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) rx_ring->head = sg_dma_len(sgl) - state.residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Calculate the tail. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) bd_size = sg_dma_len(sgl) / sport->rx_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (rx_ring->head <= sg_dma_len(sgl) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) rx_ring->head > rx_ring->tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* Move data from tail to head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) r_bytes = rx_ring->head - rx_ring->tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* CPU claims ownership of RX DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) w_bytes = tty_insert_flip_string(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sport->rx_buf + rx_ring->tail, r_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* UART retrieves ownership of RX DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dma_sync_sg_for_device(sport->port.dev, sgl, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (w_bytes != r_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) sport->port.icount.buf_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) sport->port.icount.rx += w_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) WARN_ON(rx_ring->head > sg_dma_len(sgl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) WARN_ON(rx_ring->head <= rx_ring->tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (w_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* RX DMA buffer periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define RX_DMA_PERIODS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int imx_uart_start_rx_dma(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct scatterlist *sgl = &sport->rx_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct dma_chan *chan = sport->dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct device *dev = sport->port.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) sport->rx_ring.head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) sport->rx_ring.tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) sport->rx_periods = RX_DMA_PERIODS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dev_err(dev, "DMA mapping error for RX.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev_err(dev, "We cannot prepare for the RX slave dma!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) desc->callback = imx_uart_dma_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) desc->callback_param = sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_dbg(dev, "RX: prepare for the DMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) sport->dma_is_rxing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) sport->rx_cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void imx_uart_clear_rx_errors(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct tty_port *port = &sport->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u32 usr1, usr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) usr1 = imx_uart_readl(sport, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) usr2 = imx_uart_readl(sport, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (usr2 & USR2_BRCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) sport->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) imx_uart_writel(sport, USR2_BRCD, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) uart_handle_break(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) sport->port.icount.buf_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (usr1 & USR1_FRAMERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) sport->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) imx_uart_writel(sport, USR1_FRAMERR, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else if (usr1 & USR1_PARITYERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) sport->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) imx_uart_writel(sport, USR1_PARITYERR, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (usr2 & USR2_ORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) sport->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) imx_uart_writel(sport, USR2_ORE, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define TXTL_DEFAULT 2 /* reset default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define RXTL_DEFAULT 1 /* reset default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define TXTL_DMA 8 /* DMA burst setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define RXTL_DMA 9 /* DMA burst setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static void imx_uart_setup_ufcr(struct imx_port *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) unsigned char txwl, unsigned char rxwl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* set receiver / transmitter trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) val |= txwl << UFCR_TXTL_SHF | rxwl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) imx_uart_writel(sport, val, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static void imx_uart_dma_exit(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (sport->dma_chan_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) dmaengine_terminate_sync(sport->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dma_release_channel(sport->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) sport->dma_chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) sport->rx_cookie = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) kfree(sport->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) sport->rx_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (sport->dma_chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dmaengine_terminate_sync(sport->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dma_release_channel(sport->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) sport->dma_chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static int imx_uart_dma_init(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct dma_slave_config slave_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct device *dev = sport->port.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* Prepare for RX : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (!sport->dma_chan_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dev_dbg(dev, "cannot get the DMA channel.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) slave_config.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) slave_config.src_addr = sport->port.mapbase + URXD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* one byte less than the watermark level to enable the aging timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) slave_config.src_maxburst = RXTL_DMA - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dev_err(dev, "error in RX dma configuration.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (!sport->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) sport->rx_ring.buf = sport->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* Prepare for TX : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (!sport->dma_chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_err(dev, "cannot get the TX DMA channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) slave_config.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) slave_config.dst_addr = sport->port.mapbase + URTX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) slave_config.dst_maxburst = TXTL_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(dev, "error in TX dma configuration.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) imx_uart_dma_exit(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static void imx_uart_enable_dma(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* set UCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) sport->dma_is_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static void imx_uart_disable_dma(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* clear UCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) sport->dma_is_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* half the RX buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define CTSTL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static int imx_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int retval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) int dma_is_inited = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 ucr1, ucr2, ucr3, ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) retval = clk_prepare_enable(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) retval = clk_prepare_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) clk_disable_unprepare(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* disable the DREN bit (Data Ready interrupt enable) before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * requesting IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* set the trigger level for CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ucr4 |= CTSTL << UCR4_CTSTL_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Can we enable the DMA support? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dma_is_inited = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* Reset fifo's and state machines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) i = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ucr2 &= ~UCR2_SRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * Finally, clear and enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) imx_uart_writel(sport, USR2_ORE, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ucr1 |= UCR1_UARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (sport->have_rtscts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ucr1 |= UCR1_RTSDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (!sport->dma_is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ucr4 |= UCR4_OREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (sport->inverted_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ucr4 |= UCR4_INVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * configure tx polarity before enabling tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (sport->inverted_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ucr3 |= UCR3_INVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!imx_uart_is_imx1(sport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (sport->dte_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* disable broken interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ucr3 &= ~(UCR3_RI | UCR3_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) imx_uart_writel(sport, ucr3, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ucr2 |= (UCR2_RXEN | UCR2_TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (!sport->have_rtscts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ucr2 |= UCR2_IRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * make sure the edge sensitive RTS-irq is disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * we're using RTSD instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (!imx_uart_is_imx1(sport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ucr2 &= ~UCR2_RTSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * Enable modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) imx_uart_enable_ms(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (dma_is_inited) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) imx_uart_enable_dma(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) imx_uart_start_rx_dma(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ucr1 |= UCR1_RRDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ucr2 |= UCR2_ATEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static void imx_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) u32 ucr1, ucr2, ucr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (sport->dma_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dmaengine_terminate_sync(sport->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (sport->dma_is_txing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) sport->dma_tx_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) sport->dma_is_txing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dmaengine_terminate_sync(sport->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (sport->dma_is_rxing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) sport->dma_is_rxing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) imx_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) imx_uart_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) imx_uart_disable_dma(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) imx_uart_dma_exit(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) mctrl_gpio_disable_ms(sport->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * Stop our timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) del_timer_sync(&sport->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * Disable all interrupts, port and break condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ucr4 = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ucr4 &= ~UCR4_TCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) imx_uart_writel(sport, ucr4, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) clk_disable_unprepare(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* called with port.lock taken and irqs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static void imx_uart_flush_buffer(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct scatterlist *sgl = &sport->tx_sgl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) u32 ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) int i = 100, ubir, ubmr, uts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (!sport->dma_chan_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) sport->tx_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dmaengine_terminate_all(sport->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (sport->dma_is_txing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ucr1 &= ~UCR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) sport->dma_is_txing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * According to the Reference Manual description of the UART SRST bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * "Reset the transmit and receive state machines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * and UTS[6-3]".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * We don't need to restore the old values from USR1, USR2, URXD and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * UTXD. UBRC is read only, so only save/restore the other three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ubir = imx_uart_readl(sport, UBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ubmr = imx_uart_readl(sport, UBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) uts = imx_uart_readl(sport, IMX21_UTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ucr2 &= ~UCR2_SRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* Restore the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) imx_uart_writel(sport, ubir, UBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) imx_uart_writel(sport, ubmr, UBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) imx_uart_writel(sport, uts, IMX21_UTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) u32 ucr2, old_ucr2, ufcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) unsigned int baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) unsigned long num, denom, old_ubir, old_ubmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) uint64_t tdiv64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * We only support CS7 and CS8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) while ((termios->c_cflag & CSIZE) != CS7 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) (termios->c_cflag & CSIZE) != CS8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) termios->c_cflag &= ~CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) termios->c_cflag |= old_csize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) old_csize = CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) del_timer_sync(&sport->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * Ask the core to calculate the divisor for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) quot = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * Read current UCR2 and save it for future use, then clear all the bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * except those we will or may need to preserve.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) old_ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ucr2 |= UCR2_SRST | UCR2_IRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if ((termios->c_cflag & CSIZE) == CS8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ucr2 |= UCR2_WS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (!sport->have_rtscts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) termios->c_cflag &= ~CRTSCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (port->rs485.flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * RTS is mandatory for rs485 operation, so keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * it under manual control and keep transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) imx_uart_rts_active(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) imx_uart_rts_inactive(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) } else if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * Only let receiver control RTS output if we were not requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * to have RTS inactive (which then should take precedence).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (ucr2 & UCR2_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ucr2 |= UCR2_CTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (termios->c_cflag & CRTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ucr2 &= ~UCR2_IRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ucr2 |= UCR2_STPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ucr2 |= UCR2_PREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ucr2 |= UCR2_PROE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) sport->port.read_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (termios->c_iflag & (BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) sport->port.read_status_mask |= URXD_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) sport->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) sport->port.ignore_status_mask |= URXD_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) sport->port.ignore_status_mask |= URXD_OVRRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) sport->port.ignore_status_mask |= URXD_DUMMY_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * Update the per-port timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* custom-baudrate handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) div = sport->port.uartclk / (baud * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (baud == 38400 && quot != div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) baud = sport->port.uartclk / (quot * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) div = sport->port.uartclk / (baud * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (div > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) div = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) rational_best_approximation(16 * div * baud, sport->port.uartclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) 1 << 16, 1 << 16, &num, &denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) tdiv64 = sport->port.uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) tdiv64 *= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) do_div(tdiv64, denom * 16 * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) tty_termios_encode_baud_rate(termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) (speed_t)tdiv64, (speed_t)tdiv64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) num -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) denom -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ufcr = imx_uart_readl(sport, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) imx_uart_writel(sport, ufcr, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * Two registers below should always be written both and in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) * particular order. One consequence is that we need to check if any of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * them changes and then update both. We do need the check for change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * as even writing the same values seem to "restart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * transmission/receiving logic in the hardware, that leads to data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * breakage even when rate doesn't in fact change. E.g., user switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * RTS/CTS handshake and suddenly gets broken bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) old_ubir = imx_uart_readl(sport, UBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) old_ubmr = imx_uart_readl(sport, UBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (old_ubir != num || old_ubmr != denom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) imx_uart_writel(sport, num, UBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) imx_uart_writel(sport, denom, UBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (!imx_uart_is_imx1(sport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) imx_uart_writel(sport, sport->port.uartclk / div / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) IMX21_ONEMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) imx_uart_enable_ms(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static const char *imx_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return sport->port.type == PORT_IMX ? "IMX" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * Configure/autoconfigure the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static void imx_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) sport->port.type = PORT_IMX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * Verify the new serial_struct (for TIOCSSERIAL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * The only change we allow are to the flags and type, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * even then only between PORT_IMX and PORT_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (sport->port.irq != ser->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (ser->io_type != UPIO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (sport->port.uartclk / 16 != ser->baud_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (sport->port.mapbase != (unsigned long)ser->iomem_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (sport->port.iobase != ser->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (ser->hub6 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #if defined(CONFIG_CONSOLE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static int imx_uart_poll_init(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u32 ucr1, ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) retval = clk_prepare_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) retval = clk_prepare_enable(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * Be careful about the order of enabling bits here. First enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * receiver (UARTEN + RXEN) and only then the corresponding irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * This prevents that a character that already sits in the RX fifo is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * triggering an irq but the try to fetch it from there results in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * exception because UARTEN or RXEN is still off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (imx_uart_is_imx1(sport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ucr1 |= IMX1_UCR1_UARTCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ucr1 |= UCR1_UARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ucr2 |= UCR2_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ucr2 &= ~UCR2_ATEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* now enable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static int imx_uart_poll_get_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) status = imx_uart_readl(sport, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) } while (~status & USR1_TRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) imx_uart_writel(sport, c, URTX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) status = imx_uart_readl(sport, USR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) } while (~status & USR2_TXDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* called with port.lock taken and irqs off or from .probe without locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static int imx_uart_rs485_config(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct serial_rs485 *rs485conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) u32 ucr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* RTS is required to control the transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (!sport->have_rtscts && !sport->have_rtsgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) rs485conf->flags &= ~SER_RS485_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (rs485conf->flags & SER_RS485_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* Enable receiver if low-active RTS signal is requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (sport->have_rtscts && !sport->have_rtsgpio &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) rs485conf->flags |= SER_RS485_RX_DURING_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* disable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) imx_uart_rts_active(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) imx_uart_rts_inactive(sport, &ucr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) imx_uart_writel(sport, ucr2, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* Make sure Rx is enabled in case Tx is active with Rx disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (!(rs485conf->flags & SER_RS485_ENABLED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) rs485conf->flags & SER_RS485_RX_DURING_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) imx_uart_start_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) port->rs485 = *rs485conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static const struct uart_ops imx_uart_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .tx_empty = imx_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .set_mctrl = imx_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .get_mctrl = imx_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .stop_tx = imx_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .start_tx = imx_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .stop_rx = imx_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .enable_ms = imx_uart_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .break_ctl = imx_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .startup = imx_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .shutdown = imx_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .flush_buffer = imx_uart_flush_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .set_termios = imx_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .type = imx_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .config_port = imx_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .verify_port = imx_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #if defined(CONFIG_CONSOLE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .poll_init = imx_uart_poll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .poll_get_char = imx_uart_poll_get_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .poll_put_char = imx_uart_poll_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static struct imx_port *imx_uart_ports[UART_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static void imx_uart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) struct imx_port *sport = (struct imx_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) imx_uart_writel(sport, ch, URTX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * Interrupts are disabled on entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) imx_uart_console_write(struct console *co, const char *s, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) struct imx_port *sport = imx_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) struct imx_port_ucrs old_ucr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) unsigned int ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (sport->port.sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) locked = spin_trylock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * First, save UCR1/2/3 and then disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) imx_uart_ucrs_save(sport, &old_ucr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ucr1 = old_ucr.ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (imx_uart_is_imx1(sport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ucr1 |= IMX1_UCR1_UARTCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ucr1 |= UCR1_UARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) * and restore UCR1/2/3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) imx_uart_ucrs_restore(sport, &old_ucr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) * If the port was already initialised (eg, by a boot loader),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) * try to determine the current setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) imx_uart_console_get_options(struct imx_port *sport, int *baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) int *parity, int *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /* ok, the port was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) unsigned int ucr2, ubir, ubmr, uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) unsigned int baud_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) unsigned int ucfr_rfdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ucr2 = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) *parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (ucr2 & UCR2_PREN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (ucr2 & UCR2_PROE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) *parity = 'o';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) *parity = 'e';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (ucr2 & UCR2_WS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) *bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) *bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ubir = imx_uart_readl(sport, UBIR) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (ucfr_rfdiv == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ucfr_rfdiv = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ucfr_rfdiv = 6 - ucfr_rfdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) uartclk = clk_get_rate(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) uartclk /= ucfr_rfdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) { /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * The next code provides exact computation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * without need of float support or long long division,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) * which would be required to prevent 32bit arithmetic overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) unsigned int mul = ubir + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) unsigned int div = 16 * (ubmr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) unsigned int rem = uartclk % div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) baud_raw = (uartclk / div) * mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) baud_raw += (rem * mul + div / 2) / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) *baud = (baud_raw + 50) / 100 * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (*baud != baud_raw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) baud_raw, *baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) imx_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct imx_port *sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) * Check whether an invalid uart number has been specified, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * if so, search for the first available port that does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) sport = imx_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (sport == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* For setting the registers, we only need to enable the ipg clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) retval = clk_prepare_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) goto error_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) imx_uart_console_get_options(sport, &baud, &parity, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) goto error_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) retval = clk_prepare_enable(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) error_console:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static struct uart_driver imx_uart_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct console imx_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .name = DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .write = imx_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .setup = imx_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .data = &imx_uart_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define IMX_CONSOLE &imx_uart_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define IMX_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static struct uart_driver imx_uart_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .dev_name = DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .major = SERIAL_IMX_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .minor = MINOR_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .nr = ARRAY_SIZE(imx_uart_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .cons = IMX_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) * could successfully get all information from dt or a negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static int imx_uart_probe_dt(struct imx_port *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) sport->devdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (!sport->devdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /* no device tree device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ret = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) sport->port.line = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (of_get_property(np, "uart-has-rtscts", NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) sport->have_rtscts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (of_get_property(np, "fsl,dte-mode", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) sport->dte_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (of_get_property(np, "rts-gpios", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) sport->have_rtsgpio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (of_get_property(np, "fsl,inverted-tx", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) sport->inverted_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (of_get_property(np, "fsl,inverted-rx", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) sport->inverted_rx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static inline int imx_uart_probe_dt(struct imx_port *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static void imx_uart_probe_pdata(struct imx_port *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) sport->port.line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (pdata->flags & IMXUART_HAVE_RTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) sport->have_rtscts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (sport->tx_state == WAIT_AFTER_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) imx_uart_start_tx(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (sport->tx_state == WAIT_AFTER_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) imx_uart_stop_tx(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static int imx_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) struct imx_port *sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) u32 ucr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) int txirq, rxirq, rtsirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (!sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ret = imx_uart_probe_dt(sport, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) imx_uart_probe_pdata(sport, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) dev_err(&pdev->dev, "serial%d out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) sport->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) rxirq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (rxirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) return rxirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) txirq = platform_get_irq_optional(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) rtsirq = platform_get_irq_optional(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) sport->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) sport->port.mapbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) sport->port.membase = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) sport->port.type = PORT_IMX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) sport->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) sport->port.irq = rxirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) sport->port.fifosize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) sport->port.ops = &imx_uart_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) sport->port.rs485_config = imx_uart_rs485_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) sport->port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) timer_setup(&sport->timer, imx_uart_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) sport->gpios = mctrl_gpio_init(&sport->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (IS_ERR(sport->gpios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return PTR_ERR(sport->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) if (IS_ERR(sport->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ret = PTR_ERR(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) sport->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (IS_ERR(sport->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ret = PTR_ERR(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) sport->port.uartclk = clk_get_rate(sport->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* For register access, we only need to enable the ipg clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ret = clk_prepare_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* initialize shadow register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) sport->ucr1 = readl(sport->port.membase + UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) sport->ucr2 = readl(sport->port.membase + UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) sport->ucr3 = readl(sport->port.membase + UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) sport->ucr4 = readl(sport->port.membase + UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) sport->ufcr = readl(sport->port.membase + UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ret = uart_get_rs485_mode(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (sport->port.rs485.flags & SER_RS485_ENABLED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) (!sport->have_rtscts && !sport->have_rtsgpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * signal cannot be set low during transmission in case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) * receiver is off (limitation of the i.MX UART IP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (sport->port.rs485.flags & SER_RS485_ENABLED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) sport->have_rtscts && !sport->have_rtsgpio &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "low-active RTS not possible when receiver is off, enabling receiver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) imx_uart_rs485_config(&sport->port, &sport->port.rs485);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /* Disable interrupts before requesting them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) * and influences if UCR3_RI and UCR3_DCD changes the level of RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * and DCD (when they are outputs) or enables the respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * irqs. So set this bit early, i.e. before requesting irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) u32 ufcr = imx_uart_readl(sport, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (!(ufcr & UFCR_DCEDTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) * Disable UCR3_RI and UCR3_DCD irqs. They are also not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) * enabled later because they cannot be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) * (confirmed on i.MX25) which makes them unusable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) imx_uart_writel(sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) u32 ucr3 = UCR3_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) u32 ufcr = imx_uart_readl(sport, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) if (ufcr & UFCR_DCEDTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) if (!imx_uart_is_imx1(sport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) imx_uart_writel(sport, ucr3, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) sport->trigger_start_tx.function = imx_trigger_start_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) sport->trigger_stop_tx.function = imx_trigger_stop_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * chips only have one interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (txirq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) dev_name(&pdev->dev), sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) dev_err(&pdev->dev, "failed to request rx irq: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) dev_name(&pdev->dev), sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) dev_err(&pdev->dev, "failed to request tx irq: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) dev_name(&pdev->dev), sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) dev_err(&pdev->dev, "failed to request rts irq: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) dev_name(&pdev->dev), sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) imx_uart_ports[sport->port.line] = sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) platform_set_drvdata(pdev, sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static int imx_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) struct imx_port *sport = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static void imx_uart_restore_context(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (!sport->context_saved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) imx_uart_writel(sport, sport->saved_reg[4], UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) imx_uart_writel(sport, sport->saved_reg[5], UESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) imx_uart_writel(sport, sport->saved_reg[6], UTIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) imx_uart_writel(sport, sport->saved_reg[7], UBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) imx_uart_writel(sport, sport->saved_reg[8], UBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) imx_uart_writel(sport, sport->saved_reg[0], UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) imx_uart_writel(sport, sport->saved_reg[2], UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) imx_uart_writel(sport, sport->saved_reg[3], UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) sport->context_saved = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static void imx_uart_save_context(struct imx_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* Save necessary regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) sport->saved_reg[5] = imx_uart_readl(sport, UESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) sport->context_saved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) u32 ucr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ucr3 = imx_uart_readl(sport, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) imx_uart_writel(sport, USR1_AWAKE, USR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) ucr3 |= UCR3_AWAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ucr3 &= ~UCR3_AWAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) imx_uart_writel(sport, ucr3, UCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (sport->have_rtscts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) u32 ucr1 = imx_uart_readl(sport, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ucr1 |= UCR1_RTSDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ucr1 &= ~UCR1_RTSDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) imx_uart_writel(sport, ucr1, UCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static int imx_uart_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) struct imx_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) imx_uart_save_context(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) clk_disable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static int imx_uart_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) struct imx_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ret = clk_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) imx_uart_restore_context(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static int imx_uart_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) struct imx_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) uart_suspend_port(&imx_uart_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) disable_irq(sport->port.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) ret = clk_prepare_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) /* enable wakeup from i.MX UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) imx_uart_enable_wakeup(sport, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) static int imx_uart_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) struct imx_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /* disable wakeup from i.MX UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) imx_uart_enable_wakeup(sport, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) uart_resume_port(&imx_uart_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) enable_irq(sport->port.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) static int imx_uart_freeze(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) struct imx_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) uart_suspend_port(&imx_uart_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return clk_prepare_enable(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) static int imx_uart_thaw(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) struct imx_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) uart_resume_port(&imx_uart_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) clk_disable_unprepare(sport->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static const struct dev_pm_ops imx_uart_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .suspend_noirq = imx_uart_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .resume_noirq = imx_uart_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .freeze_noirq = imx_uart_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .restore_noirq = imx_uart_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .suspend = imx_uart_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .resume = imx_uart_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .freeze = imx_uart_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .thaw = imx_uart_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .restore = imx_uart_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static struct platform_driver imx_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .probe = imx_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .remove = imx_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .id_table = imx_uart_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .name = "imx-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .of_match_table = imx_uart_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .pm = &imx_uart_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) static int __init imx_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) int ret = uart_register_driver(&imx_uart_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) ret = platform_driver_register(&imx_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) uart_unregister_driver(&imx_uart_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) static void __exit imx_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) platform_driver_unregister(&imx_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) uart_unregister_driver(&imx_uart_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) module_init(imx_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) module_exit(imx_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) MODULE_AUTHOR("Sascha Hauer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) MODULE_DESCRIPTION("IMX generic serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) MODULE_ALIAS("platform:imx-uart");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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