^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver for the IFX spi modem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009, 2010 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jim Stanley <jim.stanley@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _IFX6X60_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _IFX6X60_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct gpio_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DRVNAME "ifx6x60"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TTYNAME "ttyIFX"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IFX_SPI_MAX_MINORS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IFX_SPI_TRANSFER_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IFX_SPI_FIFO_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IFX_SPI_HEADER_OVERHEAD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IFX_RESET_TIMEOUT msecs_to_jiffies(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* device flags bitfield definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IFX_SPI_STATE_PRESENT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IFX_SPI_STATE_IO_IN_PROGRESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IFX_SPI_STATE_IO_READY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IFX_SPI_STATE_TIMER_PENDING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IFX_SPI_STATE_IO_AVAILABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* flow control bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IFX_SPI_DCD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IFX_SPI_CTS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IFX_SPI_DSR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IFX_SPI_RI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IFX_SPI_DTR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IFX_SPI_RTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IFX_SPI_TX_FC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IFX_SPI_RX_FC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IFX_SPI_UPDATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IFX_SPI_PAYLOAD_SIZE (IFX_SPI_TRANSFER_SIZE - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IFX_SPI_HEADER_OVERHEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IFX_SPI_IRQ_TYPE DETECT_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IFX_SPI_GPIO_TARGET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IFX_SPI_GPIO0 0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IFX_SPI_STATUS_TIMEOUT (2000*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* values for bits in power status byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IFX_SPI_POWER_DATA_PENDING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IFX_SPI_POWER_SRDY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ifx_spi_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Our SPI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct spi_device *spi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Port specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct kfifo tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) spinlock_t fifo_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long signal_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* TTY Layer logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct tty_port tty_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *tty_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Low level I/O work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tasklet_struct io_work_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dma_addr_t rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dma_addr_t tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int modem; /* Modem type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int use_dma; /* provide dma-able addrs in SPI msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) long max_hz; /* max SPI frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spinlock_t write_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int write_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spinlock_t power_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned char power_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char *rx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char *tx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dma_addr_t rx_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dma_addr_t tx_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned char spi_more;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned char spi_slave_cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct timer_list spi_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct spi_message spi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct spi_transfer spi_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* gpio lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct gpio_desc *srdy; /* slave-ready gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct gpio_desc *mrdy; /* master-ready gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gpio_desc *reset; /* modem-reset gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct gpio_desc *po; /* modem-on gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gpio_desc *reset_out; /* modem-in-reset gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct gpio_desc *pmu_reset; /* PMU reset gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* state/stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int unack_srdy_int_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* modem reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long mdm_reset_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MR_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MR_INPROGRESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MR_COMPLETE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) wait_queue_head_t mdm_reset_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*swap_buf)(unsigned char *buf, int len, void *end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* _IFX6X60_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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