^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * icom.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 IBM Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Serial device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on code from serial.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/termios.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kref.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "icom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*#define ICOM_TRACE enable port trace capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ICOM_DRIVER_NAME "icom"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ICOM_VERSION_STR "1.3.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NR_PORTS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ICOM_PORT ((struct icom_port *)port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define to_icom_adapter(d) container_of(d, struct icom_adapter, kref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct pci_device_id icom_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .driver_data = ADAPTER_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .subvendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .driver_data = ADAPTER_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .subvendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .driver_data = ADAPTER_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .subvendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .subdevice = PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .driver_data = ADAPTER_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .subvendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .driver_data = ADAPTER_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct lookup_proc_table start_proc[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {NULL, ICOM_CONTROL_START_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {NULL, ICOM_CONTROL_START_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {NULL, ICOM_CONTROL_START_C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {NULL, ICOM_CONTROL_START_D}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct lookup_proc_table stop_proc[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {NULL, ICOM_CONTROL_STOP_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {NULL, ICOM_CONTROL_STOP_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {NULL, ICOM_CONTROL_STOP_C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {NULL, ICOM_CONTROL_STOP_D}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct lookup_int_table int_mask_tbl[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {NULL, ICOM_INT_MASK_PRC_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {NULL, ICOM_INT_MASK_PRC_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {NULL, ICOM_INT_MASK_PRC_C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {NULL, ICOM_INT_MASK_PRC_D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODULE_DEVICE_TABLE(pci, icom_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static LIST_HEAD(icom_adapter_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* spinlock for adapter initialization and changing adapter operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static spinlock_t icom_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef ICOM_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void trace(struct icom_port *icom_port, char *trace_pt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long trace_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_info(&icom_port->adapter->pci_dev->dev, ":%d:%s - %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) icom_port->port, trace_pt, trace_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void trace(struct icom_port *icom_port, char *trace_pt, unsigned long trace_data) {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void icom_kref_release(struct kref *kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void free_port_memory(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pci_dev *dev = icom_port->adapter->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) trace(icom_port, "RET_PORT_MEM", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (icom_port->recv_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dma_free_coherent(&dev->dev, 4096, icom_port->recv_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) icom_port->recv_buf_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) icom_port->recv_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (icom_port->xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dma_free_coherent(&dev->dev, 4096, icom_port->xmit_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) icom_port->xmit_buf_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) icom_port->xmit_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (icom_port->statStg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dma_free_coherent(&dev->dev, 4096, icom_port->statStg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) icom_port->statStg_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) icom_port->statStg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (icom_port->xmitRestart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dma_free_coherent(&dev->dev, 4096, icom_port->xmitRestart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) icom_port->xmitRestart_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) icom_port->xmitRestart = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int get_port_memory(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long stgAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long startStgAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct pci_dev *dev = icom_port->adapter->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) icom_port->xmit_buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dma_alloc_coherent(&dev->dev, 4096, &icom_port->xmit_buf_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!icom_port->xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(&dev->dev, "Can not allocate Transmit buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) trace(icom_port, "GET_PORT_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (unsigned long) icom_port->xmit_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) icom_port->recv_buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dma_alloc_coherent(&dev->dev, 4096, &icom_port->recv_buf_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!icom_port->recv_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(&dev->dev, "Can not allocate Receive buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) free_port_memory(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) trace(icom_port, "GET_PORT_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (unsigned long) icom_port->recv_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) icom_port->statStg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dma_alloc_coherent(&dev->dev, 4096, &icom_port->statStg_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!icom_port->statStg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_err(&dev->dev, "Can not allocate Status buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) free_port_memory(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) trace(icom_port, "GET_PORT_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (unsigned long) icom_port->statStg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) icom_port->xmitRestart =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dma_alloc_coherent(&dev->dev, 4096, &icom_port->xmitRestart_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!icom_port->xmitRestart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "Can not allocate xmit Restart buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) free_port_memory(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* FODs: Frame Out Descriptor Queue, this is a FIFO queue that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) indicates that frames are to be transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) stgAddr = (unsigned long) icom_port->statStg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (index = 0; index < NUM_XBUFFS; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) trace(icom_port, "FOD_ADDR", stgAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) stgAddr = stgAddr + sizeof(icom_port->statStg->xmit[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (index < (NUM_XBUFFS - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) icom_port->statStg->xmit[index].leLengthASD =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) trace(icom_port, "FOD_ADDR", stgAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) trace(icom_port, "FOD_XBUFF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (unsigned long) icom_port->xmit_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) icom_port->statStg->xmit[index].leBuffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cpu_to_le32(icom_port->xmit_buf_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else if (index == (NUM_XBUFFS - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) icom_port->statStg->xmit[index].leLengthASD =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) trace(icom_port, "FOD_XBUFF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (unsigned long) icom_port->xmit_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) icom_port->statStg->xmit[index].leBuffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cpu_to_le32(icom_port->xmit_buf_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* FIDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) startStgAddr = stgAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* fill in every entry, even if no buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (index = 0; index < NUM_RBUFFS; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) trace(icom_port, "FID_ADDR", stgAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) stgAddr = stgAddr + sizeof(icom_port->statStg->rcv[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) icom_port->statStg->rcv[index].leLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) icom_port->statStg->rcv[index].WorkingLength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (index < (NUM_RBUFFS - 1) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) offset = stgAddr - (unsigned long) icom_port->statStg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) icom_port->statStg->rcv[index].leNext =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cpu_to_le32(icom_port-> statStg_pci + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) trace(icom_port, "FID_RBUFF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (unsigned long) icom_port->recv_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) icom_port->statStg->rcv[index].leBuffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cpu_to_le32(icom_port->recv_buf_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else if (index == (NUM_RBUFFS -1) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) offset = startStgAddr - (unsigned long) icom_port->statStg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) icom_port->statStg->rcv[index].leNext =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cpu_to_le32(icom_port-> statStg_pci + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) trace(icom_port, "FID_RBUFF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (unsigned long) icom_port->recv_buf + 2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) icom_port->statStg->rcv[index].leBuffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cpu_to_le32(icom_port->recv_buf_pci + 2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) icom_port->statStg->rcv[index].leNext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) icom_port->statStg->rcv[index].leBuffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void stop_processor(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_lock_irqsave(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) port = icom_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (port >= ARRAY_SIZE(stop_proc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(&icom_port->adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "Invalid port assignment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (port == 0 || port == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) stop_proc[port].global_control_reg = &icom_port->global_reg->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) stop_proc[port].global_control_reg = &icom_port->global_reg->control_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) temp = readl(stop_proc[port].global_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) temp = (temp & ~start_proc[port].processor_id) | stop_proc[port].processor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(temp, stop_proc[port].global_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* write flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) readl(stop_proc[port].global_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spin_unlock_irqrestore(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void start_processor(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_lock_irqsave(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) port = icom_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (port >= ARRAY_SIZE(start_proc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(&icom_port->adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "Invalid port assignment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (port == 0 || port == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) start_proc[port].global_control_reg = &icom_port->global_reg->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) start_proc[port].global_control_reg = &icom_port->global_reg->control_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) temp = readl(start_proc[port].global_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) temp = (temp & ~stop_proc[port].processor_id) | start_proc[port].processor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writel(temp, start_proc[port].global_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* write flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) readl(start_proc[port].global_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irqrestore(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void load_code(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) char __iomem *iram_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void __iomem *dram_ptr = icom_port->dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dma_addr_t temp_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned char *new_page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned char cable_id = NO_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct pci_dev *dev = icom_port->adapter->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Clear out any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) writew(0x3FFF, icom_port->int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) trace(icom_port, "CLEAR_INTERRUPTS", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Stop processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) stop_processor(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Zero out DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) memset_io(dram_ptr, 0, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Load Call Setup into Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (request_firmware(&fw, "icom_call_setup.bin", &dev->dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(&dev->dev,"Unable to load icom_call_setup.bin firmware image\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (fw->size > ICOM_DCE_IRAM_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(&dev->dev, "Invalid firmware image for icom_call_setup.bin found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) iram_ptr = (char __iomem *)icom_port->dram + ICOM_IRAM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (index = 0; index < fw->size; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writeb(fw->data[index], &iram_ptr[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Load Resident DCE portion of Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (request_firmware(&fw, "icom_res_dce.bin", &dev->dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(&dev->dev,"Unable to load icom_res_dce.bin firmware image\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (fw->size > ICOM_IRAM_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&dev->dev, "Invalid firmware image for icom_res_dce.bin found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) iram_ptr = (char __iomem *) icom_port->dram + ICOM_IRAM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (index = ICOM_DCE_IRAM_OFFSET; index < fw->size; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writeb(fw->data[index], &iram_ptr[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Set Hardware level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (icom_port->adapter->version == ADAPTER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writeb(V2_HARDWARE, &(icom_port->dram->misc_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Start the processor in Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) start_processor(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writeb((HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &(icom_port->dram->HDLCConfigReg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writeb(0x00, &(icom_port->dram->CmdReg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writeb(0x10, &(icom_port->dram->async_config3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writeb((ICOM_ACFG_DRIVE1 | ICOM_ACFG_NO_PARITY | ICOM_ACFG_8BPC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ICOM_ACFG_1STOP_BIT), &(icom_port->dram->async_config2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*Set up data in icom DRAM to indicate where personality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *code is located and its length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) new_page = dma_alloc_coherent(&dev->dev, 4096, &temp_pci, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!new_page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_err(&dev->dev, "Can not allocate DMA buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (request_firmware(&fw, "icom_asc.bin", &dev->dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(&dev->dev,"Unable to load icom_asc.bin firmware image\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (fw->size > ICOM_DCE_IRAM_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(&dev->dev, "Invalid firmware image for icom_asc.bin found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto load_code_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) for (index = 0; index < fw->size; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) new_page[index] = fw->data[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) writeb((char) ((fw->size + 16)/16), &icom_port->dram->mac_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) writel(temp_pci, &icom_port->dram->mac_load_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*Setting the syncReg to 0x80 causes adapter to start downloading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) the personality code into adapter instruction RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) Once code is loaded, it will begin executing and, based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) information provided above, will start DMAing data from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) shared memory to adapter DRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* the wait loop below verifies this write operation has been done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) and processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writeb(START_DOWNLOAD, &icom_port->dram->sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Wait max 1 Sec for data download and processor to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (index = 0; index < 10; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (readb(&icom_port->dram->misc_flags) & ICOM_HDW_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (index == 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * check Cable ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cable_id = readb(&icom_port->dram->cable_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (cable_id & ICOM_CABLE_ID_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Get cable ID into the lower 4 bits (standard form) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cable_id = (cable_id & ICOM_CABLE_ID_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) icom_port->cable_id = cable_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(&dev->dev,"Invalid or no cable attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) icom_port->cable_id = NO_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) load_code_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Clear out any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writew(0x3FFF, icom_port->int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Turn off port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writeb(ICOM_DISABLE, &(icom_port->dram->disable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Stop processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) stop_processor(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(&icom_port->adapter->pci_dev->dev,"Port not operational\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (new_page != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dma_free_coherent(&dev->dev, 4096, new_page, temp_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int startup(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned long temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned char cable_id, raw_cable_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) trace(icom_port, "STARTUP", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!icom_port->dram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* should NEVER be NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(&icom_port->adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "Unusable Port, port configuration missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * check Cable ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) raw_cable_id = readb(&icom_port->dram->cable_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) trace(icom_port, "CABLE_ID", raw_cable_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Get cable ID into the lower 4 bits (standard form) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cable_id = (raw_cable_id & ICOM_CABLE_ID_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Check for valid Cable ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!(raw_cable_id & ICOM_CABLE_ID_VALID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) (cable_id != icom_port->cable_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* reload adapter code, pick up any potential changes in cable id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) load_code(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* still no sign of cable, error out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) raw_cable_id = readb(&icom_port->dram->cable_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cable_id = (raw_cable_id & ICOM_CABLE_ID_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!(raw_cable_id & ICOM_CABLE_ID_VALID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) (icom_port->cable_id == NO_CABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Finally, clear and enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) spin_lock_irqsave(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) port = icom_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (port >= ARRAY_SIZE(int_mask_tbl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(&icom_port->adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "Invalid port assignment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (port == 0 || port == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (port == 0 || port == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) writew(0x00FF, icom_port->int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writew(0x3F00, icom_port->int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) temp = readl(int_mask_tbl[port].global_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writel(temp & ~int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* write flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) readl(int_mask_tbl[port].global_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_unlock_irqrestore(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void shutdown(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned long temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) spin_lock_irqsave(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) trace(icom_port, "SHUTDOWN", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * disable all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) port = icom_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (port >= ARRAY_SIZE(int_mask_tbl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(&icom_port->adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "Invalid port assignment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (port == 0 || port == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) temp = readl(int_mask_tbl[port].global_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) writel(temp | int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* write flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) readl(int_mask_tbl[port].global_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) spin_unlock_irqrestore(&icom_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * disable break condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cmdReg = readb(&icom_port->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (cmdReg & CMD_SND_BREAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int icom_write(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned long data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int temp_tail = port->state->xmit.tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) trace(ICOM_PORT, "WRITE", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SA_FLAGS_READY_TO_XMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) trace(ICOM_PORT, "WRITE_FULL", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) data_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) while ((port->state->xmit.head != temp_tail) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) (data_count <= XMIT_BUFF_SZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ICOM_PORT->xmit_buf[data_count++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) port->state->xmit.buf[temp_tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) temp_tail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) temp_tail &= (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (data_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ICOM_PORT->statStg->xmit[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) cpu_to_le16(SA_FLAGS_READY_TO_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ICOM_PORT->statStg->xmit[0].leLength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cpu_to_le16(data_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) (unsigned long) &ICOM_PORT->statStg->xmit[0] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) (unsigned long) ICOM_PORT->statStg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *ICOM_PORT->xmitRestart =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) cpu_to_le32(ICOM_PORT->statStg_pci + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cmdReg = readb(&ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writeb(cmdReg | CMD_XMIT_RCV_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writeb(START_XMIT, &ICOM_PORT->dram->StartXmitCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) trace(ICOM_PORT, "WRITE_START", data_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* write flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) readb(&ICOM_PORT->dram->StartXmitCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static inline void check_modem_status(struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static char old_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) char delta_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) spin_lock(&icom_port->uart_port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*modem input register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) status = readb(&icom_port->dram->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) trace(icom_port, "CHECK_MODEM", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) delta_status = status ^ old_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (delta_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (delta_status & ICOM_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) icom_port->uart_port.icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (delta_status & ICOM_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) icom_port->uart_port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (delta_status & ICOM_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uart_handle_dcd_change(&icom_port->uart_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) delta_status & ICOM_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (delta_status & ICOM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) uart_handle_cts_change(&icom_port->uart_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) delta_status & ICOM_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) wake_up_interruptible(&icom_port->uart_port.state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) old_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) spin_unlock(&icom_port->uart_port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned short int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (port_int_reg & (INT_XMIT_COMPLETED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) trace(icom_port, "XMIT_COMPLETE", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* clear buffer in use bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) icom_port->statStg->xmit[0].flags &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) cpu_to_le16(~SA_FLAGS_READY_TO_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) count = (unsigned short int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cpu_to_le16(icom_port->statStg->xmit[0].leLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) icom_port->uart_port.icount.tx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) for (i=0; i<count &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) !uart_circ_empty(&icom_port->uart_port.state->xmit); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) icom_port->uart_port.state->xmit.tail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) icom_port->uart_port.state->xmit.tail &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!icom_write(&icom_port->uart_port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* activate write queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) uart_write_wakeup(&icom_port->uart_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) trace(icom_port, "XMIT_DISABLED", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) short int count, rcv_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct tty_port *port = &icom_port->uart_port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned short int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct uart_icount *icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) trace(icom_port, "RCV_COMPLETE", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) rcv_buff = icom_port->next_rcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) while (status & SA_FL_RCV_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int first = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) trace(icom_port, "FID_STATUS", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) count = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].leLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) trace(icom_port, "RCV_COUNT", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) trace(icom_port, "REAL_COUNT", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) cpu_to_le32(icom_port->statStg->rcv[rcv_buff].leBuffer) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) icom_port->recv_buf_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Block copy all but the last byte as this may have status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) first = icom_port->recv_buf[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) tty_insert_flip_string(port, icom_port->recv_buf + offset, count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) icount = &icom_port->uart_port.icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) icount->rx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Break detect logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if ((status & SA_FLAGS_FRAME_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) && first == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) status &= ~SA_FLAGS_FRAME_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) status |= SA_FLAGS_BREAK_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) trace(icom_port, "BREAK_DET", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) (SA_FLAGS_BREAK_DET | SA_FLAGS_PARITY_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) SA_FLAGS_FRAME_ERROR | SA_FLAGS_OVERRUN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (status & SA_FLAGS_BREAK_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) icount->brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (status & SA_FLAGS_PARITY_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) icount->parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (status & SA_FLAGS_FRAME_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) icount->frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (status & SA_FLAGS_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) icount->overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * Now check to see if character should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * ignored, and mask off conditions which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * should be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (status & icom_port->ignore_status_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) trace(icom_port, "IGNORE_CHAR", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto ignore_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) status &= icom_port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (status & SA_FLAGS_BREAK_DET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else if (status & SA_FLAGS_PARITY_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) trace(icom_port, "PARITY_ERROR", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } else if (status & SA_FLAGS_FRAME_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) tty_insert_flip_char(port, *(icom_port->recv_buf + offset + count - 1), flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (status & SA_FLAGS_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Overrun is special, since it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * reported immediately, and doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * affect the current character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) tty_insert_flip_char(port, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ignore_char:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) icom_port->statStg->rcv[rcv_buff].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) icom_port->statStg->rcv[rcv_buff].leLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) icom_port->statStg->rcv[rcv_buff].WorkingLength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rcv_buff++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (rcv_buff == NUM_RBUFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) rcv_buff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) icom_port->next_rcv = rcv_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) spin_unlock(&icom_port->uart_port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) spin_lock(&icom_port->uart_port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void process_interrupt(u16 port_int_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct icom_port *icom_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) spin_lock(&icom_port->uart_port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) trace(icom_port, "INTERRUPT", port_int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (port_int_reg & (INT_XMIT_COMPLETED | INT_XMIT_DISABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) xmit_interrupt(port_int_reg, icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (port_int_reg & INT_RCV_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) recv_interrupt(port_int_reg, icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spin_unlock(&icom_port->uart_port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static irqreturn_t icom_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) void __iomem * int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 adapter_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u16 port_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct icom_adapter *icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct icom_port *icom_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* find icom_port for this interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) icom_adapter = (struct icom_adapter *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (icom_adapter->version == ADAPTER_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int_reg = icom_adapter->base_addr + 0x8024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) adapter_interrupts = readl(int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (adapter_interrupts & 0x00003FFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* port 2 interrupt, NOTE: for all ADAPTER_V2, port 2 will be active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) icom_port = &icom_adapter->port_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) port_int_reg = (u16) adapter_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) process_interrupt(port_int_reg, icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) check_modem_status(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (adapter_interrupts & 0x3FFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* port 3 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) icom_port = &icom_adapter->port_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (icom_port->status == ICOM_PORT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) port_int_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) (u16) (adapter_interrupts >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) process_interrupt(port_int_reg, icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) check_modem_status(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* Clear out any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) writel(adapter_interrupts, int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int_reg = icom_adapter->base_addr + 0x8004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int_reg = icom_adapter->base_addr + 0x4004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) adapter_interrupts = readl(int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (adapter_interrupts & 0x00003FFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* port 0 interrupt, NOTE: for all adapters, port 0 will be active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) icom_port = &icom_adapter->port_info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) port_int_reg = (u16) adapter_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) process_interrupt(port_int_reg, icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) check_modem_status(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (adapter_interrupts & 0x3FFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* port 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) icom_port = &icom_adapter->port_info[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (icom_port->status == ICOM_PORT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) port_int_reg = (u16) (adapter_interrupts >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) process_interrupt(port_int_reg, icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) check_modem_status(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Clear out any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) writel(adapter_interrupts, int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* flush the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) adapter_interrupts = readl(int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * ------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * Begin serial-core API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * ------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static unsigned int icom_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SA_FLAGS_READY_TO_XMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret = TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static void icom_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned char local_osr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) trace(ICOM_PORT, "SET_MODEM", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) local_osr = readb(&ICOM_PORT->dram->osr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (mctrl & TIOCM_RTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) trace(ICOM_PORT, "RAISE_RTS", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) local_osr |= ICOM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) trace(ICOM_PORT, "LOWER_RTS", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) local_osr &= ~ICOM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (mctrl & TIOCM_DTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) trace(ICOM_PORT, "RAISE_DTR", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) local_osr |= ICOM_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) trace(ICOM_PORT, "LOWER_DTR", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) local_osr &= ~ICOM_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) writeb(local_osr, &ICOM_PORT->dram->osr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static unsigned int icom_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) unsigned int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) trace(ICOM_PORT, "GET_MODEM", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) status = readb(&ICOM_PORT->dram->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) result = ((status & ICOM_DCD) ? TIOCM_CAR : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) | ((status & ICOM_RI) ? TIOCM_RNG : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) | ((status & ICOM_DSR) ? TIOCM_DSR : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) | ((status & ICOM_CTS) ? TIOCM_CTS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void icom_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) trace(ICOM_PORT, "STOP", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) cmdReg = readb(&ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) writeb(cmdReg | CMD_HOLD_XMIT, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void icom_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) trace(ICOM_PORT, "START", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) cmdReg = readb(&ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if ((cmdReg & CMD_HOLD_XMIT) == CMD_HOLD_XMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) writeb(cmdReg & ~CMD_HOLD_XMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) icom_write(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static void icom_send_xchar(struct uart_port *port, char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned char xdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) trace(ICOM_PORT, "SEND_XCHAR", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* wait .1 sec to send char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) for (index = 0; index < 10; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) xdata = readb(&ICOM_PORT->dram->xchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (xdata == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) trace(ICOM_PORT, "QUICK_WRITE", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) writeb(ch, &ICOM_PORT->dram->xchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* flush write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) xdata = readb(&ICOM_PORT->dram->xchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static void icom_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) cmdReg = readb(&ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static void icom_break(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) trace(ICOM_PORT, "BREAK", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) cmdReg = readb(&ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (break_state == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) writeb(cmdReg | CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) writeb(cmdReg & ~CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int icom_open(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) kref_get(&ICOM_PORT->adapter->kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) retval = startup(ICOM_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) trace(ICOM_PORT, "STARTUP_ERROR", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static void icom_close(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned char cmdReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) trace(ICOM_PORT, "CLOSE", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* stop receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) cmdReg = readb(&ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) shutdown(ICOM_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static void icom_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) unsigned cflag, iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) char new_config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) char new_config3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) char tmp_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int rcv_buff, xmit_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) trace(ICOM_PORT, "CHANGE_SPEED", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) cflag = termios->c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) iflag = termios->c_iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) new_config2 = ICOM_ACFG_DRIVE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* byte size and parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) switch (cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case CS5: /* 5 bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) new_config2 |= ICOM_ACFG_5BPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) case CS6: /* 6 bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) new_config2 |= ICOM_ACFG_6BPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case CS7: /* 7 bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) new_config2 |= ICOM_ACFG_7BPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case CS8: /* 8 bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) new_config2 |= ICOM_ACFG_8BPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (cflag & CSTOPB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* 2 stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) new_config2 |= ICOM_ACFG_2STOP_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* parity bit enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) new_config2 |= ICOM_ACFG_PARITY_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) trace(ICOM_PORT, "PARENB", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (cflag & PARODD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* odd parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) new_config2 |= ICOM_ACFG_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) trace(ICOM_PORT, "PARODD", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Determine divisor based on baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) baud = uart_get_baud_rate(port, termios, old_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) icom_acfg_baud[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) icom_acfg_baud[BAUD_TABLE_LIMIT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (!baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) baud = 9600; /* B0 transition handled in rs_set_termios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) for (index = 0; index < BAUD_TABLE_LIMIT; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (icom_acfg_baud[index] == baud) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) new_config3 = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) uart_update_timeout(port, cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* CTS flow control flag and modem status interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (cflag & CRTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) tmp_byte |= HDLC_HDW_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) tmp_byte &= ~HDLC_HDW_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * Set up parity check flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ICOM_PORT->read_status_mask = SA_FLAGS_OVERRUN | SA_FL_RCV_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ICOM_PORT->read_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SA_FLAGS_FRAME_ERROR | SA_FLAGS_PARITY_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if ((iflag & BRKINT) || (iflag & PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ICOM_PORT->read_status_mask |= SA_FLAGS_BREAK_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ICOM_PORT->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ICOM_PORT->ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SA_FLAGS_PARITY_ERROR | SA_FLAGS_FRAME_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ICOM_PORT->ignore_status_mask |= SA_FLAGS_BREAK_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * If we're ignore parity and break indicators, ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * overruns too. (For real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ICOM_PORT->ignore_status_mask |= SA_FLAGS_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * !!! ignore all characters if CREAD is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if ((cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ICOM_PORT->ignore_status_mask |= SA_FL_RCV_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Turn off Receiver to prepare for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) writeb(CMD_RCV_DISABLE, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) for (index = 0; index < 10; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (readb(&ICOM_PORT->dram->PrevCmdReg) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* clear all current buffers of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) for (rcv_buff = 0; rcv_buff < NUM_RBUFFS; rcv_buff++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ICOM_PORT->statStg->rcv[rcv_buff].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ICOM_PORT->statStg->rcv[rcv_buff].leLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ICOM_PORT->statStg->rcv[rcv_buff].WorkingLength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) for (xmit_buff = 0; xmit_buff < NUM_XBUFFS; xmit_buff++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ICOM_PORT->statStg->xmit[xmit_buff].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* activate changes and start xmit and receiver here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* Enable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) writeb(new_config3, &(ICOM_PORT->dram->async_config3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) writeb(new_config2, &(ICOM_PORT->dram->async_config2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) tmp_byte |= HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) writeb(0x04, &(ICOM_PORT->dram->FlagFillIdleTimer)); /* 0.5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) writeb(0xFF, &(ICOM_PORT->dram->ier)); /* enable modem signal interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* reset processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) writeb(CMD_RESTART, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) for (index = 0; index < 10; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (readb(&ICOM_PORT->dram->CmdReg) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Enable Transmitter and Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) (unsigned long) &ICOM_PORT->statStg->rcv[0] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) (unsigned long) ICOM_PORT->statStg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) writel(ICOM_PORT->statStg_pci + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) &ICOM_PORT->dram->RcvStatusAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ICOM_PORT->next_rcv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ICOM_PORT->put_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) *ICOM_PORT->xmitRestart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) writel(ICOM_PORT->xmitRestart_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) &ICOM_PORT->dram->XmitStatusAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) trace(ICOM_PORT, "XR_ENAB", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) writeb(CMD_XMIT_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const char *icom_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return "icom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static void icom_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int icom_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static void icom_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) port->type = PORT_ICOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const struct uart_ops icom_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .tx_empty = icom_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .set_mctrl = icom_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .get_mctrl = icom_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .stop_tx = icom_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .start_tx = icom_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .send_xchar = icom_send_xchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .stop_rx = icom_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .break_ctl = icom_break,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .startup = icom_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .shutdown = icom_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .set_termios = icom_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .type = icom_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .release_port = icom_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .request_port = icom_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .config_port = icom_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define ICOM_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static struct uart_driver icom_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .driver_name = ICOM_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .dev_name = "ttyA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .major = ICOM_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .minor = ICOM_MINOR_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .nr = NR_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .cons = ICOM_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int icom_init_ports(struct icom_adapter *icom_adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 subsystem_id = icom_adapter->subsystem_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct icom_port *icom_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (icom_adapter->version == ADAPTER_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) icom_adapter->numb_ports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) icom_port = &icom_adapter->port_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) icom_port->port = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) icom_port->status = ICOM_PORT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) icom_port->imbed_modem = ICOM_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (subsystem_id == PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) icom_adapter->numb_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) icom_port = &icom_adapter->port_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) icom_port->port = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) icom_port->status = ICOM_PORT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) icom_port->imbed_modem = ICOM_IMBED_MODEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) icom_adapter->numb_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) icom_adapter->port_info[0].port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) icom_adapter->port_info[0].status = ICOM_PORT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (subsystem_id ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) icom_adapter->port_info[0].imbed_modem = ICOM_IMBED_MODEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) icom_adapter->port_info[0].imbed_modem = ICOM_RVX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) icom_adapter->port_info[1].status = ICOM_PORT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) icom_adapter->port_info[2].port = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) icom_adapter->port_info[2].status = ICOM_PORT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) icom_adapter->port_info[2].imbed_modem = ICOM_RVX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) icom_adapter->port_info[3].status = ICOM_PORT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static void icom_port_active(struct icom_port *icom_port, struct icom_adapter *icom_adapter, int port_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (icom_adapter->version == ADAPTER_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) icom_port->global_reg = icom_adapter->base_addr + 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) icom_port->int_reg = icom_adapter->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) 0x4004 + 2 - 2 * port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) icom_port->global_reg = icom_adapter->base_addr + 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (icom_port->port < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) icom_port->int_reg = icom_adapter->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) 0x8004 + 2 - 2 * icom_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) icom_port->int_reg = icom_adapter->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) 0x8024 + 2 - 2 * (icom_port->port - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int icom_load_ports(struct icom_adapter *icom_adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct icom_port *icom_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) int port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) for (port_num = 0; port_num < icom_adapter->numb_ports; port_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) icom_port = &icom_adapter->port_info[port_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (icom_port->status == ICOM_PORT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) icom_port_active(icom_port, icom_adapter, port_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) icom_port->dram = icom_adapter->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) 0x2000 * icom_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) icom_port->adapter = icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* get port memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (get_port_memory(icom_port) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) dev_err(&icom_port->adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) "Memory allocation for port FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int icom_alloc_adapter(struct icom_adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) **icom_adapter_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int adapter_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct icom_adapter *icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct icom_adapter *cur_adapter_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct list_head *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) icom_adapter = kzalloc(sizeof(struct icom_adapter), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (!icom_adapter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) list_for_each(tmp, &icom_adapter_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) cur_adapter_entry =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) list_entry(tmp, struct icom_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) icom_adapter_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (cur_adapter_entry->index != adapter_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) adapter_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) icom_adapter->index = adapter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) list_add_tail(&icom_adapter->icom_adapter_entry, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) *icom_adapter_ref = icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static void icom_free_adapter(struct icom_adapter *icom_adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) list_del(&icom_adapter->icom_adapter_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) kfree(icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static void icom_remove_adapter(struct icom_adapter *icom_adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct icom_port *icom_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) for (index = 0; index < icom_adapter->numb_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) icom_port = &icom_adapter->port_info[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (icom_port->status == ICOM_PORT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_info(&icom_adapter->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) "Device removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) uart_remove_one_port(&icom_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) &icom_port->uart_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* be sure that DTR and RTS are dropped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) writeb(0x00, &icom_port->dram->osr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* Wait 0.1 Sec for simple Init to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* Stop proccessor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) stop_processor(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) free_port_memory(icom_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) free_irq(icom_adapter->pci_dev->irq, (void *) icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) iounmap(icom_adapter->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pci_release_regions(icom_adapter->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) icom_free_adapter(icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static void icom_kref_release(struct kref *kref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct icom_adapter *icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) icom_adapter = to_icom_adapter(kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) icom_remove_adapter(icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static int icom_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) unsigned int command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct icom_adapter *icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct icom_port *icom_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) retval = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dev_err(&dev->dev, "Device enable FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) retval = pci_request_regions(dev, "icom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_err(&dev->dev, "pci_request_regions FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dev_err(&dev->dev, "PCI Config read FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) pci_write_config_dword(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (ent->driver_data == ADAPTER_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pci_write_config_dword(dev, 0x44, 0x8300830A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) pci_write_config_dword(dev, 0x44, 0x42004200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pci_write_config_dword(dev, 0x48, 0x42004200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) retval = icom_alloc_adapter(&icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_err(&dev->dev, "icom_alloc_adapter FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) goto probe_exit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) icom_adapter->base_addr_pci = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) icom_adapter->pci_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) icom_adapter->version = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) icom_adapter->subsystem_id = ent->subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) retval = icom_init_ports(icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dev_err(&dev->dev, "Port configuration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) goto probe_exit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) icom_adapter->base_addr = pci_ioremap_bar(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (!icom_adapter->base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) goto probe_exit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* save off irq and request irq line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) retval = request_irq(dev->irq, icom_interrupt, IRQF_SHARED, ICOM_DRIVER_NAME, (void *)icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) goto probe_exit2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) retval = icom_load_ports(icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) for (index = 0; index < icom_adapter->numb_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) icom_port = &icom_adapter->port_info[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (icom_port->status == ICOM_PORT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) icom_port->uart_port.irq = icom_port->adapter->pci_dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) icom_port->uart_port.type = PORT_ICOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) icom_port->uart_port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) icom_port->uart_port.membase =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) (unsigned char __iomem *)icom_adapter->base_addr_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) icom_port->uart_port.fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) icom_port->uart_port.ops = &icom_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) icom_port->uart_port.line =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) icom_port->port + icom_adapter->index * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (uart_add_one_port (&icom_uart_driver, &icom_port->uart_port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) icom_port->status = ICOM_PORT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev_err(&dev->dev, "Device add failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) dev_info(&dev->dev, "Device added\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) kref_init(&icom_adapter->kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) probe_exit2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) iounmap(icom_adapter->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) probe_exit1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) icom_free_adapter(icom_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) probe_exit0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void icom_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct icom_adapter *icom_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct list_head *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) list_for_each(tmp, &icom_adapter_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) icom_adapter = list_entry(tmp, struct icom_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) icom_adapter_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (icom_adapter->pci_dev == dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) kref_put(&icom_adapter->kref, icom_kref_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_err(&dev->dev, "Unable to find device to remove\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static struct pci_driver icom_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .name = ICOM_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .id_table = icom_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .probe = icom_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .remove = icom_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static int __init icom_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) spin_lock_init(&icom_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ret = uart_register_driver(&icom_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ret = pci_register_driver(&icom_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) uart_unregister_driver(&icom_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static void __exit icom_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pci_unregister_driver(&icom_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) uart_unregister_driver(&icom_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) module_init(icom_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) module_exit(icom_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) MODULE_AUTHOR("Michael Anderson <mjanders@us.ibm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MODULE_DESCRIPTION("IBM iSeries Serial IOA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MODULE_SUPPORTED_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ("IBM iSeries 2745, 2771, 2772, 2742, 2793 and 2805 Communications adapters");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) MODULE_FIRMWARE("icom_call_setup.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) MODULE_FIRMWARE("icom_res_dce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) MODULE_FIRMWARE("icom_asc.bin");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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