^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/efm32-uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRIVER_NAME "efm32-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEV_NAME "ttyefm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UARTn_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UARTn_CTRL_SYNC 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UARTn_CTRL_TXBIL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UARTn_FRAME 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UARTn_FRAME_DATABITS__MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UARTn_FRAME_DATABITS(n) ((n) - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UARTn_FRAME_PARITY__MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UARTn_FRAME_PARITY_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UARTn_FRAME_PARITY_EVEN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UARTn_FRAME_PARITY_ODD 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UARTn_FRAME_STOPBITS_HALF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UARTn_FRAME_STOPBITS_ONE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UARTn_FRAME_STOPBITS_TWO 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UARTn_CMD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UARTn_CMD_RXEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UARTn_CMD_RXDIS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UARTn_CMD_TXEN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UARTn_CMD_TXDIS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UARTn_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UARTn_STATUS_TXENS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UARTn_STATUS_TXC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UARTn_STATUS_TXBL 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UARTn_STATUS_RXDATAV 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UARTn_CLKDIV 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UARTn_RXDATAX 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UARTn_RXDATAX_RXDATA__MASK 0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UARTn_RXDATAX_PERR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UARTn_RXDATAX_FERR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * This is a software only flag used for ignore_status_mask and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * read_status_mask! It's used for breaks that the hardware doesn't report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * explicitly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SW_UARTn_RXDATAX_BERR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UARTn_TXDATA 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UARTn_IF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UARTn_IF_TXC 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UARTn_IF_TXBL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UARTn_IF_RXDATAV 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UARTn_IF_RXOF 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UARTn_IFS 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UARTn_IFC 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UARTn_IEN 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UARTn_ROUTE 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UARTn_ROUTE_LOCATION__MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UARTn_ROUTE_RXPEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UARTn_ROUTE_TXPEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct efm32_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int txirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct efm32_uart_pdata pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define efm_debug(efm_port, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_dbg(efm_port->port.dev, format, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void efm32_uart_write32(struct efm32_uart_port *efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 value, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel_relaxed(value, efm_port->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return readl_relaxed(efm_port->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static unsigned int efm32_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (status & UARTn_STATUS_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* sorry, neither handshaking lines nor loop functionallity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* sorry, no handshaking lines available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void efm32_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) efm32_uart_write32(efm_port, ien, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct uart_port *port = &efm_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) while (efm32_uart_read32(efm_port, UARTn_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) UARTn_STATUS_TXBL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) efm32_uart_write32(efm_port, port->x_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) UARTn_TXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) UARTn_TXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!port->x_char && uart_circ_empty(xmit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) efm32_uart_read32(efm_port, UARTn_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) UARTn_STATUS_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) efm32_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void efm32_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) efm32_uart_write32(efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ien = efm32_uart_read32(efm_port, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) efm32_uart_write32(efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) efm32_uart_tx_chars(efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void efm32_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* not possible without fiddling with gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct uart_port *port = &efm_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) while (efm32_uart_read32(efm_port, UARTn_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) UARTn_STATUS_RXDATAV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * This is a reserved bit and I only saw it read as 0. But to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * sure not to be confused too much by new devices adhere to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * warning in the reference manual that reserved bits might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * read as 1 in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rxdata &= ~SW_UARTn_RXDATAX_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if ((rxdata & UARTn_RXDATAX_FERR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rxdata |= SW_UARTn_RXDATAX_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else if (rxdata & UARTn_RXDATAX_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else if (rxdata & UARTn_RXDATAX_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rxdata &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (rxdata & SW_UARTn_RXDATAX_BERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else if (rxdata & UARTn_RXDATAX_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else if (rxdata & UARTn_RXDATAX_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else if (uart_handle_sysrq_char(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rxdata & UARTn_RXDATAX_RXDATA__MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((rxdata & port->ignore_status_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tty_insert_flip_char(&port->state->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static irqreturn_t efm32_uart_rxirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct efm32_uart_port *efm_port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct uart_port *port = &efm_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (irqflag & UARTn_IF_RXDATAV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) efm32_uart_rx_chars(efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (irqflag & UARTn_IF_RXOF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static irqreturn_t efm32_uart_txirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct efm32_uart_port *efm_port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* TXBL doesn't need to be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (irqflag & UARTn_IF_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) efm32_uart_tx_chars(efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int efm32_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = clk_enable(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) efm_debug(efm_port, "failed to enable clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) port->uartclk = clk_get_rate(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Enable pins at configured location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) efm32_uart_write32(efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) UARTn_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = request_irq(port->irq, efm32_uart_rxirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DRIVER_NAME, efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) efm_debug(efm_port, "failed to register rxirq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto err_request_irq_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* disable all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) efm32_uart_write32(efm_port, 0, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DRIVER_NAME, efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) efm_debug(efm_port, "failed to register txirq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) free_irq(port->irq, efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) err_request_irq_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk_disable(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) efm32_uart_write32(efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void efm32_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) efm32_uart_write32(efm_port, 0, UARTn_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) free_irq(port->irq, efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clk_disable(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void efm32_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct ktermios *new, struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 frame = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* no modem control lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) new->c_cflag &= ~(CRTSCTS | CMSPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) baud = uart_get_baud_rate(port, new, old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DIV_ROUND_CLOSEST(port->uartclk, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (new->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) frame |= UARTn_FRAME_DATABITS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) frame |= UARTn_FRAME_DATABITS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) frame |= UARTn_FRAME_DATABITS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) frame |= UARTn_FRAME_DATABITS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (new->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* the receiver only verifies the first stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) frame |= UARTn_FRAME_STOPBITS_TWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) frame |= UARTn_FRAME_STOPBITS_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (new->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (new->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) frame |= UARTn_FRAME_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) frame |= UARTn_FRAME_PARITY_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) frame |= UARTn_FRAME_PARITY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) efm32_uart_write32(efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (new->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) port->read_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (new->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (new->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) port->ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (new->c_iflag & IGNBRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) efm32_uart_write32(efm_port, frame, UARTn_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const char *efm32_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void efm32_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_unprepare(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clk_put(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int efm32_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) port->membase = ioremap(port->mapbase, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!efm_port->port.membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) efm_debug(efm_port, "failed to remap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) efm_port->clk = clk_get(port->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (IS_ERR(efm_port->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = PTR_ERR(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) efm_debug(efm_port, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto err_clk_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = clk_prepare(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) clk_put(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) err_clk_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void efm32_uart_config_port(struct uart_port *port, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (type & UART_CONFIG_TYPE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) !efm32_uart_request_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) port->type = PORT_EFMUART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int efm32_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct serial_struct *serinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct uart_ops efm32_uart_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .tx_empty = efm32_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .set_mctrl = efm32_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .get_mctrl = efm32_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .stop_tx = efm32_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .start_tx = efm32_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .stop_rx = efm32_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .break_ctl = efm32_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .startup = efm32_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .shutdown = efm32_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .set_termios = efm32_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .type = efm32_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .release_port = efm32_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .request_port = efm32_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .config_port = efm32_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .verify_port = efm32_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct efm32_uart_port *efm32_uart_ports[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void efm32_uart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct efm32_uart_port *efm_port = to_efm_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int timeout = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) status = efm32_uart_read32(efm_port, UARTn_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (status & UARTn_STATUS_TXBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void efm32_uart_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int timeout = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!(status & UARTn_STATUS_TXENS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) uart_console_write(&efm_port->port, s, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) efm32_uart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Wait for the transmitter to become empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (status & UARTn_STATUS_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!(status & UARTn_STATUS_TXENS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int *baud, int *parity, int *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 route, clkdiv, frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ctrl & UARTn_CTRL_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* not operating in async mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) route = efm32_uart_read32(efm_port, UARTn_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!(route & UARTn_ROUTE_TXPEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* tx pin not routed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 16 * (4 + (clkdiv >> 6)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) frame = efm32_uart_read32(efm_port, UARTn_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) switch (frame & UARTn_FRAME_PARITY__MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case UARTn_FRAME_PARITY_ODD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *parity = 'o';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case UARTn_FRAME_PARITY_EVEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *parity = 'e';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) UARTn_FRAME_DATABITS(4) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) efm_debug(efm_port, "get_opts: options=%d%c%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *baud, *parity, *bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int efm32_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct efm32_uart_port *efm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (efm32_uart_ports[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) i, co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) co->index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) efm_port = efm32_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!efm_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pr_warn("efm32-console: No port at %d\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = clk_prepare(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_warn(efm_port->port.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "console: clk_prepare failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) efm_port->port.uartclk = clk_get_rate(efm_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) efm32_uart_console_get_options(efm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &baud, &parity, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct uart_driver efm32_uart_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct console efm32_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .name = DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .write = efm32_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .setup = efm32_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .data = &efm32_uart_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define efm32_uart_console (*(struct console *)NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static struct uart_driver efm32_uart_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .dev_name = DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .nr = ARRAY_SIZE(efm32_uart_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .cons = &efm32_uart_console,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int efm32_uart_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct efm32_uart_port *efm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = of_property_read_u32(np, "energymicro,location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* fall back to wrongly namespaced property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = of_property_read_u32(np, "efm32,location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* fall back to old and (wrongly) generic property "location" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = of_property_read_u32(np, "location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (location > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(&pdev->dev, "invalid location\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) efm_debug(efm_port, "using location %u\n", location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) efm_port->pdata.location = location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) efm_debug(efm_port, "fall back to location 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) efm_port->port.line = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int efm32_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct efm32_uart_port *efm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!efm_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(&pdev->dev, "failed to allocate private data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_dbg(&pdev->dev, "failed to determine base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto err_get_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (resource_size(res) < 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_dbg(&pdev->dev, "memory resource too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto err_too_small;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_dbg(&pdev->dev, "failed to get rx irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto err_get_rxirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) efm_port->port.irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = efm_port->port.irq + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) efm_port->txirq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) efm_port->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) efm_port->port.mapbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) efm_port->port.type = PORT_EFMUART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) efm_port->port.iotype = UPIO_MEM32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) efm_port->port.fifosize = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) efm_port->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_EFM32_UART_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) efm_port->port.ops = &efm32_uart_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) efm_port->port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = efm32_uart_probe_dt(pdev, efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* not created by device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) efm_port->port.line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) efm_port->pdata = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) goto err_probe_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) line = efm_port->port.line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) efm32_uart_ports[line] = efm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) efm32_uart_ports[line] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) err_probe_dt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) err_get_rxirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) err_too_small:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) err_get_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) kfree(efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) platform_set_drvdata(pdev, efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_dbg(&pdev->dev, "\\o/\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int efm32_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) unsigned int line = efm_port->port.line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) efm32_uart_ports[line] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) kfree(efm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct of_device_id efm32_uart_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .compatible = "energymicro,efm32-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* doesn't follow the "vendor,device" scheme, don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .compatible = "efm32,uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct platform_driver efm32_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .probe = efm32_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .remove = efm32_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .of_match_table = efm32_uart_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int __init efm32_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = uart_register_driver(&efm32_uart_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = platform_driver_register(&efm32_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) uart_unregister_driver(&efm32_uart_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pr_info("EFM32 UART/USART driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) module_init(efm32_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void __exit efm32_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) platform_driver_unregister(&efm32_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uart_unregister_driver(&efm32_uart_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) module_exit(efm32_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) MODULE_DESCRIPTION("EFM32 UART/USART driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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