^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dz.h: Serial port driver for DECstations equipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * with the DZ chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Olivier A. D. Lebaillif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Email: olivier.lebaillif@ifrsys.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004, 2006 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef DZ_SERIAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DZ_SERIAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Definitions for the Control and Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DZ_TRDY 0x8000 /* Transmitter empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DZ_TLINE 0x0300 /* Transmitter Line Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DZ_RDONE 0x0080 /* Receiver data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DZ_MSE 0x0020 /* Master Scan Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DZ_CLR 0x0010 /* Master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DZ_MAINT 0x0008 /* Loop Back Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Definitions for the Receiver Buffer Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DZ_RBUF_MASK 0x00FF /* Data Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DZ_LINE_MASK 0x0300 /* Line Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DZ_DVAL 0x8000 /* Valid Data indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DZ_OERR 0x4000 /* Overrun error indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DZ_FERR 0x2000 /* Frame error indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DZ_PERR 0x1000 /* Parity error indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DZ_BREAK 0x0800 /* BREAK event software flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LINE(x) ((x & DZ_LINE_MASK) >> 8) /* Get the line number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) from the input buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Definitions for the Transmit Control Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DZ_LINE_KEYBOARD 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DZ_LINE_MOUSE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DZ_LINE_MODEM 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DZ_LINE_PRINTER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DZ_MODEM_RTS 0x0800 /* RTS for the modem line (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DZ_PRINT_RTS 0x0200 /* RTS for the prntr line (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DZ_PRINT_DTR 0x0100 /* DTR for the prntr line (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DZ_LNENB 0x000f /* Transmitter Line Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Definitions for the Modem Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DZ_MODEM_RI 0x0800 /* RI for the modem line (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DZ_MODEM_CD 0x0400 /* CD for the modem line (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DZ_MODEM_DSR 0x0200 /* DSR for the modem line (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DZ_MODEM_CTS 0x0100 /* CTS for the modem line (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DZ_PRINT_RI 0x0008 /* RI for the printer line (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DZ_PRINT_CD 0x0004 /* CD for the printer line (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DZ_PRINT_DSR 0x0002 /* DSR for the prntr line (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DZ_PRINT_CTS 0x0001 /* CTS for the prntr line (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Definitions for the Transmit Data Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DZ_BRK0 0x0100 /* Break assertion for line 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DZ_BRK1 0x0200 /* Break assertion for line 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DZ_BRK2 0x0400 /* Break assertion for line 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DZ_BRK3 0x0800 /* Break assertion for line 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Definitions for the Line Parameter Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DZ_KEYBOARD 0x0000 /* line 0 = keyboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DZ_MOUSE 0x0001 /* line 1 = mouse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DZ_MODEM 0x0002 /* line 2 = modem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DZ_PRINTER 0x0003 /* line 3 = printer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DZ_CSIZE 0x0018 /* Number of bits per byte (mask) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DZ_CS5 0x0000 /* 5 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DZ_CS6 0x0008 /* 6 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DZ_CS7 0x0010 /* 7 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DZ_CS8 0x0018 /* 8 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DZ_CSTOPB 0x0020 /* 2 stop bits instead of one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DZ_PARENB 0x0040 /* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DZ_PARODD 0x0080 /* Odd parity instead of even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DZ_CBAUD 0x0E00 /* Baud Rate (mask) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DZ_B50 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DZ_B75 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DZ_B110 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DZ_B134 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DZ_B150 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DZ_B300 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DZ_B600 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DZ_B1200 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DZ_B1800 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DZ_B2000 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DZ_B2400 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DZ_B3600 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DZ_B4800 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DZ_B7200 0x0D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DZ_B9600 0x0E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DZ_RXENAB 0x1000 /* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Addresses for the DZ registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DZ_CSR 0x00 /* Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DZ_RBUF 0x08 /* Receive Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DZ_LPR 0x08 /* Line Parameters Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DZ_TCR 0x10 /* Transmitter Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DZ_MSR 0x18 /* Modem Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DZ_TDR 0x18 /* Transmit Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DZ_NB_PORT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DZ_XMIT_SIZE 4096 /* buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DZ_WAKEUP_CHARS DZ_XMIT_SIZE/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif /* DZ_SERIAL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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