^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Derived from many drivers using generic_serial interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Serial driver for BCM63xx integrated UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hardware flow control was _not_ tested since I only have RX/TX on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * my board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/serial_bcm63xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BCM63XX_NR_UARTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct uart_port ports[BCM63XX_NR_UARTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * rx interrupt mask / stat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * - rx fifo full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - rx fifo above threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - rx fifo not empty for too long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) UART_IR_MASK(UART_IR_RXTHRESH) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) UART_IR_MASK(UART_IR_RXTIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) UART_IR_STAT(UART_IR_RXTHRESH) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) UART_IR_STAT(UART_IR_RXTIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * tx interrupt mask / stat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * - tx fifo empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * - tx fifo below threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) UART_IR_MASK(UART_IR_TXTRESH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) UART_IR_STAT(UART_IR_TXTRESH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * external input interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * mask: any edge on CTS, DCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * handy uart register accessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline unsigned int bcm_uart_readl(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return __raw_readl(port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void bcm_uart_writel(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writel(value, port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * serial core request to check if uart tx fifo is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static unsigned int bcm_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * serial core request to set RTS and DTR pin state and loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val = bcm_uart_readl(port, UART_MCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* invert of written value is reflected on the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!(mctrl & TIOCM_DTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val |= UART_MCTL_DTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!(mctrl & TIOCM_RTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val |= UART_MCTL_RTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bcm_uart_writel(port, val, UART_MCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val |= UART_CTL_LOOPBACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~UART_CTL_LOOPBACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * serial core request to return RI, CTS, DCD and DSR pin state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int val, mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = bcm_uart_readl(port, UART_EXTINP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (val & UART_EXTINP_RI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mctrl |= TIOCM_RI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (val & UART_EXTINP_CTS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (val & UART_EXTINP_DCD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mctrl |= TIOCM_CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (val & UART_EXTINP_DSR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mctrl |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * serial core request to disable tx ASAP (used for flow control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void bcm_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val &= ~(UART_CTL_TXEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val &= ~UART_TX_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bcm_uart_writel(port, val, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * serial core request to (re)enable tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void bcm_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val |= UART_TX_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bcm_uart_writel(port, val, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= UART_CTL_TXEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * serial core request to stop rx, called before port shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void bcm_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val &= ~UART_RX_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bcm_uart_writel(port, val, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * serial core request to enable modem status interrupt reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void bcm_uart_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val |= UART_IR_MASK(UART_IR_EXTIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bcm_uart_writel(port, val, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * serial core request to start/stop emitting break char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val |= UART_CTL_XMITBRK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val &= ~UART_CTL_XMITBRK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * return port type in string format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char *bcm_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * read all chars in rx fifo and send them to core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void bcm_uart_do_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct tty_port *tty_port = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int max_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* limit number of char read in interrupt, should not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * higher than fifo size anyway since we're much faster than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * serial port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) max_count = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int iestat, c, cstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* get overrun/fifo empty information from ier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) iestat = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* fifo reset is required to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val |= UART_CTL_RSTRXFIFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) c &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* do stats first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (cstat & UART_FIFO_BRKDET_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (cstat & UART_FIFO_PARERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (cstat & UART_FIFO_FRAMEERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* update flag wrt read_status_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) cstat &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (cstat & UART_FIFO_BRKDET_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (cstat & UART_FIFO_FRAMEERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (cstat & UART_FIFO_PARERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (uart_handle_sysrq_char(port, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if ((cstat & port->ignore_status_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tty_insert_flip_char(tty_port, c, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } while (--max_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tty_flip_buffer_push(tty_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * fill tx fifo with chars to send, stop when fifo is about to be full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * or when all chars have been sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void bcm_uart_do_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct circ_buf *xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int val, max_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bcm_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto txq_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val = bcm_uart_readl(port, UART_MCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) max_count = port->fifosize - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) while (max_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) c = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bcm_uart_writel(port, c, UART_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto txq_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) txq_empty:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* nothing to send, disable transmit interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val &= ~UART_TX_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bcm_uart_writel(port, val, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * process uart interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) irqstat = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (irqstat & UART_RX_INT_STAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bcm_uart_do_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (irqstat & UART_TX_INT_STAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bcm_uart_do_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int estat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) estat = bcm_uart_readl(port, UART_EXTINP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) uart_handle_cts_change(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) estat & UART_EXTINP_CTS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uart_handle_dcd_change(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) estat & UART_EXTINP_DCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * enable rx & tx operation on uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void bcm_uart_enable(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * disable rx & tx operation on uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void bcm_uart_disable(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) UART_CTL_RXEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * clear all unread data in rx fifo and unsent data in tx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void bcm_uart_flush(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* empty rx and tx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* read any pending char to make sure all irq status are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (void)bcm_uart_readl(port, UART_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * serial core request to initialize uart and start rx operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int bcm_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* mask all irq and flush port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bcm_uart_disable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bcm_uart_writel(port, 0, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) bcm_uart_flush(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* clear any pending external input interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (void)bcm_uart_readl(port, UART_EXTINP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* set rx/tx fifo thresh to fifo half size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val = bcm_uart_readl(port, UART_MCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bcm_uart_writel(port, val, UART_MCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* set rx fifo timeout to 1 char time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) val &= ~UART_CTL_RXTMOUTCNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bcm_uart_writel(port, val, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* report any edge on dcd and cts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val = UART_EXTINP_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val |= UART_EXTINP_DCD_NOSENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val |= UART_EXTINP_CTS_NOSENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bcm_uart_writel(port, val, UART_EXTINP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* register irq and enable rx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = request_irq(port->irq, bcm_uart_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_name(port->dev), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) bcm_uart_enable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * serial core request to flush & disable uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void bcm_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) bcm_uart_writel(port, 0, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bcm_uart_disable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bcm_uart_flush(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * serial core request to change current uart setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void bcm_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int ctl, baud, quot, ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Drain the hot tub fully before we power it off for the winter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* disable uart while changing speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bcm_uart_disable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bcm_uart_flush(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* update Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctl = bcm_uart_readl(port, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ctl &= ~UART_CTL_BITSPERSYM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) switch (new->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ctl &= ~UART_CTL_STOPBITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (new->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ctl |= UART_CTL_STOPBITS_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ctl |= UART_CTL_STOPBITS_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (new->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (new->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) bcm_uart_writel(port, ctl, UART_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* update Baudword register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) quot = uart_get_divisor(port, baud) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) bcm_uart_writel(port, quot, UART_BAUD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* update Interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ier = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ier &= ~UART_IR_MASK(UART_IR_EXTIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (UART_ENABLE_MS(port, new->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ier |= UART_IR_MASK(UART_IR_EXTIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) bcm_uart_writel(port, ier, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* update read/ignore mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) port->read_status_mask = UART_FIFO_VALID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (new->c_iflag & INPCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) port->read_status_mask |= UART_FIFO_PARERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (new->c_iflag & (IGNBRK | BRKINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) port->read_status_mask |= UART_FIFO_BRKDET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (new->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (new->c_iflag & IGNBRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!(new->c_cflag & CREAD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) port->ignore_status_mask |= UART_FIFO_VALID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) bcm_uart_enable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * serial core request to claim uart iomem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int bcm_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* UARTs always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * serial core request to release uart iomem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void bcm_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Nothing to release ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * serial core request to do any port required autoconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void bcm_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (bcm_uart_request_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) port->type = PORT_BCM63XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * serial core request to check that port information in serinfo are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * suitable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int bcm_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct serial_struct *serinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (port->type != PORT_BCM63XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (port->irq != serinfo->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (port->iotype != serinfo->io_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (port->mapbase != (unsigned long)serinfo->iomem_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* serial core callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct uart_ops bcm_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .tx_empty = bcm_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .get_mctrl = bcm_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .set_mctrl = bcm_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .start_tx = bcm_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .stop_tx = bcm_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .stop_rx = bcm_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .enable_ms = bcm_uart_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .break_ctl = bcm_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .startup = bcm_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .shutdown = bcm_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .set_termios = bcm_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .type = bcm_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .release_port = bcm_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .request_port = bcm_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .config_port = bcm_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .verify_port = bcm_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void wait_for_xmitr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int tmout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Wait up to 10ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) while (--tmout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val = bcm_uart_readl(port, UART_IR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (val & UART_IR_STAT(UART_IR_TXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Wait up to 1s for flow control if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (port->flags & UPF_CONS_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) tmout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) while (--tmout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val = bcm_uart_readl(port, UART_EXTINP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (val & UART_EXTINP_CTS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * output given char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void bcm_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) bcm_uart_writel(port, ch, UART_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * console core request to output given string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void bcm_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) port = &ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (port->sysrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* bcm_uart_interrupt() already took the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } else if (oops_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) locked = spin_trylock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* call helper to deal with \r\n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uart_console_write(port, s, count, bcm_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* and wait for char to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * console core request to setup given console, find matching uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * port and setup it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int bcm_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) port = &ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct uart_driver bcm_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct console bcm63xx_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .write = bcm_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .setup = bcm_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .data = &bcm_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int __init bcm63xx_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) register_console(&bcm63xx_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) console_initcall(bcm63xx_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void bcm_early_write(struct console *con, const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uart_console_write(&dev->port, s, n, bcm_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) wait_for_xmitr(&dev->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int __init bcm_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) device->con->write = bcm_early_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define BCM63XX_CONSOLE (&bcm63xx_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define BCM63XX_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static struct uart_driver bcm_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .driver_name = "bcm63xx_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .dev_name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .major = TTY_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .minor = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .nr = BCM63XX_NR_UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .cons = BCM63XX_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * platform driver probe/remove callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int bcm_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct resource *res_mem, *res_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (pdev->id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) port = &ports[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) memset(port, 0, sizeof(*port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!res_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) port->mapbase = res_mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (IS_ERR(port->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return PTR_ERR(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!res_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) clk = clk_get(&pdev->dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (IS_ERR(clk) && pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clk = of_clk_get(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) port->irq = res_irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) port->ops = &bcm_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) port->fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) port->uartclk = clk_get_rate(clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) port->line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = uart_add_one_port(&bcm_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ports[pdev->id].membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) platform_set_drvdata(pdev, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int bcm_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) uart_remove_one_port(&bcm_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* mark port as free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ports[pdev->id].membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const struct of_device_id bcm63xx_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) { .compatible = "brcm,bcm6345-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * platform driver stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct platform_driver bcm_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .probe = bcm_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .remove = bcm_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .name = "bcm63xx_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .of_match_table = bcm63xx_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int __init bcm_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = uart_register_driver(&bcm_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = platform_driver_register(&bcm_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) uart_unregister_driver(&bcm_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static void __exit bcm_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) platform_driver_unregister(&bcm_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uart_unregister_driver(&bcm_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) module_init(bcm_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) module_exit(bcm_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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