^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ARC On-Chip(fpga) UART Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * vineetg: July 10th 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * -Decoupled the driver from arch/arc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * +Using platform_get_resource() for irq/membase (thx to bfin_uart.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Vineetg: Aug 21st 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * -Is uart_tx_stopped() not done in tty write path as it has already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * taken care of, in serial core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Vineetg: Aug 18th 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * -New Serial Core based ARC UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * -Derived largely from blackfin driver albiet with some major tweaks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * -check if sysreq works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ARC UART Hardware Specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ARC_UART_TX_FIFO_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * UART Register set (this is not a Standards Compliant IP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Also each reg is Word aligned, but only 8 bits wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R_ID0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R_ID1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R_ID2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R_ID3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R_DATA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R_STS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R_BAUDL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R_BAUDH 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Bits for UART Status Reg (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RXIENB 0x04 /* Receive Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TXIENB 0x40 /* Transmit Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RXEMPTY 0x20 /* Receive FIFO Empty: No char receivede */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TXEMPTY 0x80 /* Transmit FIFO Empty, thus char can be written into */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RXFULL 0x08 /* Receive FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RXFULL1 0x10 /* Receive FIFO has space for 1 char (tot space=4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RXFERR 0x01 /* Frame Error: Stop Bit not detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RXOERR 0x02 /* OverFlow Err: Char recv but RXFULL still set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Uart bit fiddling helpers: lowest level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RBASE(port, reg) (port->membase + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UART_REG_SET(u, r, v) writeb((v), RBASE(u, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UART_REG_GET(u, r) readb(RBASE(u, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UART_REG_OR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) | (v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UART_REG_CLR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) & ~(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Uart bit fiddling helpers: API level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UART_GET_STATUS(uart) UART_REG_GET(uart, R_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UART_RX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UART_RX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ARC_SERIAL_DEV_NAME "ttyARC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct arc_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define to_arc_port(uport) container_of(uport, struct arc_uart_port, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct arc_uart_port arc_uart_ports[CONFIG_SERIAL_ARC_NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #ifdef CONFIG_SERIAL_ARC_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct console arc_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRIVER_NAME "arc-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct uart_driver arc_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .dev_name = ARC_SERIAL_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .major = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .nr = CONFIG_SERIAL_ARC_NR_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef CONFIG_SERIAL_ARC_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .cons = &arc_console,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void arc_serial_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) UART_RX_IRQ_DISABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void arc_serial_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) while (!(UART_GET_STATUS(port) & TXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) UART_TX_IRQ_DISABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Return TIOCSER_TEMT when transmitter is not busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static unsigned int arc_serial_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) stat = UART_GET_STATUS(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (stat & TXEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Driver internal routine, used by both tty(serial core) as well as tx-isr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * -Called under spinlock in either cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * -also tty->stopped has already been checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * = by uart_start( ) before calling us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * = tx_ist checks that too before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void arc_serial_tx_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned char ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (unlikely(port->x_char)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) UART_SET_DATA(port, port->x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } else if (!uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ch = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) while (!(UART_GET_STATUS(port) & TXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) UART_SET_DATA(port, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * If num chars in xmit buffer are too few, ask tty layer for more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * By Hard ISR to schedule processing in software interrupt part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (sent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) UART_TX_IRQ_ENABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * port is locked and interrupts are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * uart_start( ) calls us under the port spinlock irqsave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void arc_serial_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) arc_serial_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void arc_serial_rx_chars(struct uart_port *port, unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int ch, flg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * UART has 4 deep RX-FIFO. Driver's recongnition of this fact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * is very subtle. Here's how ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Upon getting a RX-Intr, such that RX-EMPTY=0, meaning data available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * driver reads the DATA Reg and keeps doing that in a loop, until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * RX-EMPTY=1. Multiple chars being avail, with a single Interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * before RX-EMPTY=0, implies some sort of buffering going on in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * controller, which is indeed the Rx-FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * This could be an Rx Intr for err (no data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * so check err and clear that Intr first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (unlikely(status & (RXOERR | RXFERR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (status & RXOERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) flg = TTY_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) UART_CLR_STATUS(port, RXOERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (status & RXFERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) flg = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) UART_CLR_STATUS(port, RXFERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) flg = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (status & RXEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ch = UART_GET_DATA(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!(uart_handle_sysrq_char(port, ch)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) uart_insert_char(port, status, RXOERR, ch, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } while (!((status = UART_GET_STATUS(port)) & RXEMPTY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * A note on the Interrupt handling state machine of this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * kernel printk writes funnel thru the console driver framework and in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * to keep things simple as well as efficient, it writes to UART in polled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * mode, in one shot, and exits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * OTOH, Userland output (via tty layer), uses interrupt based writes as there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * can be undeterministic delay between char writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Thus Rx-interrupts are always enabled, while tx-interrupts are by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * When tty has some data to send out, serial core calls driver's start_tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * -checks-if-tty-buffer-has-char-to-send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * -writes-data-to-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * -enable-tx-intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Once data bits are pushed out, controller raises the Tx-room-avail-Interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * The first thing Tx ISR does is disable further Tx interrupts (as this could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * be the last char to send, before settling down into the quiet polled mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * It then calls the exact routine used by tty layer write to send out any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * more char in tty buffer. In case of sending, it re-enables Tx-intr. In case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * of no data, it remains disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This is how the transmit state machine is dynamically switched on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static irqreturn_t arc_serial_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) status = UART_GET_STATUS(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Single IRQ for both Rx (data available) Tx (room available) Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * notifications from the UART Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * To demultiplex between the two, we check the relevant bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (status & RXIENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* already in ISR, no need of xx_irqsave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) arc_serial_rx_chars(port, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if ((status & TXIENB) && (status & TXEMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Unconditionally disable further Tx-Interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * will be enabled by tx_chars() if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) UART_TX_IRQ_DISABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) arc_serial_tx_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static unsigned int arc_serial_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Pretend we have a Modem status reg and following bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * always set, to satify the serial core state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * (DSR) Data Set Ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * (CTS) Clear To Send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * (CAR) Carrier Detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void arc_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* MCR not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void arc_serial_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* ARC UART doesn't support sending Break signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int arc_serial_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Before we hook up the ISR, Disable all UART Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) UART_ALL_IRQ_DISABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (request_irq(port->irq, arc_serial_isr, 0, "arc uart rx-tx", port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_warn(port->dev, "Unable to attach ARC UART intr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) UART_RX_IRQ_ENABLE(port); /* Only Rx IRQ enabled to begin with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* This is not really needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void arc_serial_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) arc_serial_set_termios(struct uart_port *port, struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct arc_uart_port *uart = to_arc_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int baud, uartl, uarth, hw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Use the generic handler so that any specially encoded baud rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * such as SPD_xx flags or "%B0" can be handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Max Baud I suppose will not be more than current 115K * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Formula for ARC UART is: hw-val = ((CLK/(BAUD*4)) -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * spread over two 8-bit registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) baud = uart_get_baud_rate(port, new, old, 0, 460800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hw_val = port->uartclk / (uart->baud * 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uartl = hw_val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uarth = (hw_val >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) UART_ALL_IRQ_DISABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) UART_SET_BAUDL(port, uartl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) UART_SET_BAUDH(port, uarth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) UART_RX_IRQ_ENABLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * UART doesn't support Parity/Hardware Flow Control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Only supports 8N1 character size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) new->c_cflag &= ~(CMSPAR|CRTSCTS|CSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) new->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tty_termios_copy_hw(new, old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Don't rewrite B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (tty_termios_baud_rate(new))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tty_termios_encode_baud_rate(new, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const char *arc_serial_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return port->type == PORT_ARC ? DRIVER_NAME : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void arc_serial_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int arc_serial_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Verify the new serial_struct (for TIOCSSERIAL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) arc_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (port->type != PORT_UNKNOWN && ser->type != PORT_ARC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Configure/autoconfigure the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void arc_serial_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) port->type = PORT_ARC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void arc_serial_poll_putchar(struct uart_port *port, unsigned char chr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) while (!(UART_GET_STATUS(port) & TXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) UART_SET_DATA(port, chr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int arc_serial_poll_getchar(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned char chr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) while (!(UART_GET_STATUS(port) & RXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) chr = UART_GET_DATA(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return chr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct uart_ops arc_serial_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .tx_empty = arc_serial_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .set_mctrl = arc_serial_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .get_mctrl = arc_serial_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .stop_tx = arc_serial_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .start_tx = arc_serial_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .stop_rx = arc_serial_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .break_ctl = arc_serial_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .startup = arc_serial_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .shutdown = arc_serial_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .set_termios = arc_serial_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .type = arc_serial_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .release_port = arc_serial_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .request_port = arc_serial_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .config_port = arc_serial_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .verify_port = arc_serial_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .poll_put_char = arc_serial_poll_putchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .poll_get_char = arc_serial_poll_getchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #ifdef CONFIG_SERIAL_ARC_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int arc_serial_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (co->index < 0 || co->index >= CONFIG_SERIAL_ARC_NR_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * The uart port backing the console (e.g. ttyARC1) might not have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * init yet. If so, defer the console setup to after the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) port = &arc_uart_ports[co->index].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Serial core will call port->ops->set_termios( )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * which will set the baud reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void arc_serial_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) while (!(UART_GET_STATUS(port) & TXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) UART_SET_DATA(port, (unsigned char)ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Interrupts are disabled on entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void arc_serial_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct uart_port *port = &arc_uart_ports[co->index].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uart_console_write(port, s, count, arc_serial_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct console arc_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = ARC_SERIAL_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .write = arc_serial_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .setup = arc_serial_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .data = &arc_uart_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void arc_early_serial_write(struct console *con, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uart_console_write(&dev->port, s, n, arc_serial_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int __init arc_early_console_setup(struct earlycon_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct uart_port *port = &dev->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int l, h, hw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!dev->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hw_val = port->uartclk / (dev->baud * 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) l = hw_val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) h = (hw_val >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) UART_SET_BAUDL(port, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) UART_SET_BAUDH(port, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev->con->write = arc_early_serial_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) OF_EARLYCON_DECLARE(arc_uart, "snps,arc-uart", arc_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #endif /* CONFIG_SERIAL_ARC_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int arc_serial_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct arc_uart_port *uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* no device tree device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_id = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (dev_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (dev_id >= ARRAY_SIZE(arc_uart_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(&pdev->dev, "serial%d out of range\n", dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uart = &arc_uart_ports[dev_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) port = &uart->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (of_property_read_u32(np, "clock-frequency", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_err(&pdev->dev, "clock-frequency property NOTset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) port->uartclk = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (of_property_read_u32(np, "current-speed", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_err(&pdev->dev, "current-speed property NOT set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) uart->baud = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) port->membase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* No point of dev_err since UART itself is hosed here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) port->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) port->line = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) port->ops = &arc_serial_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ARC_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) port->fifosize = ARC_UART_TX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * uart_insert_char( ) uses it in decideding whether to ignore a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * char or not. Explicitly setting it here, removes the subtelty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return uart_add_one_port(&arc_uart_driver, &arc_uart_ports[dev_id].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int arc_serial_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* This will never be called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const struct of_device_id arc_uart_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { .compatible = "snps,arc-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MODULE_DEVICE_TABLE(of, arc_uart_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static struct platform_driver arc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .probe = arc_serial_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .remove = arc_serial_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .of_match_table = arc_uart_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int __init arc_serial_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = uart_register_driver(&arc_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = platform_driver_register(&arc_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uart_unregister_driver(&arc_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static void __exit arc_serial_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) platform_driver_unregister(&arc_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uart_unregister_driver(&arc_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) module_init(arc_serial_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) module_exit(arc_serial_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MODULE_AUTHOR("Vineet Gupta");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MODULE_DESCRIPTION("ARC(Synopsys) On-Chip(fpga) serial driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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