^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros AR933X SoC built-in UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach-ath79/ar933x_uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "serial_mctrl_gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_NAME "ar933x-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AR933X_UART_MAX_SCALE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AR933X_UART_MAX_STEP 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AR933X_UART_MIN_BAUD 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AR933X_UART_MAX_BAUD 3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AR933X_DUMMY_STATUS_RD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct uart_driver ar933x_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct ar933x_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int ier; /* shadow Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int min_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int max_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mctrl_gpios *gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_desc *rts_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return readl(up->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void ar933x_uart_write(struct ar933x_uart_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int offset, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(value, up->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) t = ar933x_uart_read(up, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) t &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) t |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ar933x_uart_write(up, offset, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ar933x_uart_rmw(up, offset, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ar933x_uart_rmw(up, offset, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) up->ier |= AR933X_UART_INT_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) up->ier &= ~AR933X_UART_INT_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void ar933x_uart_start_rx_interrupt(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) up->ier |= AR933X_UART_INT_RX_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void ar933x_uart_stop_rx_interrupt(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) up->ier &= ~AR933X_UART_INT_RX_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rdata |= AR933X_UART_DATA_TX_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mctrl_gpio_get(up->gpios, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mctrl_gpio_set(up->gpios, mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void ar933x_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ar933x_uart_start_tx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void ar933x_uart_wait_tx_complete(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int timeout = 60000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Wait up to 60ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) status = ar933x_uart_read(up, AR933X_UART_CS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (--timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } while (status & AR933X_UART_CS_TX_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(up->port.dev, "waiting for TX timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void ar933x_uart_rx_flush(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* clear RX_VALID interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* remove characters from the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ar933x_uart_write(up, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } while (status & AR933X_UART_DATA_RX_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void ar933x_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ar933x_uart_stop_tx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void ar933x_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ar933x_uart_stop_rx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AR933X_UART_CS_TX_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) AR933X_UART_CS_TX_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static unsigned long ar933x_uart_get_baud(unsigned int clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) div = (2 << 16) * (scale + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) t = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) t *= step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) t += (div / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) do_div(t, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void ar933x_uart_get_scale_step(unsigned int clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int *scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int *step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int tscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) long min_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *scale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) min_diff = baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u64 tstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tstep = baud * (tscale + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tstep *= (2 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) do_div(tstep, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (tstep > AR933X_UART_MAX_STEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (diff < min_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) min_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *scale = tscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *step = tstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void ar933x_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int baud, scale, step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Only CS8 is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) new->c_cflag &= ~CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) new->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Only one stop bit is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) new->c_cflag &= ~CSTOPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) cs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (new->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!(new->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cs |= AR933X_UART_CS_PARITY_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cs |= AR933X_UART_CS_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cs |= AR933X_UART_CS_PARITY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Mark/space parity is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) new->c_cflag &= ~CMSPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) baud = uart_get_baud_rate(port, new, old, up->min_baud, up->max_baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ar933x_uart_get_scale_step(port->uartclk, baud, &scale, &step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Ok, we're now changing the port state. Do it with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* disable the UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Update the per-port timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) up->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* ignore all characters if CREAD is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if ((new->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ar933x_uart_write(up, AR933X_UART_CLOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) scale << AR933X_UART_CLOCK_SCALE_S | step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* setup configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* enable host interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AR933X_UART_CS_HOST_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* enable RX and TX ready overide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* reenable the UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ar933x_uart_rmw(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (tty_termios_baud_rate(new))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tty_termios_encode_baud_rate(new, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void ar933x_uart_rx_chars(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct tty_port *port = &up->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int max_count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned char ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if ((rdata & AR933X_UART_DATA_RX_CSR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* remove the character from the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ar933x_uart_write(up, AR933X_UART_DATA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) AR933X_UART_DATA_RX_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) up->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ch = rdata & AR933X_UART_DATA_TX_RX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (uart_handle_sysrq_char(&up->port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tty_insert_flip_char(port, ch, TTY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } while (max_count-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct circ_buf *xmit = &up->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct serial_rs485 *rs485conf = &up->port.rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bool half_duplex_send = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (uart_tx_stopped(&up->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if ((rs485conf->flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (up->port.x_char || !uart_circ_empty(xmit))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ar933x_uart_stop_rx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_ON_SEND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) half_duplex_send = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) count = up->port.fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if ((rdata & AR933X_UART_DATA_TX_CSR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (up->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ar933x_uart_putc(up, up->port.x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) up->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ar933x_uart_putc(up, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uart_write_wakeup(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ar933x_uart_start_tx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else if (half_duplex_send) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ar933x_uart_wait_tx_complete(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ar933x_uart_rx_flush(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ar933x_uart_start_rx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_AFTER_SEND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct ar933x_uart_port *up = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) status = ar933x_uart_read(up, AR933X_UART_CS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if ((status & AR933X_UART_CS_HOST_INT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) status = ar933x_uart_read(up, AR933X_UART_INT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (status & AR933X_UART_INT_RX_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ar933x_uart_write(up, AR933X_UART_INT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) AR933X_UART_INT_RX_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ar933x_uart_rx_chars(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (status & AR933X_UART_INT_TX_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ar933x_uart_write(up, AR933X_UART_INT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) AR933X_UART_INT_TX_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ar933x_uart_stop_tx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ar933x_uart_tx_chars(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int ar933x_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = request_irq(up->port.irq, ar933x_uart_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) up->port.irqflags, dev_name(up->port.dev), up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Enable HOST interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) AR933X_UART_CS_HOST_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* enable RX and TX ready overide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Enable RX interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ar933x_uart_start_rx_interrupt(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void ar933x_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) up->ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Disable break condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) AR933X_UART_CS_TX_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) free_irq(up->port.irq, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const char *ar933x_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void ar933x_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Nothing to release ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int ar933x_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* UARTs always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void ar933x_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) port->type = PORT_AR933X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int ar933x_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ser->type != PORT_UNKNOWN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ser->type != PORT_AR933X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ser->irq < 0 || ser->irq >= NR_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ser->baud_base < up->min_baud ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ser->baud_base > up->max_baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct uart_ops ar933x_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .tx_empty = ar933x_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .set_mctrl = ar933x_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .get_mctrl = ar933x_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .stop_tx = ar933x_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .start_tx = ar933x_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .stop_rx = ar933x_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .break_ctl = ar933x_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .startup = ar933x_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .shutdown = ar933x_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .set_termios = ar933x_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .type = ar933x_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .release_port = ar933x_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .request_port = ar933x_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .config_port = ar933x_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .verify_port = ar933x_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int ar933x_config_rs485(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct serial_rs485 *rs485conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if ((rs485conf->flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) !up->rts_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(port->dev, "RS485 needs rts-gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) port->rs485 = *rs485conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_SERIAL_AR933X_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct ar933x_uart_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int timeout = 60000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Wait up to 60ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (--timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } while ((status & AR933X_UART_DATA_TX_CSR) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct ar933x_uart_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) container_of(port, struct ar933x_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ar933x_uart_wait_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ar933x_uart_putc(up, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void ar933x_uart_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct ar933x_uart_port *up = ar933x_console_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned int int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (up->port.sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) locked = spin_trylock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * First save the IER then disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * and restore the IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ar933x_uart_wait_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int ar933x_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct ar933x_uart_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) up = ar933x_console_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return uart_set_options(&up->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static struct console ar933x_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "ttyATH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .write = ar933x_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .setup = ar933x_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .data = &ar933x_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #endif /* CONFIG_SERIAL_AR933X_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static struct uart_driver ar933x_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .dev_name = "ttyATH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .nr = CONFIG_SERIAL_AR933X_NR_UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .cons = NULL, /* filled in runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int ar933x_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct ar933x_uart_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct resource *irq_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (IS_ENABLED(CONFIG_OF) && np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) id = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(&pdev->dev, "unable to get alias id, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (id == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (id >= CONFIG_SERIAL_AR933X_NR_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!irq_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_err(&pdev->dev, "no IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) up = devm_kzalloc(&pdev->dev, sizeof(struct ar933x_uart_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) up->clk = devm_clk_get(&pdev->dev, "uart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (IS_ERR(up->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_err(&pdev->dev, "unable to get UART clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return PTR_ERR(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) port = &up->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) port->membase = devm_ioremap_resource(&pdev->dev, mem_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (IS_ERR(port->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return PTR_ERR(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = clk_prepare_enable(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) port->uartclk = clk_get_rate(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!port->uartclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) port->mapbase = mem_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) port->line = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) port->irq = irq_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) port->type = PORT_AR933X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) port->iotype = UPIO_MEM32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) port->regshift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) port->fifosize = AR933X_UART_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) port->ops = &ar933x_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) port->rs485_config = ar933x_config_rs485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) baud = ar933x_uart_get_baud(port->uartclk, AR933X_UART_MAX_SCALE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) up->min_baud = max_t(unsigned int, baud, AR933X_UART_MIN_BAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = uart_get_rs485_mode(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) up->gpios = mctrl_gpio_init(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (IS_ERR(up->gpios) && PTR_ERR(up->gpios) != -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = PTR_ERR(up->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) up->rts_gpiod = mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if ((port->rs485.flags & SER_RS485_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) !up->rts_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dev_err(&pdev->dev, "lacking rts-gpio, disabling RS485\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) port->rs485.flags &= ~SER_RS485_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #ifdef CONFIG_SERIAL_AR933X_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ar933x_console_ports[up->port.line] = up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) platform_set_drvdata(pdev, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) clk_disable_unprepare(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int ar933x_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct ar933x_uart_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) up = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) uart_remove_one_port(&ar933x_uart_driver, &up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) clk_disable_unprepare(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct of_device_id ar933x_uart_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { .compatible = "qca,ar9330-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) MODULE_DEVICE_TABLE(of, ar933x_uart_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static struct platform_driver ar933x_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .probe = ar933x_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .remove = ar933x_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .of_match_table = of_match_ptr(ar933x_uart_of_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int __init ar933x_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #ifdef CONFIG_SERIAL_AR933X_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ar933x_uart_driver.cons = &ar933x_uart_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = uart_register_driver(&ar933x_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = platform_driver_register(&ar933x_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) goto err_unregister_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) err_unregister_uart_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) uart_unregister_driver(&ar933x_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void __exit ar933x_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) platform_driver_unregister(&ar933x_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uart_unregister_driver(&ar933x_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) module_init(ar933x_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) module_exit(ar933x_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MODULE_DESCRIPTION("Atheros AR933X UART driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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