Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __GRLIB_APBUART_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __GRLIB_APBUART_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define UART_NR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) static int grlib_apbuart_port_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct grlib_apbuart_regs_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	u32 scaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct amba_prom_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	unsigned int phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	unsigned int reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *  The following defines the bits in the APBUART Status Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UART_STATUS_DR   0x00000001	/* Data Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UART_STATUS_TSE  0x00000002	/* TX Send Register Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UART_STATUS_THE  0x00000004	/* TX Hold Register Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UART_STATUS_BR   0x00000008	/* Break Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UART_STATUS_OE   0x00000010	/* RX Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UART_STATUS_PE   0x00000020	/* RX Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UART_STATUS_FE   0x00000040	/* RX Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UART_STATUS_ERR  0x00000078	/* Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  *  The following defines the bits in the APBUART Ctrl Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UART_CTRL_RE     0x00000001	/* Receiver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UART_CTRL_TE     0x00000002	/* Transmitter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UART_CTRL_RI     0x00000004	/* Receiver interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UART_CTRL_TI     0x00000008	/* Transmitter irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UART_CTRL_PS     0x00000010	/* Parity select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UART_CTRL_PE     0x00000020	/* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UART_CTRL_FL     0x00000040	/* Flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UART_CTRL_LB     0x00000080	/* Loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define APBBASE(port) ((struct grlib_apbuart_regs_map *)((port)->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define APBBASE_DATA_P(port)	(&(APBBASE(port)->data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define APBBASE_STATUS_P(port)	(&(APBBASE(port)->status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define APBBASE_CTRL_P(port)	(&(APBBASE(port)->ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define APBBASE_SCALAR_P(port)	(&(APBBASE(port)->scaler))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UART_GET_CHAR(port)	(__raw_readl(APBBASE_DATA_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UART_PUT_CHAR(port, v)	(__raw_writel(v, APBBASE_DATA_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UART_GET_STATUS(port)	(__raw_readl(APBBASE_STATUS_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UART_PUT_STATUS(port, v)(__raw_writel(v, APBBASE_STATUS_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UART_GET_CTRL(port)	(__raw_readl(APBBASE_CTRL_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UART_PUT_CTRL(port, v)	(__raw_writel(v, APBBASE_CTRL_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UART_GET_SCAL(port)	(__raw_readl(APBBASE_SCALAR_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UART_PUT_SCAL(port, v)	(__raw_writel(v, APBBASE_SCALAR_P(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UART_RX_DATA(s)		(((s) & UART_STATUS_DR) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UART_TX_READY(s)	(((s) & UART_STATUS_THE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* __GRLIB_APBUART_H__ */