^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * altera_uart.c -- Altera UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on mcf.c -- Freescale ColdFire UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/altera_uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRV_NAME "altera_uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SERIAL_ALTERA_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SERIAL_ALTERA_MINOR 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Altera UART register definitions according to the Nios UART datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * http://www.altera.com/literature/ds/ds_nios_uart.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ALTERA_UART_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ALTERA_UART_RXDATA_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ALTERA_UART_TXDATA_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ALTERA_UART_STATUS_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ALTERA_UART_CONTROL_REG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ALTERA_UART_DIVISOR_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ALTERA_UART_EOP_REG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ALTERA_UART_STATUS_PE_MSK 0x0001 /* parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ALTERA_UART_STATUS_FE_MSK 0x0002 /* framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ALTERA_UART_STATUS_BRK_MSK 0x0004 /* break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ALTERA_UART_STATUS_ROE_MSK 0x0008 /* RX overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ALTERA_UART_STATUS_TOE_MSK 0x0010 /* TX overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ALTERA_UART_STATUS_TMT_MSK 0x0020 /* TX shift register state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ALTERA_UART_STATUS_TRDY_MSK 0x0040 /* TX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ALTERA_UART_STATUS_RRDY_MSK 0x0080 /* RX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ALTERA_UART_STATUS_E_MSK 0x0100 /* exception condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ALTERA_UART_STATUS_DCTS_MSK 0x0400 /* CTS logic-level change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ALTERA_UART_STATUS_CTS_MSK 0x0800 /* CTS logic state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ALTERA_UART_STATUS_EOP_MSK 0x1000 /* EOP written/read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Enable interrupt on... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ALTERA_UART_CONTROL_PE_MSK 0x0001 /* ...parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ALTERA_UART_CONTROL_FE_MSK 0x0002 /* ...framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ALTERA_UART_CONTROL_BRK_MSK 0x0004 /* ...break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ALTERA_UART_CONTROL_ROE_MSK 0x0008 /* ...RX overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ALTERA_UART_CONTROL_TOE_MSK 0x0010 /* ...TX overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ALTERA_UART_CONTROL_TMT_MSK 0x0020 /* ...TX shift register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ALTERA_UART_CONTROL_TRDY_MSK 0x0040 /* ...TX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ALTERA_UART_CONTROL_RRDY_MSK 0x0080 /* ...RX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ALTERA_UART_CONTROL_E_MSK 0x0100 /* ...exception*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ALTERA_UART_CONTROL_TRBK_MSK 0x0200 /* TX break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ALTERA_UART_CONTROL_DCTS_MSK 0x0400 /* Interrupt on CTS change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ALTERA_UART_CONTROL_RTS_MSK 0x0800 /* RTS signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ALTERA_UART_CONTROL_EOP_MSK 0x1000 /* Interrupt on EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Local per-uart structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct altera_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct timer_list tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int sigs; /* Local copy of line sigs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned short imr; /* Local IMR mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static u32 altera_uart_readl(struct uart_port *port, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return readl(port->membase + (reg << port->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void altera_uart_writel(struct uart_port *port, u32 dat, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(dat, port->membase + (reg << port->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static unsigned int altera_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ALTERA_UART_STATUS_TMT_MSK) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static unsigned int altera_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int sigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) sigs = (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ALTERA_UART_STATUS_CTS_MSK) ? TIOCM_CTS : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sigs |= (pp->sigs & TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return sigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void altera_uart_update_ctrl_reg(struct altera_uart *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned short imr = pp->imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * If the device doesn't have an irq, ensure that the irq bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * masked out to keep the irq line inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!pp->port.irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) imr &= ALTERA_UART_CONTROL_TRBK_MSK | ALTERA_UART_CONTROL_RTS_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) altera_uart_writel(&pp->port, imr, ALTERA_UART_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void altera_uart_set_mctrl(struct uart_port *port, unsigned int sigs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pp->sigs = sigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (sigs & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pp->imr |= ALTERA_UART_CONTROL_RTS_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pp->imr &= ~ALTERA_UART_CONTROL_RTS_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void altera_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pp->imr |= ALTERA_UART_CONTROL_TRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void altera_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void altera_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pp->imr &= ~ALTERA_UART_CONTROL_RRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void altera_uart_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pp->imr |= ALTERA_UART_CONTROL_TRBK_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pp->imr &= ~ALTERA_UART_CONTROL_TRBK_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void altera_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int baud, baudclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) baudclk = port->uartclk / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tty_termios_copy_hw(termios, old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * FIXME: port->read_status_mask and port->ignore_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * need to be initialized based on termios settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void altera_uart_rx_chars(struct altera_uart *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct uart_port *port = &pp->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned char ch, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) while ((status = altera_uart_readl(port, ALTERA_UART_STATUS_REG)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ALTERA_UART_STATUS_RRDY_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ch = altera_uart_readl(port, ALTERA_UART_RXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (status & ALTERA_UART_STATUS_E_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) altera_uart_writel(port, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ALTERA_UART_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (status & ALTERA_UART_STATUS_BRK_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else if (status & ALTERA_UART_STATUS_PE_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } else if (status & ALTERA_UART_STATUS_ROE_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } else if (status & ALTERA_UART_STATUS_FE_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) status &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (status & ALTERA_UART_STATUS_BRK_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else if (status & ALTERA_UART_STATUS_PE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) else if (status & ALTERA_UART_STATUS_FE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) uart_insert_char(port, status, ALTERA_UART_STATUS_ROE_MSK, ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void altera_uart_tx_chars(struct altera_uart *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct uart_port *port = &pp->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Send special char - probably flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) altera_uart_writel(port, port->x_char, ALTERA_UART_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) while (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ALTERA_UART_STATUS_TRDY_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (xmit->head == xmit->tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) altera_uart_writel(port, xmit->buf[xmit->tail],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ALTERA_UART_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (xmit->head == xmit->tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static irqreturn_t altera_uart_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct uart_port *port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) isr = altera_uart_readl(port, ALTERA_UART_STATUS_REG) & pp->imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (isr & ALTERA_UART_STATUS_RRDY_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) altera_uart_rx_chars(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (isr & ALTERA_UART_STATUS_TRDY_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) altera_uart_tx_chars(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return IRQ_RETVAL(isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void altera_uart_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct altera_uart *pp = from_timer(pp, t, tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct uart_port *port = &pp->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) altera_uart_interrupt(0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mod_timer(&pp->tmr, jiffies + uart_poll_timeout(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void altera_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) port->type = PORT_ALTERA_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Clear mask, so no surprise interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) altera_uart_writel(port, 0, ALTERA_UART_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Clear status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) altera_uart_writel(port, 0, ALTERA_UART_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int altera_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!port->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) timer_setup(&pp->tmr, altera_uart_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mod_timer(&pp->tmr, jiffies + uart_poll_timeout(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = request_irq(port->irq, altera_uart_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DRV_NAME, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pr_err(DRV_NAME ": unable to attach Altera UART %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "interrupt vector=%d\n", port->line, port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Enable RX interrupts now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pp->imr = ALTERA_UART_CONTROL_RRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void altera_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct altera_uart *pp = container_of(port, struct altera_uart, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Disable all interrupts now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pp->imr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) altera_uart_update_ctrl_reg(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (port->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) del_timer_sync(&pp->tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char *altera_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return (port->type == PORT_ALTERA_UART) ? "Altera UART" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int altera_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* UARTs always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void altera_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Nothing to release... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int altera_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ALTERA_UART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int altera_uart_poll_get_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ALTERA_UART_STATUS_RRDY_MSK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return altera_uart_readl(port, ALTERA_UART_RXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void altera_uart_poll_put_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ALTERA_UART_STATUS_TRDY_MSK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) altera_uart_writel(port, c, ALTERA_UART_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Define the basic serial functions we support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct uart_ops altera_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .tx_empty = altera_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .get_mctrl = altera_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .set_mctrl = altera_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .start_tx = altera_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .stop_tx = altera_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .stop_rx = altera_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .break_ctl = altera_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .startup = altera_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .shutdown = altera_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .set_termios = altera_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .type = altera_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .request_port = altera_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .release_port = altera_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .config_port = altera_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .verify_port = altera_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .poll_get_char = altera_uart_poll_get_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .poll_put_char = altera_uart_poll_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct altera_uart altera_uart_ports[CONFIG_SERIAL_ALTERA_UART_MAXPORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #if defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void altera_uart_console_putc(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ALTERA_UART_STATUS_TRDY_MSK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) altera_uart_writel(port, c, ALTERA_UART_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void altera_uart_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct uart_port *port = &(altera_uart_ports + co->index)->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uart_console_write(port, s, count, altera_uart_console_putc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int __init altera_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int baud = CONFIG_SERIAL_ALTERA_UART_BAUDRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (co->index < 0 || co->index >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) port = &altera_uart_ports[co->index].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct uart_driver altera_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct console altera_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .name = "ttyAL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .write = altera_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .setup = altera_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .data = &altera_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int __init altera_uart_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) register_console(&altera_uart_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) console_initcall(altera_uart_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define ALTERA_UART_CONSOLE (&altera_uart_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void altera_uart_earlycon_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct earlycon_device *dev = co->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uart_console_write(&dev->port, s, count, altera_uart_console_putc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int __init altera_uart_earlycon_setup(struct earlycon_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) const char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct uart_port *port = &dev->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Enable RX interrupts now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) altera_uart_writel(port, ALTERA_UART_CONTROL_RRDY_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ALTERA_UART_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (dev->baud) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int baudclk = port->uartclk / dev->baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev->con->write = altera_uart_earlycon_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) OF_EARLYCON_DECLARE(uart, "altr,uart-1.0", altera_uart_earlycon_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define ALTERA_UART_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif /* CONFIG_SERIAL_ALTERA_UART_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Define the altera_uart UART driver structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static struct uart_driver altera_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .driver_name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .dev_name = "ttyAL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .major = SERIAL_ALTERA_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .minor = SERIAL_ALTERA_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .nr = CONFIG_SERIAL_ALTERA_UART_MAXPORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cons = ALTERA_UART_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int altera_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct altera_uart_platform_uart *platp = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct resource *res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct resource *res_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int i = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* if id is -1 scan for a free id and use that one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (i == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (altera_uart_ports[i].port.mapbase == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (i < 0 || i >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) port = &altera_uart_ports[i].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (res_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) port->mapbase = res_mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else if (platp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) port->mapbase = platp->mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (res_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) port->irq = res_irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else if (platp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) port->irq = platp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Check platform data first so we can override device node data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (platp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) port->uartclk = platp->uartclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &port->uartclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (platp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) port->regshift = platp->bus_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) port->regshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) port->line = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) port->type = PORT_ALTERA_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) port->iotype = SERIAL_IO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) port->ops = &altera_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) platform_set_drvdata(pdev, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) uart_add_one_port(&altera_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int altera_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct uart_port *port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) uart_remove_one_port(&altera_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) port->mapbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const struct of_device_id altera_uart_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { .compatible = "ALTR,uart-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { .compatible = "altr,uart-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MODULE_DEVICE_TABLE(of, altera_uart_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static struct platform_driver altera_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .probe = altera_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .remove = altera_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .of_match_table = of_match_ptr(altera_uart_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int __init altera_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rc = uart_register_driver(&altera_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) rc = platform_driver_register(&altera_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) uart_unregister_driver(&altera_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void __exit altera_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) platform_driver_unregister(&altera_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uart_unregister_driver(&altera_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) module_init(altera_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) module_exit(altera_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MODULE_DESCRIPTION("Altera UART driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_ALIAS("platform:" DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_ALTERA_MAJOR);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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