Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for 8250/16550-type serial ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2001 Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "../serial_mctrl_gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct uart_8250_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	int (*tx_dma)(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	int (*rx_dma)(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	/* Filter function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	dma_filter_fn		fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	/* Parameter to the filter function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	void			*rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	void			*tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct dma_slave_config	rxconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct dma_slave_config	txconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct dma_chan		*rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct dma_chan		*txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	/* Device address base for DMA operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	phys_addr_t		rx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	phys_addr_t		tx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	/* DMA address of the buffer in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	dma_addr_t		rx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	dma_addr_t		tx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	dma_cookie_t		rx_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	dma_cookie_t		tx_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void			*rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	size_t			rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	size_t			tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned char		tx_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned char		tx_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned char		rx_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	size_t			rx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct old_serial_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	upf_t        flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned char io_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned char __iomem *iomem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned short iomem_reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct serial8250_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned short	fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned short	tx_loadsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned char	fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned char	rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned int	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define UART_CAP_FIFO	(1 << 8)	/* UART has FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define UART_CAP_EFR	(1 << 9)	/* UART has EFR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define UART_CAP_SLEEP	(1 << 10)	/* UART has IER sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define UART_CAP_AFE	(1 << 11)	/* MCR-based hw flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define UART_CAP_UUE	(1 << 12)	/* UART needs IER bit 6 set (Xscale) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define UART_CAP_RTOIE	(1 << 13)	/* UART needs IER bit 4 set (Xscale, Tegra) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define UART_CAP_HFIFO	(1 << 14)	/* UART has a "hidden" FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define UART_CAP_RPM	(1 << 15)	/* Runtime PM is active while idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define UART_CAP_IRDA	(1 << 16)	/* UART supports IrDA line discipline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define UART_CAP_MINI	(1 << 17)	/* Mini UART on BCM283X family lacks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					 * STOP PARITY EPAR SPAR WLEN5 WLEN6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define UART_BUG_QUOT	(1 << 0)	/* UART has buggy quot LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define UART_BUG_TXEN	(1 << 1)	/* UART has buggy TX IIR status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define UART_BUG_NOMSR	(1 << 2)	/* UART has buggy MSR status bits (Au1x00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define UART_BUG_THRE	(1 << 3)	/* UART has buggy THRE reassertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define UART_BUG_PARITY	(1 << 4)	/* UART mishandles parity if FIFO enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define UART_BUG_TXRACE	(1 << 5)	/* UART Tx fails to set remote DR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #ifdef CONFIG_SERIAL_8250_SHARE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SERIAL8250_SHARE_IRQS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SERIAL8250_SHARE_IRQS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.iobase		= _base,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.irq		= _irq,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.uartclk	= 1843200,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.iotype		= UPIO_PORT,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.flags		= UPF_BOOT_AUTOCONF | (_flags),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline int serial_in(struct uart_8250_port *up, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return up->port.serial_in(&up->port, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void serial_out(struct uart_8250_port *up, int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	up->port.serial_out(&up->port, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline int serial_dl_read(struct uart_8250_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return up->dl_read(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void serial_dl_write(struct uart_8250_port *up, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	up->dl_write(up, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline bool serial8250_set_THRI(struct uart_8250_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (up->ier & UART_IER_THRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	up->ier |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	up->ier |= UART_IER_PTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline bool serial8250_clear_THRI(struct uart_8250_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (!(up->ier & UART_IER_THRI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	up->ier &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	up->ier &= ~UART_IER_PTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct uart_8250_port *serial8250_get_port(int line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void serial8250_rpm_get(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void serial8250_rpm_put(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void serial8250_rpm_get_tx(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void serial8250_rpm_put_tx(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void serial8250_em485_start_tx(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void serial8250_em485_stop_tx(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void serial8250_em485_destroy(struct uart_8250_port *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* MCR <-> TIOCM conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline int serial8250_TIOCM_to_MCR(int tiocm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int mcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (tiocm & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		mcr |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (tiocm & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		mcr |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (tiocm & TIOCM_OUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		mcr |= UART_MCR_OUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (tiocm & TIOCM_OUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		mcr |= UART_MCR_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (tiocm & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		mcr |= UART_MCR_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline int serial8250_MCR_to_TIOCM(int mcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int tiocm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (mcr & UART_MCR_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		tiocm |= TIOCM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (mcr & UART_MCR_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		tiocm |= TIOCM_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (mcr & UART_MCR_OUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		tiocm |= TIOCM_OUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (mcr & UART_MCR_OUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		tiocm |= TIOCM_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (mcr & UART_MCR_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		tiocm |= TIOCM_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	return tiocm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* MSR <-> TIOCM conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int serial8250_MSR_to_TIOCM(int msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int tiocm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (msr & UART_MSR_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		tiocm |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (msr & UART_MSR_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		tiocm |= TIOCM_RNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (msr & UART_MSR_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		tiocm |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (msr & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		tiocm |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return tiocm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void serial8250_out_MCR(struct uart_8250_port *up, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	serial_out(up, UART_MCR, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (up->gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		mctrl_gpio_set(up->gpios, serial8250_MCR_to_TIOCM(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline int serial8250_in_MCR(struct uart_8250_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	mctrl = serial_in(up, UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (up->gpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		unsigned int mctrl_gpio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		mctrl_gpio = mctrl_gpio_get_outputs(up->gpios, &mctrl_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		mctrl |= serial8250_TIOCM_to_MCR(mctrl_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #if defined(__alpha__) && !defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * Digital did something really horribly wrong with the OUT1 and OUT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * lines on at least some ALPHA's.  The failure mode is that if either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * is cleared, the machine locks up with endless interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ALPHA_KLUDGE_MCR  (UART_MCR_OUT2 | UART_MCR_OUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ALPHA_KLUDGE_MCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_SERIAL_8250_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int serial8250_pnp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void serial8250_pnp_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline int serial8250_pnp_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline void serial8250_pnp_exit(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifdef CONFIG_SERIAL_8250_FINTEK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int fintek_8250_probe(struct uart_8250_port *uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef CONFIG_ARCH_OMAP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline int is_omap1_8250(struct uart_8250_port *pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	switch (pt->port.mapbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	case OMAP1_UART1_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	case OMAP1_UART2_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case OMAP1_UART3_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		res = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline int is_omap1510_8250(struct uart_8250_port *pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (!cpu_is_omap1510())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return is_omap1_8250(pt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline int is_omap1_8250(struct uart_8250_port *pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static inline int is_omap1510_8250(struct uart_8250_port *pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifdef CONFIG_SERIAL_8250_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) extern int serial8250_tx_dma(struct uart_8250_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) extern int serial8250_rx_dma(struct uart_8250_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) extern int serial8250_start_rx_dma(struct uart_8250_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) extern void serial8250_rx_dma_flush(struct uart_8250_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) extern int serial8250_request_dma(struct uart_8250_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) extern void serial8250_release_dma(struct uart_8250_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline int serial8250_tx_dma(struct uart_8250_port *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline int serial8250_rx_dma(struct uart_8250_port *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static inline int serial8250_start_rx_dma(struct uart_8250_port *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline int serial8250_request_dma(struct uart_8250_port *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline void serial8250_release_dma(struct uart_8250_port *p) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	status = serial_in(up, 0x04); /* EXCR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PRESL(x) ((x) & 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (PRESL(status) == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		/* already in high speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		serial_out(up, 0x04, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline int serial_index(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	return port->minor - 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }