^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on drivers/char/serial.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/hardware/dec21285.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BAUD_BASE (mem_fclk_21285/64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SERIAL_21285_NAME "ttyFB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SERIAL_21285_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SERIAL_21285_MINOR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RXSTAT_DUMMY_READ 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RXSTAT_FRAME (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RXSTAT_PARITY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RXSTAT_OVERRUN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RXSTAT_ANYERR (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define H_UBRLCR_BREAK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define H_UBRLCR_PARENB (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define H_UBRLCR_PAREVN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define H_UBRLCR_STOPB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define H_UBRLCR_FIFO (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char serial21285_name[] = "Footbridge UART";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * We only need 2 bits of data, so instead of creating a whole structure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * this, use bits of the private_data pointer of the uart port structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define tx_enabled_bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define rx_enabled_bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static bool is_enabled(struct uart_port *port, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long *private_data = (unsigned long *)&port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (test_bit(bit, private_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void enable(struct uart_port *port, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long *private_data = (unsigned long *)&port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) set_bit(bit, private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void disable(struct uart_port *port, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long *private_data = (unsigned long *)&port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clear_bit(bit, private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define is_tx_enabled(port) is_enabled(port, tx_enabled_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define tx_enable(port) enable(port, tx_enabled_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define tx_disable(port) disable(port, tx_enabled_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define is_rx_enabled(port) is_enabled(port, rx_enabled_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define rx_enable(port) enable(port, rx_enabled_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define rx_disable(port) disable(port, rx_enabled_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The documented expression for selecting the divisor is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * BAUD_BASE / baud - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * However, typically BAUD_BASE is not divisible by baud, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * we want to select the divisor that gives us the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * error. Therefore, we want:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * int(BAUD_BASE / baud - 0.5) ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * int(BAUD_BASE / baud - (baud >> 1) / baud) ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * int((BAUD_BASE - (baud >> 1)) / baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void serial21285_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (is_tx_enabled(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) disable_irq_nosync(IRQ_CONTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tx_disable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void serial21285_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!is_tx_enabled(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enable_irq(IRQ_CONTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tx_enable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void serial21285_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (is_rx_enabled(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) disable_irq_nosync(IRQ_CONRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rx_disable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int status, ch, flag, rxs, max_count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) status = *CSR_UARTFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) while (!(status & 0x10) && max_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ch = *CSR_UARTDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (unlikely(rxs & RXSTAT_ANYERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (rxs & RXSTAT_PARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else if (rxs & RXSTAT_FRAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (rxs & RXSTAT_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rxs &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (rxs & RXSTAT_PARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else if (rxs & RXSTAT_FRAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) status = *CSR_UARTFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *CSR_UARTDR = port->x_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) serial21285_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *CSR_UARTDR = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } while (--count > 0 && !(*CSR_UARTFLG & 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) serial21285_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static unsigned int serial21285_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* no modem control lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static unsigned int serial21285_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void serial21285_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int h_lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) h_lcr = *CSR_H_UBRLCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) h_lcr |= H_UBRLCR_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) h_lcr &= ~H_UBRLCR_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *CSR_H_UBRLCR = h_lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int serial21285_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tx_enable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rx_enable(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) serial21285_name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) serial21285_name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) free_irq(IRQ_CONRX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void serial21285_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) free_irq(IRQ_CONTX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) free_irq(IRQ_CONRX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int baud, quot, h_lcr, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * We don't support modem control lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) termios->c_cflag |= CLOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * We don't support BREAK character recognition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) termios->c_iflag &= ~(IGNBRK | BRKINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Ask the core to calculate the divisor for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) quot = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) b = port->uartclk / (16 * quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tty_termios_encode_baud_rate(termios, b, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) h_lcr = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) h_lcr = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) h_lcr = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default: /* CS8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) h_lcr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) h_lcr |= H_UBRLCR_STOPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) h_lcr |= H_UBRLCR_PARENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!(termios->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) h_lcr |= H_UBRLCR_PAREVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (port->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) h_lcr |= H_UBRLCR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Update the per-port timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Which character status flags are we interested in?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) port->read_status_mask = RXSTAT_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Which character status flags should we ignore?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) port->ignore_status_mask |= RXSTAT_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Ignore all characters if CREAD is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) port->ignore_status_mask |= RXSTAT_DUMMY_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) quot -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *CSR_UARTCON = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *CSR_L_UBRLCR = quot & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *CSR_M_UBRLCR = (quot >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *CSR_H_UBRLCR = h_lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *CSR_UARTCON = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const char *serial21285_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return port->type == PORT_21285 ? "DC21285" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void serial21285_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) release_mem_region(port->mapbase, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int serial21285_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return request_mem_region(port->mapbase, 32, serial21285_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) != NULL ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void serial21285_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) port->type = PORT_21285;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * verify the new serial_struct (for TIOCSSERIAL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ser->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ser->baud_base != port->uartclk / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct uart_ops serial21285_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .tx_empty = serial21285_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .get_mctrl = serial21285_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .set_mctrl = serial21285_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .stop_tx = serial21285_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .start_tx = serial21285_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .stop_rx = serial21285_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .break_ctl = serial21285_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .startup = serial21285_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .shutdown = serial21285_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .set_termios = serial21285_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .type = serial21285_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .release_port = serial21285_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .request_port = serial21285_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .config_port = serial21285_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .verify_port = serial21285_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct uart_port serial21285_port = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .mapbase = 0x42000160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .irq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .ops = &serial21285_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .flags = UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void serial21285_setup_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) serial21285_port.uartclk = mem_fclk_21285 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #ifdef CONFIG_SERIAL_21285_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void serial21285_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) while (*CSR_UARTFLG & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *CSR_UARTDR = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) serial21285_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) serial21285_get_options(struct uart_port *port, int *baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int *parity, int *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (*CSR_UARTCON == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tmp = *CSR_H_UBRLCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch (tmp & 0x60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *bits = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (tmp & H_UBRLCR_PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *parity = 'o';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (tmp & H_UBRLCR_PAREVN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) *parity = 'e';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *baud = port->uartclk / (16 * (tmp + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int __init serial21285_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct uart_port *port = &serial21285_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (machine_is_personal_server())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) baud = 57600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Check whether an invalid uart number has been specified, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * if so, search for the first available port that does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) serial21285_get_options(port, &baud, &parity, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct uart_driver serial21285_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct console serial21285_console =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .name = SERIAL_21285_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .write = serial21285_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .setup = serial21285_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .data = &serial21285_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int __init rs285_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) serial21285_setup_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) register_console(&serial21285_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) console_initcall(rs285_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SERIAL_21285_CONSOLE &serial21285_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SERIAL_21285_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct uart_driver serial21285_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .driver_name = "ttyFB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .dev_name = "ttyFB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .major = SERIAL_21285_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .minor = SERIAL_21285_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .nr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .cons = SERIAL_21285_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int __init serial21285_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) printk(KERN_INFO "Serial: 21285 driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) serial21285_setup_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = uart_register_driver(&serial21285_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uart_add_one_port(&serial21285_reg, &serial21285_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void __exit serial21285_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) uart_remove_one_port(&serial21285_reg, &serial21285_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) uart_unregister_driver(&serial21285_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) module_init(serial21285_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) module_exit(serial21285_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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