^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rocket_int.h --- internal header file for rocket.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written by Theodore Ts'o, Copyright 1997.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 1997 Comtrol Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Definition of the types in rcktpt_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ROCKET_TYPE_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ROCKET_TYPE_MODEM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ROCKET_TYPE_MODEMII 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ROCKET_TYPE_MODEMIII 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ROCKET_TYPE_PC104 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) typedef unsigned char Byte_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) typedef unsigned int ByteIO_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) typedef unsigned int Word_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) typedef unsigned int WordIO_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) typedef unsigned int DWordIO_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Note! Normally the Linux I/O macros already take care of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * byte-swapping the I/O instructions. However, all accesses using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * sOutDW aren't really 32-bit accesses, but should be handled in byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * order. Hence the use of the cpu_to_le32() macro to byte-swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * things to no-op the byte swapping done by the big-endian outl()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void sOutB(unsigned short port, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifdef ROCKET_DEBUG_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) printk(KERN_DEBUG "sOutB(%x, %x)...\n", port, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) outb_p(value, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline void sOutW(unsigned short port, unsigned short value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef ROCKET_DEBUG_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) printk(KERN_DEBUG "sOutW(%x, %x)...\n", port, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) outw_p(value, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void out32(unsigned short port, Byte_t *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 value = get_unaligned_le32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef ROCKET_DEBUG_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) outl_p(value, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline unsigned char sInB(unsigned short port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return inb_p(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline unsigned short sInW(unsigned short port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return inw_p(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* This is used to move arrays of bytes so byte swapping isn't appropriate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define sInStrW(port, addr, count) if (count) insw(port, addr, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CTL_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AIOP_CTL_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CHAN_AIOP_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MAX_PORTS_PER_AIOP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAX_AIOPS_PER_BOARD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX_PORTS_PER_BOARD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Bus type ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define isISA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define isPCI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define isMC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Controller ID numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CTLID_NULL -1 /* no controller exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CTLID_0001 0x0001 /* controller release 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* AIOP ID numbers, identifies AIOP type implementing channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AIOPID_NULL -1 /* no AIOP or channel exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AIOPID_0001 0x0001 /* AIOP release 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Global Register Offsets - Direct Access - Fixed values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define _CMD_REG 0x38 /* Command Register 8 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define _UNUSED 0x3B /* Unused 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Channel Register Offsets for 1st channel in AIOP - Direct Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define _TD0 0x00 /* Transmit Data 16 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define _RD0 0x00 /* Receive Data 16 Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) Tx Control Register Offsets - Indexed - External - Fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Memory Controller Register Offsets - Indexed - External - Fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define _RX_FIFO 0x000 /* Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define _TX_FIFO 0x800 /* Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TXFIFO_SIZE 255 /* size of Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) Tx Priority Buffer - Indexed - External - Fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TXP_SIZE 0x20 /* 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Channel Register Offsets - Indexed - Internal - Fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define _BAUD 0xFF4 /* Baud Rate 16 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define STMBREAK 0x08 /* BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define STMFRAME 0x04 /* framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define STMRCVROVR 0x02 /* receiver over run error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define STMPARITY 0x01 /* parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define STMBREAKH 0x800 /* BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define STMFRAMEH 0x400 /* framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define STMRCVROVRH 0x200 /* receiver over run error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define STMPARITYH 0x100 /* parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CTS_ACT 0x20 /* CTS input asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DSR_ACT 0x10 /* DSR input asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CD_ACT 0x08 /* CD input asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TXFIFOMT 0x04 /* Tx FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TXSHRMT 0x02 /* Tx shift register is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RDA 0x01 /* Rx data available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define STATMODE 0x8000 /* status mode enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RXFOVERFL 0x2000 /* receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RX2MATCH 0x1000 /* receive compare byte 2 match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RX1MATCH 0x0800 /* receive compare byte 1 match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RXBREAK 0x0400 /* received BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RXFRAME 0x0200 /* received framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RXPARITY 0x0100 /* received parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CTSFC_EN 0x80 /* CTS flow control enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TXINT_EN 0x10 /* transmit interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SETBREAK 0x10 /* send break condition (must clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LOCALLOOP 0x08 /* local loopback set for test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SET_DTR 0x04 /* assert DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SET_RTS 0x02 /* assert RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TX_ENABLE 0x01 /* enable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RTSFC_EN 0x40 /* RTS flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RXPROC_EN 0x20 /* receive processor enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TRIG_1 0x08 /* trigger level 1 char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TRIG_1_2 0x10 /* trigger level 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TRIG_7_8 0x18 /* trigger level 7/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TRIG_MASK 0x18 /* trigger level mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RXINT_EN 0x02 /* Rx interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MCINT_EN 0x01 /* modem change interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRC_INT 0x08 /* special receive condition interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DELTA_CD 0x04 /* CD change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DELTA_CTS 0x02 /* CTS change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DELTA_DSR 0x01 /* DSR change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IGN2_EN 0x08 /* ignore byte 2 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IGN1_EN 0x04 /* ignore byte 1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define COMP2_EN 0x02 /* compare byte 2 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define COMP1_EN 0x01 /* compare byte 1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RESET_ALL 0x80 /* reset AIOP (all channels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TXOVERIDE 0x40 /* Transmit software off override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RESETUART 0x20 /* reset channel's UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define INTR_EN 0x08 /* allow interrupts to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUDBAC remapped for PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define _CFG_INT_PCI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define _PCI_INT_FUNC 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCI_STROB 0x2000 /* bit 13 of int aiop register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define INTR_EN_PCI 0x0010 /* allow interrupts to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Definitions for Universal PCI board registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define _PCI_9030_GPIO_CTRL 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PCI_INT_CTRL_AIOP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PCI_GPIO_CTRL_8PORT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CHAN3_EN 0x08 /* enable AIOP 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CHAN2_EN 0x04 /* enable AIOP 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CHAN1_EN 0x02 /* enable AIOP 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CHAN0_EN 0x01 /* enable AIOP 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define FREQ_DIS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define FREQ_274HZ 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define FREQ_137HZ 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define FREQ_69HZ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define FREQ_34HZ 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define FREQ_17HZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define FREQ_9HZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define RDATASIZE 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define RREGDATASIZE 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * AIOP interrupt bits for ISA/PCI boards and UPCI boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define AIOP_INTR_BIT_0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AIOP_INTR_BIT_1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AIOP_INTR_BIT_2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AIOP_INTR_BIT_3 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AIOP_INTR_BITS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) AIOP_INTR_BIT_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) | AIOP_INTR_BIT_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) | AIOP_INTR_BIT_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) | AIOP_INTR_BIT_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define UPCI_AIOP_INTR_BIT_0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define UPCI_AIOP_INTR_BIT_1 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define UPCI_AIOP_INTR_BIT_2 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define UPCI_AIOP_INTR_BIT_3 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define UPCI_AIOP_INTR_BITS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) UPCI_AIOP_INTR_BIT_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) | UPCI_AIOP_INTR_BIT_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) | UPCI_AIOP_INTR_BIT_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) | UPCI_AIOP_INTR_BIT_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Controller level information structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int CtlID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int CtlNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int BusType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int boardType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int isUPCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) WordIO_t PCIIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) WordIO_t PCIIO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ByteIO_t MBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ByteIO_t MReg1IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ByteIO_t MReg2IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ByteIO_t MReg3IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) Byte_t MReg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) Byte_t MReg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int NumAiop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int AltChanRingIndicator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ByteIO_t UPCIRingInd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) WordIO_t AiopIO[AIOP_CTL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int AiopID[AIOP_CTL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int AiopNumChan[AIOP_CTL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) Word_t *AiopIntrBits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } CONTROLLER_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) typedef CONTROLLER_T CONTROLLER_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Channel level information structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CONTROLLER_T *CtlP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int AiopNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ChanID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ChanNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int rtsToggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ByteIO_t Cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ByteIO_t IntChan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ByteIO_t IntMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DWordIO_t IndexAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) WordIO_t IndexData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WordIO_t TxRxData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) WordIO_t ChanStat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) WordIO_t TxRxCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ByteIO_t IntID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) Word_t TxFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) Word_t TxFIFOPtrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) Word_t RxFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) Word_t RxFIFOPtrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) Word_t TxPrioCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) Word_t TxPrioPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) Word_t TxPrioBuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) Byte_t R[RREGDATASIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) Byte_t BaudDiv[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) Byte_t TxControl[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) Byte_t RxControl[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) Byte_t TxEnables[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) Byte_t TxCompare[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) Byte_t TxReplace1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) Byte_t TxReplace2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } CHANNEL_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) typedef CHANNEL_T CHANNEL_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) typedef CHANNEL_T *CHANPTR_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define InterfaceModeRS232 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define InterfaceModeRS422 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define InterfaceModeRS485 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define InterfaceModeRS232T 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) Function: sClrBreak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) Purpose: Stop sending a transmit BREAK signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) Call: sClrBreak(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define sClrBreak(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (ChP)->TxControl[3] &= ~SETBREAK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) Function: sClrDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) Purpose: Clr the DTR output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) Call: sClrDTR(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define sClrDTR(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (ChP)->TxControl[3] &= ~SET_DTR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) Function: sClrRTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) Purpose: Clr the RTS output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) Call: sClrRTS(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define sClrRTS(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if ((ChP)->rtsToggle) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) (ChP)->TxControl[3] &= ~SET_RTS; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) Function: sClrTxXOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) Purpose: Clear any existing transmit software flow control off condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) Call: sClrTxXOFF(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define sClrTxXOFF(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) Function: sCtlNumToCtlPtr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) Purpose: Convert a controller number to controller structure pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) Call: sCtlNumToCtlPtr(CtlNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int CtlNum; Controller number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Return: CONTROLLER_T *: Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) Function: sControllerEOI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) Purpose: Strobe the MUDBAC's End Of Interrupt bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) Call: sControllerEOI(CtlP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) Function: sPCIControllerEOI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) Purpose: Strobe the PCI End Of Interrupt bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) For the UPCI boards, toggle the AIOP interrupt enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (this was taken from the Windows driver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) Call: sPCIControllerEOI(CtlP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define sPCIControllerEOI(CTLP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((CTLP)->isUPCI) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) Word_t w = sInW((CTLP)->PCIIO); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sOutW((CTLP)->PCIIO, w); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) sOutW((CTLP)->PCIIO, PCI_STROB); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) Function: sDisAiop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) Purpose: Disable I/O access to an AIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) Call: sDisAiop(CltP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int AiopNum; Number of AIOP on controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define sDisAiop(CTLP,AIOPNUM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) Function: sDisCTSFlowCtl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) Purpose: Disable output flow control using CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) Call: sDisCTSFlowCtl(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define sDisCTSFlowCtl(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (ChP)->TxControl[2] &= ~CTSFC_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) Function: sDisIXANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) Purpose: Disable IXANY Software Flow Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) Call: sDisIXANY(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define sDisIXANY(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) (ChP)->R[0x0e] = 0x86; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) Function: DisParity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) Purpose: Disable parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) Call: sDisParity(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) Comments: Function sSetParity() can be used in place of functions sEnParity(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sDisParity(), sSetOddParity(), and sSetEvenParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define sDisParity(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (ChP)->TxControl[2] &= ~PARITY_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) Function: sDisRTSToggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) Purpose: Disable RTS toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) Call: sDisRTSToggle(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define sDisRTSToggle(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (ChP)->TxControl[2] &= ~RTSTOG_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) (ChP)->rtsToggle = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) Function: sDisRxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) Purpose: Disable Rx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) Call: sDisRxFIFO(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define sDisRxFIFO(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (ChP)->R[0x32] = 0x0a; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) Function: sDisRxStatusMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) Purpose: Disable the Rx status mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) Call: sDisRxStatusMode(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) Comments: This takes the channel out of the receive status mode. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) subsequent reads of receive data using sReadRxWord() will return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) two data bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) Function: sDisTransmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) Purpose: Disable transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) Call: sDisTransmit(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) This disables movement of Tx data from the Tx FIFO into the 1 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) Tx buffer. Therefore there could be up to a 2 byte latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) between the time sDisTransmit() is called and the transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) and transmit shift register going completely empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define sDisTransmit(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) (ChP)->TxControl[3] &= ~TX_ENABLE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) Function: sDisTxSoftFlowCtl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) Purpose: Disable Tx Software Flow Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) Call: sDisTxSoftFlowCtl(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define sDisTxSoftFlowCtl(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (ChP)->R[0x06] = 0x8a; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) Function: sEnAiop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) Purpose: Enable I/O access to an AIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) Call: sEnAiop(CltP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int AiopNum; Number of AIOP on controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define sEnAiop(CTLP,AIOPNUM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) Function: sEnCTSFlowCtl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) Purpose: Enable output flow control using CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) Call: sEnCTSFlowCtl(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define sEnCTSFlowCtl(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (ChP)->TxControl[2] |= CTSFC_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) Function: sEnIXANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) Purpose: Enable IXANY Software Flow Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) Call: sEnIXANY(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define sEnIXANY(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) (ChP)->R[0x0e] = 0x21; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) Function: EnParity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) Purpose: Enable parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) Call: sEnParity(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) Comments: Function sSetParity() can be used in place of functions sEnParity(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) sDisParity(), sSetOddParity(), and sSetEvenParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) Warnings: Before enabling parity odd or even parity should be chosen using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) functions sSetOddParity() or sSetEvenParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define sEnParity(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) (ChP)->TxControl[2] |= PARITY_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) Function: sEnRTSToggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) Purpose: Enable RTS toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) Call: sEnRTSToggle(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) Comments: This function will disable RTS flow control and clear the RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) line to allow operation of RTS toggle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define sEnRTSToggle(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) (ChP)->RxControl[2] &= ~RTSFC_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) out32((ChP)->IndexAddr,(ChP)->RxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) (ChP)->TxControl[2] |= RTSTOG_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) (ChP)->TxControl[3] &= ~SET_RTS; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (ChP)->rtsToggle = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) Function: sEnRxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) Purpose: Enable Rx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) Call: sEnRxFIFO(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define sEnRxFIFO(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (ChP)->R[0x32] = 0x08; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) Function: sEnRxProcessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) Purpose: Enable the receive processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) Call: sEnRxProcessor(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) Comments: This function is used to start the receive processor. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) the channel is in the reset state the receive processor is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) running. This is done to prevent the receive processor from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) executing invalid microcode instructions prior to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) downloading of the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) Warnings: This function must be called after valid microcode has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) downloaded to the AIOP, and it must not be called before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) microcode has been downloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define sEnRxProcessor(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (ChP)->RxControl[2] |= RXPROC_EN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) out32((ChP)->IndexAddr,(ChP)->RxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) Function: sEnRxStatusMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) Purpose: Enable the Rx status mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) Call: sEnRxStatusMode(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) Comments: This places the channel in the receive status mode. All subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) reads of receive data using sReadRxWord() will return a data byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) in the low word and a status byte in the high word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) Function: sEnTransmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) Purpose: Enable transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) Call: sEnTransmit(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define sEnTransmit(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (ChP)->TxControl[3] |= TX_ENABLE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) Function: sEnTxSoftFlowCtl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) Purpose: Enable Tx Software Flow Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) Call: sEnTxSoftFlowCtl(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define sEnTxSoftFlowCtl(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (ChP)->R[0x06] = 0xc5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) Function: sGetAiopIntStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) Purpose: Get the AIOP interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) Call: sGetAiopIntStatus(CtlP,AiopNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int AiopNum; AIOP number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) represent channels 0 through 7 respectively. If a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) bit is set that channel is interrupting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) Function: sGetAiopNumChan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) Purpose: Get the number of channels supported by an AIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) Call: sGetAiopNumChan(CtlP,AiopNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int AiopNum; AIOP number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) Return: int: The number of channels supported by the AIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) Function: sGetChanIntID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) Purpose: Get a channel's interrupt identification byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) Call: sGetChanIntID(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) Return: Byte_t: The channel interrupt ID. Can be any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) combination of the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RXF_TRIG: Rx FIFO trigger level interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) TXFIFO_MT: Tx FIFO empty interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SRC_INT: Special receive condition interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) DELTA_CD: CD change interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) DELTA_CTS: CTS change interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) DELTA_DSR: DSR change interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) Function: sGetChanNum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) Purpose: Get the number of a channel within an AIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) Call: sGetChanNum(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) Return: int: Channel number within AIOP, or NULLCHAN if channel does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) not exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define sGetChanNum(ChP) (ChP)->ChanNum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) Function: sGetChanStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) Purpose: Get the channel status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) Call: sGetChanStatus(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) Return: Word_t: The channel status. Can be any combination of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) LOW BYTE FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) CTS_ACT: CTS input asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DSR_ACT: DSR input asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) CD_ACT: CD input asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) TXFIFOMT: Tx FIFO is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TXSHRMT: Tx shift register is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) RDA: Rx data available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) HIGH BYTE FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) STATMODE: status mode enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) RXFOVERFL: receive FIFO overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) RX2MATCH: receive compare byte 2 match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) RX1MATCH: receive compare byte 1 match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) RXBREAK: received BREAK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) RXFRAME: received framing error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) RXPARITY: received parity error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) Warnings: This function will clear the high byte flags in the Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) Function: sGetChanStatusLo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) Purpose: Get the low byte only of the channel status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) Call: sGetChanStatusLo(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) Return: Byte_t: The channel status low byte. Can be any combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) of the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) CTS_ACT: CTS input asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DSR_ACT: DSR input asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) CD_ACT: CD input asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TXFIFOMT: Tx FIFO is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TXSHRMT: Tx shift register is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) RDA: Rx data available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /**********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * Get RI status of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Defined as a function in rocket.c -aes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) Function: sGetControllerIntStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) Purpose: Get the controller interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) Call: sGetControllerIntStatus(CtlP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) Return: Byte_t: The controller interrupt status in the lower 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) bits. Bits 0 through 3 represent AIOP's 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) through 3 respectively. If a bit is set that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) AIOP is interrupting. Bits 4 through 7 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) always be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) Function: sPCIGetControllerIntStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) Purpose: Get the controller interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) Call: sPCIGetControllerIntStatus(CtlP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) Return: unsigned char: The controller interrupt status in the lower 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) bits and bit 4. Bits 0 through 3 represent AIOP's 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) through 3 respectively. Bit 4 is set if the int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) was generated from periodic. If a bit is set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) AIOP is interrupting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define sPCIGetControllerIntStatus(CTLP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ((CTLP)->isUPCI ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) Function: sGetRxCnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) Purpose: Get the number of data bytes in the Rx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) Call: sGetRxCnt(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) Return: int: The number of data bytes in the Rx FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) Comments: Byte read of count register is required to obtain Rx count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) Function: sGetTxCnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) Purpose: Get the number of data bytes in the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) Call: sGetTxCnt(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) Return: Byte_t: The number of data bytes in the Tx FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) Comments: Byte read of count register is required to obtain Tx count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) Function: sGetTxRxDataIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) Purpose: Get the I/O address of a channel's TxRx Data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) Call: sGetTxRxDataIO(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) Return: WordIO_t: I/O address of a channel's TxRx Data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) Function: sInitChanDefaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) Purpose: Initialize a channel structure to it's default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) Call: sInitChanDefaults(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) CHANNEL_T *ChP; Ptr to the channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) Comments: This function must be called once for every channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) that exists before any other SSCI calls can be made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define sInitChanDefaults(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) (ChP)->CtlP = NULLCTLPTR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) (ChP)->AiopNum = NULLAIOP; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) (ChP)->ChanID = AIOPID_NULL; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) (ChP)->ChanNum = NULLCHAN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) Function: sResetAiopByNum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) Purpose: Reset the AIOP by number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) Call: sResetAiopByNum(CTLP,AIOPNUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) CONTROLLER_T CTLP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) AIOPNUM; AIOP index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define sResetAiopByNum(CTLP,AIOPNUM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) Function: sSendBreak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) Purpose: Send a transmit BREAK signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) Call: sSendBreak(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define sSendBreak(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) (ChP)->TxControl[3] |= SETBREAK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) Function: sSetBaud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) Purpose: Set baud rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) Call: sSetBaud(ChP,Divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) Word_t Divisor; 16 bit baud rate divisor for channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define sSetBaud(ChP,DIVISOR) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) Function: sSetData7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) Purpose: Set data bits to 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) Call: sSetData7(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define sSetData7(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) (ChP)->TxControl[2] &= ~DATA8BIT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) Function: sSetData8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) Purpose: Set data bits to 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) Call: sSetData8(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define sSetData8(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) (ChP)->TxControl[2] |= DATA8BIT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) Function: sSetDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) Purpose: Set the DTR output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) Call: sSetDTR(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define sSetDTR(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) (ChP)->TxControl[3] |= SET_DTR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) Function: sSetEvenParity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) Purpose: Set even parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) Call: sSetEvenParity(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) Comments: Function sSetParity() can be used in place of functions sEnParity(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) sDisParity(), sSetOddParity(), and sSetEvenParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) Warnings: This function has no effect unless parity is enabled with function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) sEnParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define sSetEvenParity(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) (ChP)->TxControl[2] |= EVEN_PAR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) Function: sSetOddParity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) Purpose: Set odd parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) Call: sSetOddParity(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) Comments: Function sSetParity() can be used in place of functions sEnParity(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) sDisParity(), sSetOddParity(), and sSetEvenParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) Warnings: This function has no effect unless parity is enabled with function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) sEnParity().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define sSetOddParity(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) (ChP)->TxControl[2] &= ~EVEN_PAR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) Function: sSetRTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) Purpose: Set the RTS output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) Call: sSetRTS(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define sSetRTS(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if ((ChP)->rtsToggle) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) (ChP)->TxControl[3] |= SET_RTS; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) Function: sSetRxTrigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) Purpose: Set the Rx FIFO trigger level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) Call: sSetRxProcessor(ChP,Level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) Byte_t Level; Number of characters in Rx FIFO at which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) interrupt will be generated. Can be any of the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) TRIG_NO: no trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) TRIG_1: 1 character in FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) TRIG_1_2: FIFO 1/2 full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) TRIG_7_8: FIFO 7/8 full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) Comments: An interrupt will be generated when the trigger level is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) only if function sEnInterrupt() has been called with flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) register will be set whenever the trigger level is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) regardless of the setting of RXINT_EN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define sSetRxTrigger(ChP,LEVEL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) (ChP)->RxControl[2] &= ~TRIG_MASK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) (ChP)->RxControl[2] |= LEVEL; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) out32((ChP)->IndexAddr,(ChP)->RxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) Function: sSetStop1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) Purpose: Set stop bits to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) Call: sSetStop1(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define sSetStop1(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) (ChP)->TxControl[2] &= ~STOP2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) Function: sSetStop2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) Purpose: Set stop bits to 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) Call: sSetStop2(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define sSetStop2(ChP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) (ChP)->TxControl[2] |= STOP2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) out32((ChP)->IndexAddr,(ChP)->TxControl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) Function: sSetTxXOFFChar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) Purpose: Set the Tx XOFF flow control character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) Call: sSetTxXOFFChar(ChP,Ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) Byte_t Ch; The value to set the Tx XOFF character to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define sSetTxXOFFChar(ChP,CH) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) (ChP)->R[0x07] = (CH); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) Function: sSetTxXONChar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) Purpose: Set the Tx XON flow control character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) Call: sSetTxXONChar(ChP,Ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) Byte_t Ch; The value to set the Tx XON character to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define sSetTxXONChar(ChP,CH) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) (ChP)->R[0x0b] = (CH); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) Function: sStartRxProcessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) Purpose: Start a channel's receive processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) Call: sStartRxProcessor(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) Comments: This function is used to start a Rx processor after it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) will restart both the Rx processor and software input flow control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) Function: sWriteTxByte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) Purpose: Write a transmit data byte to a channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ByteIO_t io: Channel transmit register I/O address. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) be obtained with sGetTxRxDataIO().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) Byte_t Data; The transmit data byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) Warnings: This function writes the data byte without checking to see if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sMaxTxSize is exceeded in the Tx FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Begin Linux specific definitions for the Rocketport driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * This code is Copyright Theodore Ts'o, 1995-1997
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct r_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct tty_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int flags; /* Don't yet match the ASY_ flags!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) unsigned int board:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) unsigned int aiop:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned int chan:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) CONTROLLER_t *ctlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) CHANNEL_t channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int xmit_fifo_room; /* room in xmit fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) unsigned char *xmit_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int xmit_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int xmit_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) int xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int cd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) int ignore_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct mutex write_mtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define RPORT_MAGIC 0x525001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define NUM_BOARDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define MAX_RP_PORTS (32*NUM_BOARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * The size of the xmit buffer is 1 page, or 4096 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define XMIT_BUF_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* number of characters left in xmit buffer before we ask for more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define WAKEUP_CHARS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Assigned major numbers for the Comtrol Rocketport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define TTY_ROCKET_MAJOR 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define CUA_ROCKET_MAJOR 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #ifdef PCI_VENDOR_ID_RP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #undef PCI_VENDOR_ID_RP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #undef PCI_DEVICE_ID_RP8OCTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #undef PCI_DEVICE_ID_RP8INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #undef PCI_DEVICE_ID_RP16INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #undef PCI_DEVICE_ID_RP32INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #undef PCI_DEVICE_ID_URP8OCTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #undef PCI_DEVICE_ID_URP8INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #undef PCI_DEVICE_ID_URP16INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #undef PCI_DEVICE_ID_CRP16INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #undef PCI_DEVICE_ID_URP32INTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Comtrol PCI Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define PCI_VENDOR_ID_RP 0x11fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Comtrol Device ID's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Universal PCI boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* Compact PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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