^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RocketPort device driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Kernel Synchronization:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This driver has 2 kernel control paths - exception handlers (calls into the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * are not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Critical data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * serial port state information and the xmit_buf circular buffer. Protected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * a per port spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * is data to be transmitted. Protected by atomic bit operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * rp_write() and rp_write_char() functions use a per port semaphore to protect against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * simultaneous access to the same port by more than one process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /****** Defines ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ROCKET_PARANOIA_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ROCKET_DISABLE_SIMUSAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #undef ROCKET_SOFT_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #undef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #undef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #undef ROCKET_DEBUG_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #undef ROCKET_DEBUG_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #undef ROCKET_DEBUG_THROTTLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #undef ROCKET_DEBUG_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #undef ROCKET_DEBUG_HANGUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #undef REV_PCI_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #undef ROCKET_DEBUG_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /****** Kernel includes ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/tty_driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /****** RocketPort includes ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include "rocket_int.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include "rocket.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ROCKET_VERSION "2.09"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ROCKET_DATE "12-June-2003"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /****** RocketPort Local Variables ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void rp_do_poll(struct timer_list *unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct tty_driver *rocket_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct rocket_version driver_version = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ROCKET_VERSION, ROCKET_DATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* eg. Bit 0 indicates port 0 has xmit data, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static atomic_t rp_num_ports_open; /* Number of serial ports open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static DEFINE_TIMER(rocket_timer, rp_do_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static unsigned long board2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned long board3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static unsigned long board4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static unsigned long controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static bool support_low_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned long modem1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned long modem2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static unsigned long modem3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static unsigned long modem4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned long pc104_1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static unsigned long pc104_2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static unsigned long pc104_3[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned long pc104_4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned long rcktpt_io_addr[NUM_BOARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int rcktpt_type[NUM_BOARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int is_PCI[NUM_BOARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static rocketModel_t rocketModel[NUM_BOARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int max_board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct tty_port_operations rocket_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The following arrays define the interrupt bits corresponding to each AIOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * These bits are different between the ISA and regular PCI boards and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Universal PCI boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AIOP_INTR_BIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) AIOP_INTR_BIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) AIOP_INTR_BIT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AIOP_INTR_BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) UPCI_AIOP_INTR_BIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) UPCI_AIOP_INTR_BIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) UPCI_AIOP_INTR_BIT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) UPCI_AIOP_INTR_BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static Byte_t RData[RDATASIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x00, 0x09, 0xf6, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x02, 0x09, 0x86, 0xfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x04, 0x09, 0x00, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x06, 0x09, 0x01, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x08, 0x09, 0x8a, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x0a, 0x09, 0xc5, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x0c, 0x09, 0x86, 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x0e, 0x09, 0x20, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x10, 0x09, 0x21, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x12, 0x09, 0x41, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x14, 0x09, 0x82, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x16, 0x09, 0x82, 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x18, 0x09, 0x8a, 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x1a, 0x09, 0x88, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x1c, 0x09, 0x86, 0x7a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x1e, 0x09, 0x84, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x20, 0x09, 0x82, 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x22, 0x09, 0x0a, 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static Byte_t RRegData[RREGDATASIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static CONTROLLER_T sController[CTL_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static Byte_t sBitMapClrTbl[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static Byte_t sBitMapSetTbl[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int sClockPrescale = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Line number is the ttySIx number (x), the Minor number. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * assign them sequentially, starting at zero. The following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * array keeps track of the line number assigned to a given board/aiop/channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static unsigned char lineNumbers[MAX_RP_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static unsigned long nextLineNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /***** RocketPort Static Prototypes *********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int __init init_ISA(int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void rp_flush_buffer(struct tty_struct *tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void rp_start(struct tty_struct *tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ChanNum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void sFlushRxFIFO(CHANNEL_T * ChP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void sFlushTxFIFO(CHANNEL_T * ChP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ByteIO_t * AiopIOList, int AiopIOListSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int IRQNum, Byte_t Frequency, int PeriodicOnly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int sReadAiopID(ByteIO_t io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int sReadAiopNumChan(WordIO_t io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_AUTHOR("Theodore Ts'o");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_DESCRIPTION("Comtrol RocketPort driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) module_param_hw(board1, ulong, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) module_param_hw(board2, ulong, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) module_param_hw(board3, ulong, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) module_param_hw(board4, ulong, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) module_param_hw(controller, ulong, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) module_param(support_low_speed, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) module_param(modem1, ulong, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) module_param(modem2, ulong, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) module_param(modem3, ulong, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) module_param(modem4, ulong, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) module_param_array(pc104_1, ulong, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) module_param_array(pc104_2, ulong, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) module_param_array(pc104_3, ulong, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) module_param_array(pc104_4, ulong, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int __init rp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void rp_cleanup_module(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) module_init(rp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) module_exit(rp_cleanup_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Module code starts here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static inline int rocket_paranoia_check(struct r_port *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const char *routine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #ifdef ROCKET_PARANOIA_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (info->magic != RPORT_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) printk(KERN_WARNING "Warning: bad magic number for rocketport "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "struct in %s\n", routine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * tty layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int ChanStatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int CharNStat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ToRecv, wRecv, space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned char *cbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ToRecv = sGetRxCnt(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #ifdef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ToRecv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * if status indicates there are errored characters in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * FIFO, then enter status mode (a word in FIFO holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * character and status).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!(ChanStatus & STATMODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #ifdef ROCKET_DEBUG_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) printk(KERN_INFO "Entering STATMODE...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ChanStatus |= STATMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) sEnRxStatusMode(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * if we previously entered status mode, then read down the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * FIFO one word at a time, pulling apart the character and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * the status. Update error counters depending on status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ChanStatus & STATMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #ifdef ROCKET_DEBUG_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) printk(KERN_INFO "Ignore %x, read %x...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) info->ignore_status_mask, info->read_status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) while (ToRecv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CharNStat = sInW(sGetTxRxDataIO(cp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #ifdef ROCKET_DEBUG_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) printk(KERN_INFO "%x...\n", CharNStat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (CharNStat & STMBREAKH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CharNStat &= ~(STMFRAMEH | STMPARITYH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (CharNStat & info->ignore_status_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ToRecv--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CharNStat &= info->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (CharNStat & STMBREAKH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else if (CharNStat & STMPARITYH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else if (CharNStat & STMFRAMEH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else if (CharNStat & STMRCVROVRH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) flag = TTY_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tty_insert_flip_char(&info->port, CharNStat & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ToRecv--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * after we've emptied the FIFO in status mode, turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * status mode back off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (sGetRxCnt(cp) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #ifdef ROCKET_DEBUG_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) printk(KERN_INFO "Status mode off.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sDisRxStatusMode(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * we aren't in status mode, so read down the FIFO two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * characters at time by doing repeated word IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (space < ToRecv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef ROCKET_DEBUG_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (space <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ToRecv = space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) wRecv = ToRecv >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (wRecv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ToRecv & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Push the data up to the tty layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tty_flip_buffer_push(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Serial port transmit data function. Called from the timer polling loop as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void rp_do_transmit(struct r_port *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) CHANNEL_t *cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct tty_struct *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) printk(KERN_DEBUG "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tty = tty_port_tty_get(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (tty == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Loop sending data to FIFO until done or FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (tty->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) c = min(info->xmit_fifo_room, info->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (c <= 0 || info->xmit_fifo_room <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (c & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) info->xmit_tail += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) info->xmit_tail &= XMIT_BUF_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) info->xmit_cnt -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) info->xmit_fifo_room -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) printk(KERN_INFO "tx %d chars...\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (info->xmit_cnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (info->xmit_cnt < WAKEUP_CHARS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #ifdef ROCKETPORT_HAVE_POLL_WAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) wake_up_interruptible(&tty->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #ifdef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) info->xmit_tail, info->xmit_fifo_room);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Called when a serial port signals it has read data in it's RX FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * It checks what interrupts are pending and services them, including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * receiving serial data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void rp_handle_port(struct r_port *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int IntMask, ChanStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!tty_port_initialized(&info->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "info->flags & NOT_INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) IntMask = sGetChanIntID(cp) & info->intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #ifdef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ChanStatus = sGetChanStatus(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rp_do_receive(info, cp, ChanStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (IntMask & DELTA_CD) { /* CD change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (ChanStatus & CD_ACT) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!(ChanStatus & CD_ACT) && info->cd_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #ifdef ROCKET_DEBUG_HANGUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) printk(KERN_INFO "CD drop, calling hangup.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tty_port_tty_hangup(&info->port, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) wake_up_interruptible(&info->port.open_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #ifdef ROCKET_DEBUG_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (IntMask & DELTA_CTS) { /* CTS change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) printk(KERN_INFO "CTS change...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (IntMask & DELTA_DSR) { /* DSR change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) printk(KERN_INFO "DSR change...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * The top level polling routine. Repeats every 1/100 HZ (10ms).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void rp_do_poll(struct timer_list *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CONTROLLER_t *ctlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ctrl, aiop, ch, line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int xmitmask, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int CtlMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned char AiopMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) Word_t bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Walk through all the boards (ctrl's) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (ctrl = 0; ctrl < max_board; ctrl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (rcktpt_io_addr[ctrl] <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Get a ptr to the board's control struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ctlp = sCtlNumToCtlPtr(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Get the interrupt status from the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ctlp->BusType == isPCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) CtlMask = sPCIGetControllerIntStatus(ctlp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CtlMask = sGetControllerIntStatus(ctlp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Check if any AIOP read bits are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (aiop = 0; CtlMask; aiop++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bit = ctlp->AiopIntrBits[aiop];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (CtlMask & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CtlMask &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) AiopMask = sGetAiopIntStatus(ctlp, aiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Check if any port read bits are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (AiopMask & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Get the line number (/dev/ttyRx number). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Read the data from the port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) line = GetLineNumber(ctrl, aiop, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) rp_handle_port(rp_table[line]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) xmitmask = xmit_flags[ctrl];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * xmit_flags contains bit-significant flags, indicating there is data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * 1, ... (32 total possible). The variable i has the aiop and ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (xmitmask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (xmitmask & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) aiop = (i & 0x18) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ch = i & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) line = GetLineNumber(ctrl, aiop, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) rp_do_transmit(rp_table[line]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Reset the timer so we get called at the next clock tick (10ms).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (atomic_read(&rp_num_ports_open))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Initializes the r_port structure for a port, as well as enabling the port on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * Inputs: board, aiop, chan numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned rocketMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct r_port *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) CONTROLLER_T *ctlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Get the next available line number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) line = SetLineNumber(board, aiop, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ctlp = sCtlNumToCtlPtr(board);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) info->magic = RPORT_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) info->line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) info->ctlp = ctlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) info->board = board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) info->aiop = aiop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) info->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) tty_port_init(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) info->port.ops = &rocket_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) info->flags &= ~ROCKET_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (board < ARRAY_SIZE(pc104) && line < ARRAY_SIZE(pc104_1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) switch (pc104[board][line]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case 422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) info->flags |= ROCKET_MODE_RS422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case 485:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) info->flags |= ROCKET_MODE_RS485;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case 232:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) info->flags |= ROCKET_MODE_RS232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) info->flags |= ROCKET_MODE_RS232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) board, aiop, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tty_port_destroy(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) rocketMode = info->flags & ROCKET_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) sEnRTSToggle(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) sDisRTSToggle(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ctlp->boardType == ROCKET_TYPE_PC104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) switch (rocketMode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case ROCKET_MODE_RS485:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) sSetInterfaceMode(&info->channel, InterfaceModeRS485);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case ROCKET_MODE_RS422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) sSetInterfaceMode(&info->channel, InterfaceModeRS422);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case ROCKET_MODE_RS232:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (info->flags & ROCKET_RTS_TOGGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) sSetInterfaceMode(&info->channel, InterfaceModeRS232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) spin_lock_init(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mutex_init(&info->write_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) rp_table[line] = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tty_port_register_device(&info->port, rocket_driver, line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pci_dev ? &pci_dev->dev : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * Configures a rocketport port according to its termio settings. Called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void configure_r_port(struct tty_struct *tty, struct r_port *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unsigned rocketMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int bits, baud, divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct ktermios *t = &tty->termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cflag = t->c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Byte size and parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if ((cflag & CSIZE) == CS8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) sSetData8(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) bits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) sSetData7(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (cflag & CSTOPB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sSetStop2(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) sSetStop1(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) sEnParity(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (cflag & PARODD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) sSetOddParity(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sSetEvenParity(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) sDisParity(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) baud = tty_get_baud_rate(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if ((divisor >= 8192 || divisor < 0) && old_termios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) baud = tty_termios_baud_rate(old_termios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) divisor = (rp_baud_base[info->board] / baud) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (divisor >= 8192 || divisor < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) divisor = (rp_baud_base[info->board] / baud) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) info->cps = baud / bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) sSetBaud(cp, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* FIXME: Should really back compute a baud rate from the divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tty_encode_baud_rate(tty, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) info->intmask |= DELTA_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) sEnCTSFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) info->intmask &= ~DELTA_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) sDisCTSFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (cflag & CLOCAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) info->intmask &= ~DELTA_CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (sGetChanStatus(cp) & CD_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) info->cd_status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) info->cd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) info->intmask |= DELTA_CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Handle software flow control in the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #ifdef ROCKET_SOFT_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (I_IXON(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) sEnTxSoftFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (I_IXANY(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) sEnIXANY(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) sDisIXANY(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) sSetTxXONChar(cp, START_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) sSetTxXOFFChar(cp, STOP_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) sDisTxSoftFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) sDisIXANY(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sClrTxXOFF(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Set up ignore/read mask words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) info->read_status_mask = STMRCVROVRH | 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (I_INPCK(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) info->read_status_mask |= STMFRAMEH | STMPARITYH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (I_BRKINT(tty) || I_PARMRK(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) info->read_status_mask |= STMBREAKH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) info->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (I_IGNPAR(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (I_IGNBRK(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) info->ignore_status_mask |= STMBREAKH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * ignore overruns too. (For real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (I_IGNPAR(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) info->ignore_status_mask |= STMRCVROVRH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) rocketMode = info->flags & ROCKET_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if ((info->flags & ROCKET_RTS_TOGGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) || (rocketMode == ROCKET_MODE_RS485))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) sEnRTSToggle(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) sDisRTSToggle(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) sSetRTS(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) switch (rocketMode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case ROCKET_MODE_RS485:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) sSetInterfaceMode(cp, InterfaceModeRS485);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case ROCKET_MODE_RS422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sSetInterfaceMode(cp, InterfaceModeRS422);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case ROCKET_MODE_RS232:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (info->flags & ROCKET_RTS_TOGGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) sSetInterfaceMode(cp, InterfaceModeRS232T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) sSetInterfaceMode(cp, InterfaceModeRS232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int carrier_raised(struct tty_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct r_port *info = container_of(port, struct r_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static void dtr_rts(struct tty_port *port, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct r_port *info = container_of(port, struct r_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) sSetDTR(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) sSetRTS(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) sClrDTR(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) sClrRTS(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * port's r_port struct. Initializes the port hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int rp_open(struct tty_struct *tty, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct r_port *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct tty_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned long page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) info = rp_table[tty->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) port = &info->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) page = __get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * We must not sleep from here until the port is marked fully in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (info->xmit_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) free_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) info->xmit_buf = (unsigned char *) page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) tty->driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tty_port_tty_set(port, tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (port->count++ == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) atomic_inc(&rp_num_ports_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #ifdef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) printk(KERN_INFO "rocket mod++ = %d...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) atomic_read(&rp_num_ports_open));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #ifdef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Info->count is now 1; so it's safe to sleep now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!tty_port_initialized(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) sSetRxTrigger(cp, TRIG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (sGetChanStatus(cp) & CD_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) info->cd_status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) info->cd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) sDisRxStatusMode(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sFlushRxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) sFlushTxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) sSetRxTrigger(cp, TRIG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) sGetChanStatus(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) sDisRxStatusMode(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) sClrTxXOFF(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) sDisCTSFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) sDisTxSoftFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) sEnRxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) sEnTransmit(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) tty_port_set_initialized(&info->port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) configure_r_port(tty, info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (C_BAUD(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) sSetDTR(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) sSetRTS(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Starts (or resets) the maint polling loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) retval = tty_port_block_til_ready(port, tty, filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #ifdef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * Exception handler that closes a serial port. info->port.count is considered critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static void rp_close(struct tty_struct *tty, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct tty_port *port = &info->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (rocket_paranoia_check(info, "rp_close"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #ifdef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (tty_port_close_start(port, tty, filp) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mutex_lock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * Before we drop DTR, make sure the UART transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * has completely drained; this is especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * important if there is a transmit FIFO!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) rp_wait_until_sent(tty, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) sDisTransmit(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) sDisCTSFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) sDisTxSoftFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) sClrTxXOFF(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) sFlushRxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) sFlushTxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) sClrRTS(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (C_HUPCL(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) sClrDTR(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) rp_flush_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) tty_ldisc_flush(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* We can't yet use tty_port_close_end as the buffer handling in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) driver is a bit different to the usual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (port->blocked_open) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (port->close_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) msleep_interruptible(jiffies_to_msecs(port->close_delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) wake_up_interruptible(&port->open_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (info->xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) free_page((unsigned long) info->xmit_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) info->xmit_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) spin_lock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) tty->closing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) tty_port_set_initialized(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) tty_port_set_active(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) tty_port_tty_set(port, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) atomic_dec(&rp_num_ports_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #ifdef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) printk(KERN_INFO "rocket mod-- = %d...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) atomic_read(&rp_num_ports_open));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static void rp_set_termios(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) unsigned cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (rocket_paranoia_check(info, "rp_set_termios"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) cflag = tty->termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * This driver doesn't support CS5 or CS6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) tty->termios.c_cflag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Or CMSPAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) tty->termios.c_cflag &= ~CMSPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) configure_r_port(tty, info, old_termios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Handle transition to B0 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) sClrDTR(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) sClrRTS(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Handle transition away from B0 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) sSetRTS(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) sSetDTR(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) rp_start(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static int rp_break(struct tty_struct *tty, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (rocket_paranoia_check(info, "rp_break"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) sSendBreak(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) sClrBreak(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * the UPCI boards was added, it was decided to make this a function because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * the macro was getting too complicated. All cases except the first one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * (UPCIRingInd) are taken directly from the original macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int sGetChanRI(CHANNEL_T * ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) CONTROLLER_t *CtlP = ChP->CtlP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int ChanNum = ChP->ChanNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int RingInd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (CtlP->UPCIRingInd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) else if (CtlP->AltChanRingIndicator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) else if (CtlP->boardType == ROCKET_TYPE_PC104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return RingInd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /********************************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * Returns the state of the serial modem control lines. These next 2 functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int rp_tiocmget(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned int control, result, ChanStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ChanStatus = sGetChanStatusLo(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) control = info->channel.TxControl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ((control & SET_DTR) ? TIOCM_DTR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * Sets the modem control lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int rp_tiocmset(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unsigned int set, unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (set & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) info->channel.TxControl[3] |= SET_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (set & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) info->channel.TxControl[3] |= SET_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (clear & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) info->channel.TxControl[3] &= ~SET_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (clear & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) info->channel.TxControl[3] &= ~SET_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) out32(info->channel.IndexAddr, info->channel.TxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct rocket_config tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) memset(&tmp, 0, sizeof (tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mutex_lock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) tmp.line = info->line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) tmp.flags = info->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) tmp.close_delay = info->port.close_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) tmp.closing_wait = info->port.closing_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int set_config(struct tty_struct *tty, struct r_port *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct rocket_config __user *new_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct rocket_config new_serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mutex_lock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* warn about deprecation, unless clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (new_serial.flags & ROCKET_SPD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) info->port.close_delay = new_serial.close_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) info->port.closing_wait = new_serial.closing_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) configure_r_port(tty, info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * This function fills in a rocket_ports struct with information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * about what boards/ports are in the system. This info is passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * to user space. See setrocket.c where the info is used to create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * the /dev/ttyRx ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct rocket_ports *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int board, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) tmp->tty_major = rocket_driver->major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) for (board = 0; board < 4; board++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) tmp->rocketModel[board].model = rocketModel[board].model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) strcpy(tmp->rocketModel[board].modelString,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) rocketModel[board].modelString);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) tmp->rocketModel[board].numPorts = rocketModel[board].numPorts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) tmp->rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) tmp->rocketModel[board].startingPortNumber =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) rocketModel[board].startingPortNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (copy_to_user(retports, tmp, sizeof(*retports)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static int reset_rm2(struct r_port *info, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (copy_from_user(&reset, arg, sizeof (int)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (info->ctlp->BusType == isISA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) sModemReset(info->ctlp, info->chan, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) sPCIModemReset(info->ctlp, info->chan, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static int get_version(struct r_port *info, struct rocket_version __user *retvers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* IOCTL call handler into the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static int rp_ioctl(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case RCKP_GET_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_warn_ratelimited(tty->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "RCKP_GET_CONFIG option is deprecated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = get_config(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case RCKP_SET_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dev_warn_ratelimited(tty->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) "RCKP_SET_CONFIG option is deprecated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = set_config(tty, info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case RCKP_GET_PORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_warn_ratelimited(tty->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) "RCKP_GET_PORTS option is deprecated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = get_ports(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case RCKP_RESET_RM2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) dev_warn_ratelimited(tty->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "RCKP_RESET_RM2 option is deprecated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = reset_rm2(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) case RCKP_GET_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_warn_ratelimited(tty->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) "RCKP_GET_VERSION option is deprecated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = get_version(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static void rp_send_xchar(struct tty_struct *tty, char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (rocket_paranoia_check(info, "rp_send_xchar"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (sGetTxCnt(cp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sWriteTxPrioByte(cp, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) sWriteTxByte(sGetTxRxDataIO(cp), ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static void rp_throttle(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #ifdef ROCKET_DEBUG_THROTTLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) printk(KERN_INFO "throttle %s ....\n", tty->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (rocket_paranoia_check(info, "rp_throttle"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (I_IXOFF(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) rp_send_xchar(tty, STOP_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) sClrRTS(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static void rp_unthrottle(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #ifdef ROCKET_DEBUG_THROTTLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) printk(KERN_INFO "unthrottle %s ....\n", tty->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (rocket_paranoia_check(info, "rp_unthrottle"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (I_IXOFF(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) rp_send_xchar(tty, START_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) sSetRTS(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * ------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * rp_stop() and rp_start()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * This routines are called before setting or resetting tty->stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * They enable or disable transmitter interrupts, as necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * ------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static void rp_stop(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #ifdef ROCKET_DEBUG_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) info->xmit_cnt, info->xmit_fifo_room);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (rocket_paranoia_check(info, "rp_stop"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (sGetTxCnt(&info->channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) sDisTransmit(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static void rp_start(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #ifdef ROCKET_DEBUG_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) printk(KERN_INFO "start %s: %d %d....\n", tty->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) info->xmit_cnt, info->xmit_fifo_room);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (rocket_paranoia_check(info, "rp_stop"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) sEnTransmit(&info->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) set_bit((info->aiop * 8) + info->chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * rp_wait_until_sent() --- wait until the transmitter is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) unsigned long orig_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int check_time, exit_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) int txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (rocket_paranoia_check(info, "rp_wait_until_sent"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) printk(KERN_INFO "cps=%d...\n", info->cps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) txcnt = sGetTxCnt(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (!txcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (sGetChanStatusLo(cp) & TXSHRMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) check_time = (HZ / info->cps) / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) check_time = HZ * txcnt / info->cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) exit_time = orig_jiffies + timeout - jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (exit_time <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (exit_time < check_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) check_time = exit_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (check_time == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) check_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) jiffies, check_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) msleep_interruptible(jiffies_to_msecs(check_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (signal_pending(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) __set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static void rp_hangup(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (rocket_paranoia_check(info, "rp_hangup"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) rp_flush_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) spin_lock_irqsave(&info->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (info->port.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) atomic_dec(&rp_num_ports_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) spin_unlock_irqrestore(&info->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) tty_port_hangup(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) sDisRxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) sDisTransmit(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) sDisCTSFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) sDisTxSoftFlowCtl(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) sClrTxXOFF(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) tty_port_set_initialized(&info->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) wake_up_interruptible(&info->port.open_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * Exception handler - write char routine. The RocketPort driver uses a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * double-buffering strategy, with the twist that if the in-memory CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * buffer is empty, and there's space in the transmit FIFO, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * writing routines will write directly to transmit FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * Write buffer and counters protected by spinlocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static int rp_put_char(struct tty_struct *tty, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (rocket_paranoia_check(info, "rp_put_char"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * Grab the port write mutex, locking out other processes that try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * write to this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) mutex_lock(&info->write_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #ifdef ROCKET_DEBUG_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) printk(KERN_INFO "rp_put_char %c...\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!tty->stopped && info->xmit_fifo_room == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) info->xmit_buf[info->xmit_head++] = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) info->xmit_head &= XMIT_BUF_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) info->xmit_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) sOutB(sGetTxRxDataIO(cp), ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) info->xmit_fifo_room--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mutex_unlock(&info->write_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * Exception handler - write routine, called when user app writes to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * A per port write mutex is used to protect from another process writing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * this port at the same time. This other process could be running on the other CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * Spinlocks protect the info xmit members.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static int rp_write(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) const unsigned char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) const unsigned char *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) int c, retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (mutex_lock_interruptible(&info->write_mtx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #ifdef ROCKET_DEBUG_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) printk(KERN_INFO "rp_write %d chars...\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (!tty->stopped && info->xmit_fifo_room < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * If the write queue for the port is empty, and there is FIFO space, stuff bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * into FIFO. Use the write queue for temp storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) c = min(count, info->xmit_fifo_room);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) b = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Push data into FIFO, 2 bytes at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* If there is a byte remaining, write it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (c & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) sOutB(sGetTxRxDataIO(cp), b[c - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) retval += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) buf += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) count -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) info->xmit_fifo_room -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* If count is zero, we wrote it all and are done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* Write remaining data into the port's xmit_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* Hung up ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!tty_port_active(&info->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) c = min(c, XMIT_BUF_SIZE - info->xmit_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (c <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) b = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) memcpy(info->xmit_buf + info->xmit_head, b, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) info->xmit_head =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) info->xmit_cnt += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) buf += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) count -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) retval += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if ((retval > 0) && !tty->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (info->xmit_cnt < WAKEUP_CHARS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #ifdef ROCKETPORT_HAVE_POLL_WAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) wake_up_interruptible(&tty->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) mutex_unlock(&info->write_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * Return the number of characters that can be sent. We estimate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * only using the in-memory transmit buffer only, and ignore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * potential space in the transmit FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static int rp_write_room(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (rocket_paranoia_check(info, "rp_write_room"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #ifdef ROCKET_DEBUG_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) printk(KERN_INFO "rp_write_room returns %d...\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * Return the number of characters in the buffer. Again, this only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * counts those characters in the in-memory transmit buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int rp_chars_in_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #ifdef ROCKET_DEBUG_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return info->xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * r_port struct for the port. Note that spinlock are used to protect info members,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * do not call this function if the spinlock is already held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static void rp_flush_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) struct r_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) CHANNEL_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (rocket_paranoia_check(info, "rp_flush_buffer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #ifdef ROCKETPORT_HAVE_POLL_WAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) wake_up_interruptible(&tty->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) cp = &info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) sFlushTxFIFO(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static const struct pci_device_id rocket_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* Resets the speaker controller on RocketModem II and III devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ByteIO_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) addr = CtlP->AiopIO[0] + 0x4F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) sOutB(addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if ((model == MODEL_UPCI_RM3_8PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) || (model == MODEL_UPCI_RM3_4PORT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) addr = CtlP->AiopIO[0] + 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) sOutB(addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) Function: sPCIInitController
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) Purpose: Initialization of controller global registers and controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) IRQNum,Frequency,PeriodicOnly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) int CtlNum; Controller number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) This list must be in the order the AIOPs will be found on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) controller. Once an AIOP in the list is not found, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) assumed that there are no more AIOPs on the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) int AiopIOListSize; Number of addresses in AiopIOList
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) int IRQNum; Interrupt Request number. Can be any of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) 0: Disable global interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) 3: IRQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) 4: IRQ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) 5: IRQ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) 9: IRQ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) 10: IRQ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) 11: IRQ 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) 12: IRQ 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) 15: IRQ 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) Byte_t Frequency: A flag identifying the frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) of the periodic interrupt, can be any one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) FREQ_DIS - periodic interrupt disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) FREQ_137HZ - 137 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) FREQ_69HZ - 69 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) FREQ_34HZ - 34 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) FREQ_17HZ - 17 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) FREQ_9HZ - 9 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) FREQ_4HZ - 4 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) If IRQNum is set to 0 the Frequency parameter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) overidden, it is forced to a value of FREQ_DIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int PeriodicOnly: 1 if all interrupts except the periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) interrupt are to be blocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) 0 is both the periodic interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) other channel interrupts are allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) If IRQNum is set to 0 the PeriodicOnly parameter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) overidden, it is forced to a value of 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) initialization failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) Comments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) If periodic interrupts are to be disabled but AIOP interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) If interrupts are to be completely disabled set IRQNum to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) invalid combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) This function performs initialization of global interrupt modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) but it does not actually enable global interrupts. To enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) and disable global interrupts use functions sEnGlobalInt() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) sDisGlobalInt(). Enabling of global interrupts is normally not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) done until all other initializations are complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) Even if interrupts are globally enabled, they must also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) individually enabled for each channel that is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) Warnings: No range checking on any of the parameters is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) After this function all AIOPs on the controller are disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) they can be enabled with sEnAiop().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ByteIO_t * AiopIOList, int AiopIOListSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) int PeriodicOnly, int altChanRingIndicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int UPCIRingInd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ByteIO_t io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) CtlP->AltChanRingIndicator = altChanRingIndicator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) CtlP->UPCIRingInd = UPCIRingInd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) CtlP->CtlNum = CtlNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) CtlP->CtlID = CTLID_0001; /* controller release 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) CtlP->BusType = isPCI; /* controller release 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (ConfigIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) CtlP->isUPCI = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) CtlP->AiopIntrBits = upci_aiop_intr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) CtlP->isUPCI = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) CtlP->PCIIO =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) CtlP->AiopIntrBits = aiop_intr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) sPCIControllerEOI(CtlP); /* clear EOI if warm init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* Init AIOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) CtlP->NumAiop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) for (i = 0; i < AiopIOListSize; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) io = AiopIOList[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) CtlP->AiopIO[i] = (WordIO_t) io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) break; /* done looking for AIOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) sOutB(io + _INDX_DATA, sClockPrescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) CtlP->NumAiop++; /* bump count of AIOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (CtlP->NumAiop == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return (-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return (CtlP->NumAiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * Called when a PCI card is found. Retrieves and stores model information,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * init's aiopic and serial port hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * Inputs: i is the board number (0-n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static __init int register_PCI(int i, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) int num_aiops, aiop, max_num_aiops, chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) unsigned int aiopio[MAX_AIOPS_PER_BOARD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) CONTROLLER_t *ctlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) int fast_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) int altChanRingIndicator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) int ports_per_aiop = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) WordIO_t ConfigIO = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ByteIO_t UPCIRingInd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) pci_enable_device(dev) || i >= NUM_BOARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) rcktpt_io_addr[i] = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) rcktpt_type[i] = ROCKET_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) rocketModel[i].loadrm2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) rocketModel[i].startingPortNumber = nextLineNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) /* Depending on the model, set up some config variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) case PCI_DEVICE_ID_RP4QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ports_per_aiop = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) rocketModel[i].model = MODEL_RP4QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) rocketModel[i].numPorts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) case PCI_DEVICE_ID_RP8OCTA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) rocketModel[i].model = MODEL_RP8OCTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) case PCI_DEVICE_ID_URP8OCTA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) rocketModel[i].model = MODEL_UPCI_RP8OCTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) case PCI_DEVICE_ID_RP8INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) rocketModel[i].model = MODEL_RP8INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) case PCI_DEVICE_ID_URP8INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) rocketModel[i].model = MODEL_UPCI_RP8INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) case PCI_DEVICE_ID_RP8J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) rocketModel[i].model = MODEL_RP8J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) case PCI_DEVICE_ID_RP4J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ports_per_aiop = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) rocketModel[i].model = MODEL_RP4J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) rocketModel[i].numPorts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) case PCI_DEVICE_ID_RP8SNI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) rocketModel[i].model = MODEL_RP8SNI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) case PCI_DEVICE_ID_RP16SNI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) max_num_aiops = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) rocketModel[i].model = MODEL_RP16SNI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) rocketModel[i].numPorts = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) case PCI_DEVICE_ID_RP16INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) max_num_aiops = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) rocketModel[i].model = MODEL_RP16INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) rocketModel[i].numPorts = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) case PCI_DEVICE_ID_URP16INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) max_num_aiops = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) rocketModel[i].model = MODEL_UPCI_RP16INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) rocketModel[i].numPorts = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) case PCI_DEVICE_ID_CRP16INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) max_num_aiops = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) rocketModel[i].model = MODEL_CPCI_RP16INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) rocketModel[i].numPorts = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) case PCI_DEVICE_ID_RP32INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) max_num_aiops = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) rocketModel[i].model = MODEL_RP32INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) rocketModel[i].numPorts = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) case PCI_DEVICE_ID_URP32INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) max_num_aiops = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) rocketModel[i].model = MODEL_UPCI_RP32INTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) rocketModel[i].numPorts = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) case PCI_DEVICE_ID_RPP4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ports_per_aiop = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) altChanRingIndicator++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) fast_clock++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) rocketModel[i].model = MODEL_RPP4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) rocketModel[i].numPorts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) case PCI_DEVICE_ID_RPP8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) max_num_aiops = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) ports_per_aiop = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) altChanRingIndicator++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) fast_clock++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) rocketModel[i].model = MODEL_RPP8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) case PCI_DEVICE_ID_RP2_232:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ports_per_aiop = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) altChanRingIndicator++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) fast_clock++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) rocketModel[i].model = MODEL_RP2_232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) rocketModel[i].numPorts = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) case PCI_DEVICE_ID_RP2_422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ports_per_aiop = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) altChanRingIndicator++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) fast_clock++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) rocketModel[i].model = MODEL_RP2_422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) rocketModel[i].numPorts = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) case PCI_DEVICE_ID_RP6M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ports_per_aiop = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* If revision is 1, the rocketmodem flash must be loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * If it is 2 it is a "socketed" version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (dev->revision == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) rcktpt_type[i] = ROCKET_TYPE_MODEMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) rocketModel[i].loadrm2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) rcktpt_type[i] = ROCKET_TYPE_MODEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) rocketModel[i].model = MODEL_RP6M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) strcpy(rocketModel[i].modelString, "RocketModem 6 port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) rocketModel[i].numPorts = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) case PCI_DEVICE_ID_RP4M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ports_per_aiop = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (dev->revision == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) rcktpt_type[i] = ROCKET_TYPE_MODEMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) rocketModel[i].loadrm2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) rcktpt_type[i] = ROCKET_TYPE_MODEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) rocketModel[i].model = MODEL_RP4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) strcpy(rocketModel[i].modelString, "RocketModem 4 port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) rocketModel[i].numPorts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) max_num_aiops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * Check for UPCI boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) case PCI_DEVICE_ID_URP32INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) case PCI_DEVICE_ID_URP8INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) case PCI_DEVICE_ID_URP16INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) case PCI_DEVICE_ID_CRP16INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) case PCI_DEVICE_ID_URP8OCTA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) rcktpt_io_addr[i] = pci_resource_start(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ConfigIO = pci_resource_start(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * Check for octa or quad cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) PCI_GPIO_CTRL_8PORT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ports_per_aiop = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) rocketModel[i].numPorts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) case PCI_DEVICE_ID_UPCI_RM3_8PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) rocketModel[i].numPorts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) rcktpt_io_addr[i] = pci_resource_start(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ConfigIO = pci_resource_start(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) case PCI_DEVICE_ID_UPCI_RM3_4PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) max_num_aiops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) rocketModel[i].numPorts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) rcktpt_io_addr[i] = pci_resource_start(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ConfigIO = pci_resource_start(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (fast_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) sClockPrescale = 0x12; /* mod 2 (divide by 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) rp_baud_base[i] = 921600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * If support_low_speed is set, use the slow clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) * prescale, which supports 50 bps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (support_low_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /* mod 9 (divide by 10) prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) sClockPrescale = 0x19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) rp_baud_base[i] = 230400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* mod 4 (divide by 5) prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) sClockPrescale = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) rp_baud_base[i] = 460800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) for (aiop = 0; aiop < max_num_aiops; aiop++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ctlp = sCtlNumToCtlPtr(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) for (aiop = 0; aiop < max_num_aiops; aiop++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ctlp->AiopNumChan[aiop] = ports_per_aiop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) dev_info(&dev->dev, "comtrol PCI controller #%d found at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) rocketModel[i].startingPortNumber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (num_aiops <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) rcktpt_io_addr[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) is_PCI[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* Reset the AIOPIC, init the serial ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) for (aiop = 0; aiop < num_aiops; aiop++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) sResetAiopByNum(ctlp, aiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) for (chan = 0; chan < ports_per_aiop; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) init_r_port(i, aiop, chan, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Rocket modems must be reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) for (chan = 0; chan < ports_per_aiop; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) sPCIModemReset(ctlp, chan, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) for (chan = 0; chan < ports_per_aiop; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) sPCIModemReset(ctlp, chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) rmSpeakerReset(ctlp, rocketModel[i].model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * Probes for PCI cards, inits them if found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) * Input: board_found = number of ISA boards already found, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) * starting board number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) * Returns: Number of PCI boards found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static int __init init_PCI(int boards_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /* Work through the PCI device list, pulling out ours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (register_PCI(count + boards_found, dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return (count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) * Probes for ISA cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * Input: i = the board number to look for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) * Returns: 1 if board found, 0 else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static int __init init_ISA(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) int num_aiops, num_chan = 0, total_num_chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) int aiop, chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) unsigned int aiopio[MAX_AIOPS_PER_BOARD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) CONTROLLER_t *ctlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) char *type_string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* If io_addr is zero, no board configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (rcktpt_io_addr[i] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* Reserve the IO region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) printk(KERN_ERR "Unable to reserve IO region for configured "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) "ISA RocketPort at address 0x%lx, board not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) "installed...\n", rcktpt_io_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) rcktpt_io_addr[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ctlp = sCtlNumToCtlPtr(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ctlp->boardType = rcktpt_type[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) switch (rcktpt_type[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) case ROCKET_TYPE_PC104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) type_string = "(PC104)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) case ROCKET_TYPE_MODEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) type_string = "(RocketModem)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) case ROCKET_TYPE_MODEMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) type_string = "(RocketModem II)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) type_string = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) * If support_low_speed is set, use the slow clock prescale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * which supports 50 bps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (support_low_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) rp_baud_base[i] = 230400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) rp_baud_base[i] = 460800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (ctlp->boardType == ROCKET_TYPE_PC104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) sEnAiop(ctlp, 3); /* CSels used for other stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* If something went wrong initing the AIOP's release the ISA IO memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (num_aiops <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) release_region(rcktpt_io_addr[i], 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) rcktpt_io_addr[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) rocketModel[i].startingPortNumber = nextLineNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) for (aiop = 0; aiop < num_aiops; aiop++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) sResetAiopByNum(ctlp, aiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) sEnAiop(ctlp, aiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) num_chan = sGetAiopNumChan(ctlp, aiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) total_num_chan += num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) for (chan = 0; chan < num_chan; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) init_r_port(i, aiop, chan, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) is_PCI[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) num_chan = sGetAiopNumChan(ctlp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) total_num_chan = num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) for (chan = 0; chan < num_chan; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) sModemReset(ctlp, chan, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) for (chan = 0; chan < num_chan; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) sModemReset(ctlp, chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) strcpy(rocketModel[i].modelString, "RocketModem ISA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) strcpy(rocketModel[i].modelString, "RocketPort ISA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) rocketModel[i].numPorts = total_num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) rocketModel[i].model = MODEL_ISA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) i, rcktpt_io_addr[i], num_aiops, type_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) rocketModel[i].modelString,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) rocketModel[i].startingPortNumber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) rocketModel[i].startingPortNumber +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) rocketModel[i].numPorts - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static const struct tty_operations rocket_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .open = rp_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .close = rp_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .write = rp_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .put_char = rp_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .write_room = rp_write_room,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .chars_in_buffer = rp_chars_in_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .flush_buffer = rp_flush_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .ioctl = rp_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .throttle = rp_throttle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .unthrottle = rp_unthrottle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .set_termios = rp_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .stop = rp_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .start = rp_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .hangup = rp_hangup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .break_ctl = rp_break,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .send_xchar = rp_send_xchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .wait_until_sent = rp_wait_until_sent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .tiocmget = rp_tiocmget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .tiocmset = rp_tiocmset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static const struct tty_port_operations rocket_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .carrier_raised = carrier_raised,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .dtr_rts = dtr_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * The module "startup" routine; it's run when the module is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static int __init rp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ROCKET_VERSION, ROCKET_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if (!rocket_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) * If board 1 is non-zero, there is at least one ISA configured. If controller is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) * zero, use the default controller IO address of board1 + 0x40.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (board1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (controller == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) controller = board1 + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) controller = 0; /* Used as a flag, meaning no ISA boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) printk(KERN_ERR "Unable to reserve IO region for first "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) "configured ISA RocketPort controller 0x%lx. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) "Driver exiting\n", controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) goto err_tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) /* Store ISA variable retrieved from command line or .conf file. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) rcktpt_io_addr[0] = board1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) rcktpt_io_addr[1] = board2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) rcktpt_io_addr[2] = board3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) rcktpt_io_addr[3] = board4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * Set up the tty driver structure and then register this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * driver with the tty layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) rocket_driver->name = "ttyR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) rocket_driver->driver_name = "Comtrol RocketPort";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) rocket_driver->major = TTY_ROCKET_MAJOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) rocket_driver->minor_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) rocket_driver->subtype = SERIAL_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) rocket_driver->init_termios = tty_std_termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) rocket_driver->init_termios.c_cflag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) B9600 | CS8 | CREAD | HUPCL | CLOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) rocket_driver->init_termios.c_ispeed = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) rocket_driver->init_termios.c_ospeed = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) #ifdef ROCKET_SOFT_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) tty_set_operations(rocket_driver, &rocket_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ret = tty_register_driver(rocket_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) goto err_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) #ifdef ROCKET_DEBUG_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) * OK, let's probe each of the controllers looking for boards. Any boards found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) * will be initialized here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) isa_boards_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) pci_boards_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) for (i = 0; i < NUM_BOARDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) if (init_ISA(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) isa_boards_found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) if (isa_boards_found < NUM_BOARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) pci_boards_found = init_PCI(isa_boards_found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) max_board = pci_boards_found + isa_boards_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) if (max_board == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) printk(KERN_ERR "No rocketport ports found; unloading driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) goto err_ttyu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) err_ttyu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) tty_unregister_driver(rocket_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) err_controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) if (controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) release_region(controller, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) err_tty:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) put_tty_driver(rocket_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static void rp_cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) del_timer_sync(&rocket_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) retval = tty_unregister_driver(rocket_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) printk(KERN_ERR "Error %d while trying to unregister "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) "rocketport driver\n", -retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) for (i = 0; i < MAX_RP_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) if (rp_table[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) tty_unregister_device(rocket_driver, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) tty_port_destroy(&rp_table[i]->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) kfree(rp_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) put_tty_driver(rocket_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) for (i = 0; i < NUM_BOARDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) release_region(rcktpt_io_addr[i], 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) release_region(controller, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) Function: sInitController
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) Purpose: Initialization of controller global registers and controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) IRQNum,Frequency,PeriodicOnly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) int CtlNum; Controller number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) ByteIO_t MudbacIO; Mudbac base I/O address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) This list must be in the order the AIOPs will be found on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) controller. Once an AIOP in the list is not found, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) assumed that there are no more AIOPs on the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) int AiopIOListSize; Number of addresses in AiopIOList
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) int IRQNum; Interrupt Request number. Can be any of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) 0: Disable global interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) 3: IRQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) 4: IRQ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) 5: IRQ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) 9: IRQ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) 10: IRQ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) 11: IRQ 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) 12: IRQ 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) 15: IRQ 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) Byte_t Frequency: A flag identifying the frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) of the periodic interrupt, can be any one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) FREQ_DIS - periodic interrupt disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) FREQ_137HZ - 137 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) FREQ_69HZ - 69 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) FREQ_34HZ - 34 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) FREQ_17HZ - 17 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) FREQ_9HZ - 9 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) FREQ_4HZ - 4 Hertz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) If IRQNum is set to 0 the Frequency parameter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) overidden, it is forced to a value of FREQ_DIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) int PeriodicOnly: 1 if all interrupts except the periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) interrupt are to be blocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) 0 is both the periodic interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) other channel interrupts are allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) If IRQNum is set to 0 the PeriodicOnly parameter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) overidden, it is forced to a value of 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) initialization failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) Comments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) If periodic interrupts are to be disabled but AIOP interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) If interrupts are to be completely disabled set IRQNum to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) invalid combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) This function performs initialization of global interrupt modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) but it does not actually enable global interrupts. To enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) and disable global interrupts use functions sEnGlobalInt() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) sDisGlobalInt(). Enabling of global interrupts is normally not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) done until all other initializations are complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) Even if interrupts are globally enabled, they must also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) individually enabled for each channel that is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) Warnings: No range checking on any of the parameters is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) After this function all AIOPs on the controller are disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) they can be enabled with sEnAiop().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) ByteIO_t * AiopIOList, int AiopIOListSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) int IRQNum, Byte_t Frequency, int PeriodicOnly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ByteIO_t io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) CtlP->AiopIntrBits = aiop_intr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) CtlP->AltChanRingIndicator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) CtlP->CtlNum = CtlNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) CtlP->CtlID = CTLID_0001; /* controller release 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) CtlP->BusType = isISA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) CtlP->MBaseIO = MudbacIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) CtlP->MReg1IO = MudbacIO + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) CtlP->MReg2IO = MudbacIO + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) CtlP->MReg3IO = MudbacIO + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) CtlP->MReg2 = 0; /* interrupt disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) CtlP->MReg3 = 0; /* no periodic interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) CtlP->MReg2 = 0; /* interrupt disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) CtlP->MReg3 = 0; /* no periodic interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) CtlP->MReg3 = Frequency; /* set frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (PeriodicOnly) { /* periodic interrupt only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) CtlP->MReg3 |= PERIODIC_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) sOutB(CtlP->MReg2IO, CtlP->MReg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) sOutB(CtlP->MReg3IO, CtlP->MReg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) sControllerEOI(CtlP); /* clear EOI if warm init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) /* Init AIOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) CtlP->NumAiop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) for (i = done = 0; i < AiopIOListSize; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) io = AiopIOList[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) CtlP->AiopIO[i] = (WordIO_t) io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) sEnAiop(CtlP, i); /* enable the AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) done = 1; /* done looking for AIOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) sOutB(io + _INDX_DATA, sClockPrescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) CtlP->NumAiop++; /* bump count of AIOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) sDisAiop(CtlP, i); /* disable AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (CtlP->NumAiop == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return (-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) return (CtlP->NumAiop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) Function: sReadAiopID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) Purpose: Read the AIOP idenfication number directly from an AIOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) Call: sReadAiopID(io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) ByteIO_t io: AIOP base I/O address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) is replace by an identifying number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) Flag AIOPID_NULL if no valid AIOP is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) Warnings: No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static int sReadAiopID(ByteIO_t io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) Byte_t AiopID; /* ID byte from AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) sOutB(io + _CMD_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) AiopID = sInW(io + _CHN_STAT0) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) if (AiopID == 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) else /* AIOP does not exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return (-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) Function: sReadAiopNumChan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) Purpose: Read the number of channels available in an AIOP directly from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) an AIOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) Call: sReadAiopNumChan(io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) WordIO_t io: AIOP base I/O address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) Return: int: The number of channels available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) Comments: The number of channels is determined by write/reads from identical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) offsets within the SRAM address spaces for channels 0 and 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) If the channel 4 space is mirrored to channel 0 it is a 4 channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) AIOP, otherwise it is an 8 channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) Warnings: No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) static int sReadAiopNumChan(WordIO_t io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) Word_t x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) /* write to chan 0 SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) out32((DWordIO_t) io + _INDX_ADDR, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) x = sInW(io + _INDX_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) return (8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) return (4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) Function: sInitChan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) Purpose: Initialization of a channel and channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) CONTROLLER_T *CtlP; Ptr to controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) int AiopNum; AIOP number within controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) int ChanNum; Channel number within AIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) Return: int: 1 if initialization succeeded, 0 if it fails because channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) number exceeds number of channels available in AIOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) Comments: This function must be called before a channel can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) Warnings: No range checking on any of the parameters is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) int ChanNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) WordIO_t AiopIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) WordIO_t ChIOOff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) Byte_t *ChR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) Word_t ChOff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static Byte_t R[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) int brd9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (ChanNum >= CtlP->AiopNumChan[AiopNum])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return 0; /* exceeds num chans in AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* Channel, AIOP, and controller identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) ChP->CtlP = CtlP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) ChP->ChanID = CtlP->AiopID[AiopNum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) ChP->AiopNum = AiopNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) ChP->ChanNum = ChanNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* Global direct addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) AiopIO = CtlP->AiopIO[AiopNum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) ChP->IndexData = AiopIO + _INDX_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) /* Channel direct addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) ChIOOff = AiopIO + ChP->ChanNum * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) ChP->TxRxData = ChIOOff + _TD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) ChP->ChanStat = ChIOOff + _CHN_STAT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* Initialize the channel from the RData array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) for (i = 0; i < RDATASIZE; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) R[0] = RData[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) R[1] = RData[i + 1] + 0x10 * ChanNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) R[2] = RData[i + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) R[3] = RData[i + 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) out32(ChP->IndexAddr, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) ChR = ChP->R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) for (i = 0; i < RREGDATASIZE; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) ChR[i] = RRegData[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) ChR[i + 2] = RRegData[i + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) ChR[i + 3] = RRegData[i + 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) /* Indexed registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) ChOff = (Word_t) ChanNum *0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (sClockPrescale == 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) brd9600 = 47;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) brd9600 = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) ChP->BaudDiv[2] = (Byte_t) brd9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) out32(ChP->IndexAddr, ChP->BaudDiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) ChP->TxControl[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) ChP->TxControl[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) out32(ChP->IndexAddr, ChP->TxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ChP->RxControl[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) ChP->RxControl[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) out32(ChP->IndexAddr, ChP->RxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) ChP->TxEnables[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) ChP->TxEnables[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) out32(ChP->IndexAddr, ChP->TxEnables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) ChP->TxCompare[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) ChP->TxCompare[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) out32(ChP->IndexAddr, ChP->TxCompare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) ChP->TxReplace1[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) ChP->TxReplace1[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) out32(ChP->IndexAddr, ChP->TxReplace1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) ChP->TxReplace2[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) ChP->TxReplace2[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) out32(ChP->IndexAddr, ChP->TxReplace2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) ChP->TxFIFO = ChOff + _TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) sOutW(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) ChP->RxFIFO = ChOff + _RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) sOutW(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) sOutW(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ChP->TxPrioCnt = ChOff + _TXP_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) sOutB(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) ChP->TxPrioPtr = ChOff + _TXP_PNTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) sOutB(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) ChP->TxPrioBuf = ChOff + _TXP_BUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) sEnRxProcessor(ChP); /* start the Rx processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) Function: sStopRxProcessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) Purpose: Stop the receive processor from processing a channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) Call: sStopRxProcessor(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) Comments: The receive processor can be started again with sStartRxProcessor().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) This function causes the receive processor to skip over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) stopped channel. It does not stop it from processing other channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) Warnings: No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) Do not leave the receive processor stopped for more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) character time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) After calling this function a delay of 4 uS is required to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) that the receive processor is no longer processing this channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) static void sStopRxProcessor(CHANNEL_T * ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) Byte_t R[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) R[0] = ChP->R[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) R[1] = ChP->R[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) R[2] = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) R[3] = ChP->R[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) out32(ChP->IndexAddr, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) Function: sFlushRxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) Purpose: Flush the Rx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) Call: sFlushRxFIFO(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) Return: void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) while it is being flushed the receive processor is stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) and the transmitter is disabled. After these operations a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) 4 uS delay is done before clearing the pointers to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) the receive processor to stop. These items are handled inside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) Warnings: No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) static void sFlushRxFIFO(CHANNEL_T * ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) Byte_t Ch; /* channel number within AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) return; /* don't need to flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) RxFIFOEnabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) RxFIFOEnabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) sDisRxFIFO(ChP); /* disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) sInB(ChP->IntChan); /* depends on bus i/o timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) Ch = (Byte_t) sGetChanNum(ChP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) sOutW(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) sOutW(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) if (RxFIFOEnabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) sEnRxFIFO(ChP); /* enable Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) Function: sFlushTxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) Purpose: Flush the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) Call: sFlushTxFIFO(ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) Return: void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) while it is being flushed the receive processor is stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) and the transmitter is disabled. After these operations a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) 4 uS delay is done before clearing the pointers to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) the receive processor to stop. These items are handled inside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) Warnings: No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static void sFlushTxFIFO(CHANNEL_T * ChP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) Byte_t Ch; /* channel number within AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) int TxEnabled; /* 1 if transmitter enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) return; /* don't need to flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) TxEnabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) if (ChP->TxControl[3] & TX_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) TxEnabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) sDisTransmit(ChP); /* disable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) sStopRxProcessor(ChP); /* stop Rx processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) sInB(ChP->IntChan); /* depends on bus i/o timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) Ch = (Byte_t) sGetChanNum(ChP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) sOutW(ChP->IndexData, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) if (TxEnabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) sEnTransmit(ChP); /* enable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) sStartRxProcessor(ChP); /* restart Rx processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) Function: sWriteTxPrioByte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) Purpose: Write a byte of priority transmit data to a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) Call: sWriteTxPrioByte(ChP,Data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) Byte_t Data; The transmit data byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) Return: int: 1 if the bytes is successfully written, otherwise 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) Comments: The priority byte is transmitted before any data in the Tx FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) Warnings: No context switches are allowed while executing this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) Byte_t DWBuf[4]; /* buffer for double word writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) Word_t *WordPtr; /* must be far because Win SS != DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) register DWordIO_t IndexAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) IndexAddr = ChP->IndexAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) return (0); /* nothing sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) WordPtr = (Word_t *) (&DWBuf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) *WordPtr = ChP->TxPrioBuf; /* data byte address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) DWBuf[2] = Data; /* data byte value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) out32(IndexAddr, DWBuf); /* write it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) DWBuf[3] = 0; /* priority buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) out32(IndexAddr, DWBuf); /* write it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) } else { /* write it to Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) sWriteTxByte(sGetTxRxDataIO(ChP), Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) return (1); /* 1 byte sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) Function: sEnInterrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) Purpose: Enable one or more interrupts for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) Call: sEnInterrupts(ChP,Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) Word_t Flags: Interrupt enable flags, can be any combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) of the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) TXINT_EN: Interrupt on Tx FIFO empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) RXINT_EN: Interrupt on Rx FIFO at trigger level (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) sSetRxTrigger())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) SRCINT_EN: Interrupt on SRC (Special Rx Condition)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) MCINT_EN: Interrupt on modem input change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) CHANINT_EN: Allow channel interrupt signal to the AIOP's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) Interrupt Channel Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) Return: void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) Comments: If an interrupt enable flag is set in Flags, that interrupt will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) enabled. If an interrupt enable flag is not set in Flags, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) interrupt will not be changed. Interrupts can be disabled with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) function sDisInterrupts().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) This function sets the appropriate bit for the channel in the AIOP's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) Interrupt Mask Register if the CHANINT_EN flag is set. This allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) this channel's bit to be set in the AIOP's Interrupt Channel Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) Interrupts must also be globally enabled before channel interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) will be passed on to the host. This is done with function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) sEnGlobalInt().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) In some cases it may be desirable to disable interrupts globally but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) enable channel interrupts. This would allow the global interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) status register to be used to determine which AIOPs need service.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) Byte_t Mask; /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ChP->RxControl[2] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) out32(ChP->IndexAddr, ChP->RxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) out32(ChP->IndexAddr, ChP->TxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) if (Flags & CHANINT_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) sOutB(ChP->IntMask, Mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) Function: sDisInterrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) Purpose: Disable one or more interrupts for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) Call: sDisInterrupts(ChP,Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) CHANNEL_T *ChP; Ptr to channel structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) Word_t Flags: Interrupt flags, can be any combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) of the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) TXINT_EN: Interrupt on Tx FIFO empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) RXINT_EN: Interrupt on Rx FIFO at trigger level (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) sSetRxTrigger())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) SRCINT_EN: Interrupt on SRC (Special Rx Condition)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) MCINT_EN: Interrupt on modem input change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) CHANINT_EN: Disable channel interrupt signal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) AIOP's Interrupt Channel Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) Return: void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) Comments: If an interrupt flag is set in Flags, that interrupt will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) disabled. If an interrupt flag is not set in Flags, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) interrupt will not be changed. Interrupts can be enabled with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) function sEnInterrupts().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) This function clears the appropriate bit for the channel in the AIOP's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) this channel's bit from being set in the AIOP's Interrupt Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) Byte_t Mask; /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) ChP->RxControl[2] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) out32(ChP->IndexAddr, ChP->RxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) out32(ChP->IndexAddr, ChP->TxControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) if (Flags & CHANINT_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) sOutB(ChP->IntMask, Mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * Not an official SSCI function, but how to reset RocketModems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * ISA bus version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) ByteIO_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) Byte_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) addr = CtlP->AiopIO[0] + 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) val = sInB(CtlP->MReg3IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) /* if AIOP[1] is not enabled, enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) if ((val & 2) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) val = sInB(CtlP->MReg2IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) sEnAiop(CtlP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) addr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) sOutB(addr + chan, 0); /* apply or remove reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) sDisAiop(CtlP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) * Not an official SSCI function, but how to reset RocketModems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) * PCI bus version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) ByteIO_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) addr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) sOutB(addr + chan, 0); /* apply or remove reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) /* Returns the line number given the controller (board), aiop and channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) * Stores the line number associated with a given controller (board), aiop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) * and channel number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) * Returns: The line number assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) return (nextLineNumber - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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