^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written by: Ulf Jakobsson,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jan Åkerfeldt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Stefan Thomasson,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Maintained by: Paul Hardwick (p.hardwick@option.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Patches:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Locking code changes for Vodafone by Sphere Systems Ltd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Andrew Bird (ajb@spheresystems.co.uk )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * & Phil Sanderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Source has been ported from an implementation made by Filip Aben @ Option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * --------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Copyright (c) 2005,2006 Option Wireless Sweden AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (c) 2006 Sphere Systems Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Copyright (c) 2006 Option Wireless n/v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * All rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * --------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Enable this to have a lot of debug printouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/tty_driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/kmod.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VERSION_STRING DRIVER_DESC " 2.1d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Default debug printout level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NOZOMI_DEBUG_LEVEL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int debug = NOZOMI_DEBUG_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param(debug, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Macros definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DBG_(lvl, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (lvl & debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_debug("[%d] %s(): " fmt "\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __LINE__, __func__, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DBG1(args...) DBG_(0x01, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DBG2(args...) DBG_(0x02, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DBG3(args...) DBG_(0x04, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DBG4(args...) DBG_(0x08, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* TODO: rewrite to optimize macros... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TMP_BUF_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DUMP(buf__, len__) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) char tbuf[TMP_BUF_MAX] = {0}; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (len__ > 1) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 data_len = min_t(u32, len__, TMP_BUF_MAX); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) strscpy(tbuf, buf__, data_len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (tbuf[data_len - 2] == '\r') \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tbuf[data_len - 2] = 'r'; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DBG1("SENDING: '%s' (%d+n)", tbuf, len__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DBG1("SENDING: '%s' (%d)", tbuf, len__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NOZOMI_NAME "nozomi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NOZOMI_NAME_TTY "nozomi_tty"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRIVER_DESC "Nozomi driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NTTY_TTY_MAXMINORS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NTTY_FIFO_BUFFER_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Must be power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FIFO_BUFFER_SIZE_UL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Size of tmp send buffer to card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SEND_BUF_MAX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RECEIVE_BUF_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R_IIR 0x0000 /* Interrupt Identity Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R_FCR 0x0000 /* Flow Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R_IER 0x0004 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NOZOMI_CONFIG_MAGIC 0xEFEFFEFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TOGGLE_VALID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Definition of interrupt tokens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MDM_DL1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MDM_UL1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MDM_DL2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MDM_UL2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DIAG_DL1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DIAG_DL2 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DIAG_UL 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define APP1_DL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define APP1_UL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define APP2_DL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define APP2_UL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CTRL_DL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CTRL_UL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RESET 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MDM_DL (MDM_DL1 | MDM_DL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MDM_UL (MDM_UL1 | MDM_UL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DIAG_DL (DIAG_DL1 | DIAG_DL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* modem signal definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CTRL_DSR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CTRL_DCD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CTRL_RI 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CTRL_CTS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CTRL_DTR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CTRL_RTS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MAX_PORT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NOZOMI_MAX_PORTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NOZOMI_MAX_CARDS (NTTY_TTY_MAXMINORS / MAX_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Type definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * There are two types of nozomi cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * one with 2048 memory and with 8192 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum card_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Initialization states a card can be in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum card_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) NOZOMI_STATE_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) NOZOMI_STATE_ENABLED = 1, /* pci device enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) NOZOMI_STATE_ALLOCATED = 2, /* config setup done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) NOZOMI_STATE_READY = 3, /* flowcontrols received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Two different toggle channels exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum channel_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CH_A = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CH_B = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Port definition for the card regarding flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) enum ctrl_port_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CTRL_CMD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CTRL_MDM = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CTRL_DIAG = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CTRL_APP1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CTRL_APP2 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CTRL_ERROR = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Ports that the nozomi has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum port_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PORT_MDM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PORT_DIAG = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PORT_APP1 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PORT_APP2 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PORT_CTRL = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PORT_ERROR = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct toggles {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int enabled:5; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Toggle fields are valid if enabled is 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * else A-channels must always be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int diag_dl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int mdm_dl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int mdm_ul:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Configuration table to read at startup of card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Is for now only needed during initialization phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct config_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 product_information;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 pad3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct toggles toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 pad1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 dl_mdm_len1; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * If this is 64, it can hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * 60 bytes + 4 that is length field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 dl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u16 dl_diag_len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 dl_mdm_len2; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * If this is 64, it can hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 60 bytes + 4 that is length field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 dl_app1_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 dl_diag_len2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 dl_ctrl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 dl_app2_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 pad2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 ul_mdm_len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 ul_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 ul_diag_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 ul_mdm_len2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 ul_app1_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 ul_app2_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 ul_ctrl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* This stores all control downlink flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct ctrl_dl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int reserved:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int CTS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int RI:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int DCD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int DSR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* This stores all control uplink flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct ctrl_ul {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int reserved:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int RTS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int DTR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* This represents the toggle information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct toggles {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int mdm_ul:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int mdm_dl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int diag_dl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int enabled:5; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Toggle fields are valid if enabled is 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * else A-channels must always be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Configuration table to read at startup of card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct config_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u16 product_information;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct toggles toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 pad1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 dl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u16 dl_mdm_len1; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * If this is 64, it can hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * 60 bytes + 4 that is length field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u16 dl_mdm_len2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 dl_diag_len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 dl_diag_len2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u16 dl_app1_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u16 dl_app2_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u16 dl_ctrl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 pad2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u16 ul_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 ul_mdm_len2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u16 ul_mdm_len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u16 ul_diag_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 ul_app1_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u16 ul_app2_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u16 ul_ctrl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* This stores all control downlink flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ctrl_dl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int DSR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int DCD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int RI:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int CTS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int reserved:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* This stores all control uplink flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct ctrl_ul {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int DTR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int RTS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int reserved:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* This holds all information that is needed regarding a port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct tty_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 update_flow_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ctrl_ul ctrl_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct ctrl_dl ctrl_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct kfifo fifo_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void __iomem *dl_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 dl_size[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 toggle_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void __iomem *ul_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 ul_size[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 toggle_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 token_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) wait_queue_head_t tty_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct async_icount tty_icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct nozomi *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Private data one for each card in the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct nozomi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned long flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Pointers to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *reg_iir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) void __iomem *reg_fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void __iomem *reg_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u16 last_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) enum card_type card_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct config_table config_table; /* Configuration table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct port port[NOZOMI_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 *send_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spinlock_t spin_mutex; /* secures access to registers and tty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int index_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) enum card_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 open_ttys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* This is a data packet that is read or written to/from card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 size; /* size is the length of the data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Global variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct pci_device_id nozomi_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {PCI_DEVICE(0x1931, 0x000c)}, /* Nozomi HSDPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_DEVICE_TABLE(pci, nozomi_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct nozomi *ndevs[NOZOMI_MAX_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct tty_driver *ntty_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct tty_port_operations noz_tty_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * find card by tty_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static inline struct nozomi *get_dc_by_tty(const struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return tty ? ndevs[tty->index / MAX_PORT] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static inline struct port *get_port_by_tty(const struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct nozomi *ndev = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ndev ? &ndev->port[tty->index % MAX_PORT] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * -Optimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * -Rewrite cleaner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void read_mem32(u32 *buf, const void __iomem *mem_addr_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 size_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const u32 __iomem *ptr = mem_addr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u16 *buf16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (unlikely(!ptr || !buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* shortcut for extremely often used cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) switch (size_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case 2: /* 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) buf16 = (u16 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *buf16 = __le16_to_cpu(readw(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 4: /* 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *(buf) = __le32_to_cpu(readl(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) while (i < size_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (size_bytes - i == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Handle 2 bytes in the end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) buf16 = (u16 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *(buf16) = __le16_to_cpu(readw(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) i += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Read 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *(buf) = __le32_to_cpu(readl(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * -Optimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * -Rewrite cleaner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static u32 write_mem32(void __iomem *mem_addr_start, const u32 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 size_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 __iomem *ptr = mem_addr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) const u16 *buf16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (unlikely(!ptr || !buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* shortcut for extremely often used cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) switch (size_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case 2: /* 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) buf16 = (const u16 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writew(__cpu_to_le16(*buf16), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case 1: /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * also needs to write 4 bytes in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * so falling through..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 4: /* 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writel(__cpu_to_le32(*buf), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) while (i < size_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (size_bytes - i == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) buf16 = (const u16 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) writew(__cpu_to_le16(*buf16), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) writel(__cpu_to_le32(*buf), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Setup pointers to different channels and also setup buffer sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void nozomi_setup_memory(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void __iomem *offset = dc->base_addr + dc->config_table.dl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* The length reported is including the length field of 4 bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * hence subtract with 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) const u16 buff_offset = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Modem port dl configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dc->port[PORT_MDM].dl_addr[CH_A] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dc->port[PORT_MDM].dl_addr[CH_B] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) (offset += dc->config_table.dl_mdm_len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dc->port[PORT_MDM].dl_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dc->config_table.dl_mdm_len1 - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dc->port[PORT_MDM].dl_size[CH_B] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dc->config_table.dl_mdm_len2 - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Diag port dl configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dc->port[PORT_DIAG].dl_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (offset += dc->config_table.dl_mdm_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dc->port[PORT_DIAG].dl_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dc->config_table.dl_diag_len1 - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dc->port[PORT_DIAG].dl_addr[CH_B] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) (offset += dc->config_table.dl_diag_len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dc->port[PORT_DIAG].dl_size[CH_B] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dc->config_table.dl_diag_len2 - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* App1 port dl configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dc->port[PORT_APP1].dl_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (offset += dc->config_table.dl_diag_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dc->port[PORT_APP1].dl_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dc->config_table.dl_app1_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* App2 port dl configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dc->port[PORT_APP2].dl_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (offset += dc->config_table.dl_app1_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dc->port[PORT_APP2].dl_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dc->config_table.dl_app2_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Ctrl dl configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dc->port[PORT_CTRL].dl_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) (offset += dc->config_table.dl_app2_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dc->port[PORT_CTRL].dl_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dc->config_table.dl_ctrl_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) offset = dc->base_addr + dc->config_table.ul_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Modem Port ul configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dc->port[PORT_MDM].ul_addr[CH_A] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dc->port[PORT_MDM].ul_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dc->config_table.ul_mdm_len1 - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dc->port[PORT_MDM].ul_addr[CH_B] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) (offset += dc->config_table.ul_mdm_len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dc->port[PORT_MDM].ul_size[CH_B] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dc->config_table.ul_mdm_len2 - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Diag port ul configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dc->port[PORT_DIAG].ul_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) (offset += dc->config_table.ul_mdm_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dc->port[PORT_DIAG].ul_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dc->config_table.ul_diag_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* App1 port ul configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dc->port[PORT_APP1].ul_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) (offset += dc->config_table.ul_diag_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dc->port[PORT_APP1].ul_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dc->config_table.ul_app1_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* App2 port ul configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dc->port[PORT_APP2].ul_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (offset += dc->config_table.ul_app1_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dc->port[PORT_APP2].ul_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dc->config_table.ul_app2_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Ctrl ul configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dc->port[PORT_CTRL].ul_addr[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (offset += dc->config_table.ul_app2_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dc->port[PORT_CTRL].ul_size[CH_A] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dc->config_table.ul_ctrl_len - buff_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Dump config table under initalization phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void dump_table(const struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) DBG3("signature: 0x%08X", dc->config_table.signature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DBG3("version: 0x%04X", dc->config_table.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DBG3("product_information: 0x%04X", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dc->config_table.product_information);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DBG3("toggle enabled: %d", dc->config_table.toggle.enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DBG3("toggle up_mdm: %d", dc->config_table.toggle.mdm_ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DBG3("toggle dl_mdm: %d", dc->config_table.toggle.mdm_dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) DBG3("toggle dl_dbg: %d", dc->config_table.toggle.diag_dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) DBG3("dl_start: 0x%04X", dc->config_table.dl_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DBG3("dl_mdm_len0: 0x%04X, %d", dc->config_table.dl_mdm_len1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dc->config_table.dl_mdm_len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) DBG3("dl_mdm_len1: 0x%04X, %d", dc->config_table.dl_mdm_len2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dc->config_table.dl_mdm_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DBG3("dl_diag_len0: 0x%04X, %d", dc->config_table.dl_diag_len1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dc->config_table.dl_diag_len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DBG3("dl_diag_len1: 0x%04X, %d", dc->config_table.dl_diag_len2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dc->config_table.dl_diag_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) DBG3("dl_app1_len: 0x%04X, %d", dc->config_table.dl_app1_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dc->config_table.dl_app1_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DBG3("dl_app2_len: 0x%04X, %d", dc->config_table.dl_app2_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dc->config_table.dl_app2_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DBG3("dl_ctrl_len: 0x%04X, %d", dc->config_table.dl_ctrl_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dc->config_table.dl_ctrl_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) DBG3("ul_start: 0x%04X, %d", dc->config_table.ul_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dc->config_table.ul_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DBG3("ul_mdm_len[0]: 0x%04X, %d", dc->config_table.ul_mdm_len1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dc->config_table.ul_mdm_len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DBG3("ul_mdm_len[1]: 0x%04X, %d", dc->config_table.ul_mdm_len2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dc->config_table.ul_mdm_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DBG3("ul_diag_len: 0x%04X, %d", dc->config_table.ul_diag_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dc->config_table.ul_diag_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) DBG3("ul_app1_len: 0x%04X, %d", dc->config_table.ul_app1_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dc->config_table.ul_app1_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) DBG3("ul_app2_len: 0x%04X, %d", dc->config_table.ul_app2_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dc->config_table.ul_app2_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) DBG3("ul_ctrl_len: 0x%04X, %d", dc->config_table.ul_ctrl_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dc->config_table.ul_ctrl_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static inline void dump_table(const struct nozomi *dc) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Read configuration table from card under intalization phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Returns 1 if ok, else 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int nozomi_read_config_table(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) read_mem32((u32 *) &dc->config_table, dc->base_addr + 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sizeof(struct config_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (dc->config_table.signature != NOZOMI_CONFIG_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(&dc->pdev->dev, "ConfigTable Bad! 0x%08X != 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dc->config_table.signature, NOZOMI_CONFIG_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if ((dc->config_table.version == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) || (dc->config_table.toggle.enabled == TOGGLE_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) DBG1("Second phase, configuring card");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) nozomi_setup_memory(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dc->port[PORT_MDM].toggle_ul = dc->config_table.toggle.mdm_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dc->port[PORT_MDM].toggle_dl = dc->config_table.toggle.mdm_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dc->port[PORT_DIAG].toggle_dl = dc->config_table.toggle.diag_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) DBG1("toggle ports: MDM UL:%d MDM DL:%d, DIAG DL:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dc->port[PORT_MDM].toggle_ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dc->port[PORT_MDM].toggle_dl, dc->port[PORT_DIAG].toggle_dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dump_table(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = PORT_MDM; i < MAX_PORT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) memset(&dc->port[i].ctrl_dl, 0, sizeof(struct ctrl_dl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) memset(&dc->port[i].ctrl_ul, 0, sizeof(struct ctrl_ul));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Enable control channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dc->last_ier = dc->last_ier | CTRL_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dc->state = NOZOMI_STATE_ALLOCATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_info(&dc->pdev->dev, "Initialization OK!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if ((dc->config_table.version > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) && (dc->config_table.toggle.enabled != TOGGLE_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) DBG1("First phase: pushing upload buffers, clearing download");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_info(&dc->pdev->dev, "Version of card: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dc->config_table.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Here we should disable all I/O over F32. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) nozomi_setup_memory(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * We should send ALL channel pair tokens back along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * with reset token
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* push upload modem buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) write_mem32(dc->port[PORT_MDM].ul_addr[CH_A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (u32 *) &offset, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) write_mem32(dc->port[PORT_MDM].ul_addr[CH_B],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) (u32 *) &offset, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) writew(MDM_UL | DIAG_DL | MDM_DL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) DBG1("First phase done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Enable uplink interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void enable_transmit_ul(enum port_type port, struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const u16 mask[] = {MDM_UL, DIAG_UL, APP1_UL, APP2_UL, CTRL_UL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (port < NOZOMI_MAX_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dc->last_ier |= mask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(&dc->pdev->dev, "Called with wrong port?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Disable uplink interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static void disable_transmit_ul(enum port_type port, struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const u16 mask[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {~MDM_UL, ~DIAG_UL, ~APP1_UL, ~APP2_UL, ~CTRL_UL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (port < NOZOMI_MAX_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dc->last_ier &= mask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(&dc->pdev->dev, "Called with wrong port?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Enable downlink interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static void enable_transmit_dl(enum port_type port, struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const u16 mask[] = {MDM_DL, DIAG_DL, APP1_DL, APP2_DL, CTRL_DL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (port < NOZOMI_MAX_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dc->last_ier |= mask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_err(&dc->pdev->dev, "Called with wrong port?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Disable downlink interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static void disable_transmit_dl(enum port_type port, struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const u16 mask[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {~MDM_DL, ~DIAG_DL, ~APP1_DL, ~APP2_DL, ~CTRL_DL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (port < NOZOMI_MAX_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dc->last_ier &= mask[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(&dc->pdev->dev, "Called with wrong port?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Return 1 - send buffer to card and ack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * Return 0 - don't ack, don't send buffer to card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int send_data(enum port_type index, struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct port *port = &dc->port[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) const u8 toggle = port->toggle_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) void __iomem *addr = port->ul_addr[toggle];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) const u32 ul_size = port->ul_size[toggle];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Get data from tty and place in buf for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) size = kfifo_out(&port->fifo_ul, dc->send_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ul_size < SEND_BUF_MAX ? ul_size : SEND_BUF_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DBG4("No more data to send, disable link:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* DUMP(buf, size); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Write length + data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) write_mem32(addr, (u32 *) &size, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) write_mem32(addr + 4, (u32 *) dc->send_buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) tty_port_tty_wakeup(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* If all data has been read, return 1, else 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int receive_data(enum port_type index, struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u8 buf[RECEIVE_BUF_MAX] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u32 offset = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct port *port = &dc->port[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void __iomem *addr = port->dl_addr[port->toggle_dl];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct tty_struct *tty = tty_port_tty_get(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) size = __le32_to_cpu(readl(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* DBG1( "%d bytes port: %d", size, index); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (tty && tty_throttled(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DBG1("No room in tty, don't read data, don't ack interrupt, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "disable interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* disable interrupt in downlink... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) disable_transmit_dl(index, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (unlikely(size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_err(&dc->pdev->dev, "size == 0?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) read_mem32((u32 *) buf, addr + offset, RECEIVE_BUF_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) tty_insert_flip_char(&port->port, buf[0], TTY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } else if (size < RECEIVE_BUF_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) size -= tty_insert_flip_string(&port->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (char *)buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) i = tty_insert_flip_string(&port->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (char *)buf, RECEIVE_BUF_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) size -= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) offset += i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) set_bit(index, &dc->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Debug for interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static char *interrupt2str(u16 interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static char buf[TMP_BUF_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) char *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (interrupt & MDM_DL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) p += scnprintf(p, TMP_BUF_MAX, "MDM_DL1 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (interrupt & MDM_DL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "MDM_DL2 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (interrupt & MDM_UL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "MDM_UL1 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (interrupt & MDM_UL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "MDM_UL2 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (interrupt & DIAG_DL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "DIAG_DL1 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (interrupt & DIAG_DL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "DIAG_DL2 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (interrupt & DIAG_UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "DIAG_UL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (interrupt & APP1_DL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "APP1_DL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (interrupt & APP2_DL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "APP2_DL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (interrupt & APP1_UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "APP1_UL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (interrupt & APP2_UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "APP2_UL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (interrupt & CTRL_DL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "CTRL_DL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (interrupt & CTRL_UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "CTRL_UL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (interrupt & RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) p += scnprintf(p, TMP_BUF_MAX - (p - buf), "RESET ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * Receive flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * Return 1 - If ok, else 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int receive_flow_control(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) enum port_type port = PORT_MDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct ctrl_dl ctrl_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct ctrl_dl old_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u16 enable_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) read_mem32((u32 *) &ctrl_dl, dc->port[PORT_CTRL].dl_addr[CH_A], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) switch (ctrl_dl.port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case CTRL_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DBG1("The Base Band sends this value as a response to a "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "request for IMSI detach sent over the control "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "channel uplink (see section 7.6.1).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case CTRL_MDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) port = PORT_MDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) enable_ier = MDM_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case CTRL_DIAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) port = PORT_DIAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) enable_ier = DIAG_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case CTRL_APP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) port = PORT_APP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) enable_ier = APP1_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case CTRL_APP2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) port = PORT_APP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) enable_ier = APP2_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (dc->state == NOZOMI_STATE_ALLOCATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * After card initialization the flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * received for APP2 is always the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dc->state = NOZOMI_STATE_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_info(&dc->pdev->dev, "Device READY!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_err(&dc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "ERROR: flow control received for non-existing port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *((u16 *)&ctrl_dl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) old_ctrl = dc->port[port].ctrl_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dc->port[port].ctrl_dl = ctrl_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) DBG1("Disable interrupt (0x%04X) on port: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) enable_ier, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) disable_transmit_ul(port, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) } else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (kfifo_len(&dc->port[port].fifo_ul)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DBG1("Enable interrupt (0x%04X) on port: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) enable_ier, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) DBG1("Data in buffer [%d], enable transmit! ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) kfifo_len(&dc->port[port].fifo_ul));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) enable_transmit_ul(port, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) DBG1("No data in buffer...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (*(u16 *)&old_ctrl == *(u16 *)&ctrl_dl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) DBG1(" No change in mctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Update statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (old_ctrl.CTS != ctrl_dl.CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dc->port[port].tty_icount.cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (old_ctrl.DSR != ctrl_dl.DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dc->port[port].tty_icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (old_ctrl.RI != ctrl_dl.RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dc->port[port].tty_icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (old_ctrl.DCD != ctrl_dl.DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dc->port[port].tty_icount.dcd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) wake_up_interruptible(&dc->port[port].tty_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) DBG1("port: %d DCD(%d), CTS(%d), RI(%d), DSR(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dc->port[port].tty_icount.dcd, dc->port[port].tty_icount.cts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dc->port[port].tty_icount.rng, dc->port[port].tty_icount.dsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static enum ctrl_port_type port2ctrl(enum port_type port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) const struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case PORT_MDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return CTRL_MDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case PORT_DIAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return CTRL_DIAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) case PORT_APP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return CTRL_APP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) case PORT_APP2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return CTRL_APP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_err(&dc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "ERROR: send flow control " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "received for non-existing port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return CTRL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * Send flow control, can only update one channel at a time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * Return 0 - If we have updated all flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Return 1 - If we need to update more flow control, ack current enable more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int send_flow_control(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u32 i, more_flow_control_to_be_updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u16 *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for (i = PORT_MDM; i < MAX_PORT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (dc->port[i].update_flow_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (more_flow_control_to_be_updated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* We have more flow control to be updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dc->port[i].ctrl_ul.port = port2ctrl(i, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ctrl = (u16 *)&dc->port[i].ctrl_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) write_mem32(dc->port[PORT_CTRL].ul_addr[0], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) (u32 *) ctrl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) dc->port[i].update_flow_control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) more_flow_control_to_be_updated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * Handle downlink data, ports that are handled are modem and diagnostics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * Return 1 - ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Return 0 - toggle fields are out of sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int handle_data_dl(struct nozomi *dc, enum port_type port, u8 *toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) u16 read_iir, u16 mask1, u16 mask2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (*toggle == 0 && read_iir & mask1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (receive_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) writew(mask1, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) *toggle = !(*toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (read_iir & mask2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (receive_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) writew(mask2, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *toggle = !(*toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else if (*toggle == 1 && read_iir & mask2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (receive_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) writew(mask2, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) *toggle = !(*toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (read_iir & mask1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (receive_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) writew(mask1, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) *toggle = !(*toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_err(&dc->pdev->dev, "port out of sync!, toggle:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) *toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Handle uplink data, this is currently for the modem port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * Return 1 - ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * Return 0 - toggle field are out of sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int handle_data_ul(struct nozomi *dc, enum port_type port, u16 read_iir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u8 *toggle = &(dc->port[port].toggle_ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (*toggle == 0 && read_iir & MDM_UL1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dc->last_ier &= ~MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (send_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) writew(MDM_UL1, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dc->last_ier = dc->last_ier | MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) *toggle = !*toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (read_iir & MDM_UL2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dc->last_ier &= ~MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (send_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) writew(MDM_UL2, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dc->last_ier = dc->last_ier | MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) *toggle = !*toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) } else if (*toggle == 1 && read_iir & MDM_UL2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dc->last_ier &= ~MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (send_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writew(MDM_UL2, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dc->last_ier = dc->last_ier | MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) *toggle = !*toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (read_iir & MDM_UL1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dc->last_ier &= ~MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (send_data(port, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) writew(MDM_UL1, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dc->last_ier = dc->last_ier | MDM_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) *toggle = !*toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) writew(read_iir & MDM_UL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_err(&dc->pdev->dev, "port out of sync!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static irqreturn_t interrupt_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct nozomi *dc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) unsigned int a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u16 read_iir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) spin_lock(&dc->spin_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) read_iir = readw(dc->reg_iir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Card removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (read_iir == (u16)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) goto none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * Just handle interrupt enabled in IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * (by masking with dc->last_ier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) read_iir &= dc->last_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (read_iir == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) goto none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) DBG4("%s irq:0x%04X, prev:0x%04X", interrupt2str(read_iir), read_iir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dc->last_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (read_iir & RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (unlikely(!nozomi_read_config_table(dc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dc->last_ier = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_err(&dc->pdev->dev, "Could not read status from "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "card, we should disable interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) writew(RESET, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* No more useful info if this was the reset interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) goto exit_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (read_iir & CTRL_UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) DBG1("CTRL_UL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dc->last_ier &= ~CTRL_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (send_flow_control(dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) writew(CTRL_UL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dc->last_ier = dc->last_ier | CTRL_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (read_iir & CTRL_DL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) receive_flow_control(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) writew(CTRL_DL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (read_iir & MDM_DL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!handle_data_dl(dc, PORT_MDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) &(dc->port[PORT_MDM].toggle_dl), read_iir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) MDM_DL1, MDM_DL2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_err(&dc->pdev->dev, "MDM_DL out of sync!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) goto exit_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (read_iir & MDM_UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!handle_data_ul(dc, PORT_MDM, read_iir)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_err(&dc->pdev->dev, "MDM_UL out of sync!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) goto exit_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (read_iir & DIAG_DL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (!handle_data_dl(dc, PORT_DIAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) &(dc->port[PORT_DIAG].toggle_dl), read_iir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) DIAG_DL1, DIAG_DL2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dev_err(&dc->pdev->dev, "DIAG_DL out of sync!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) goto exit_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (read_iir & DIAG_UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dc->last_ier &= ~DIAG_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (send_data(PORT_DIAG, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) writew(DIAG_UL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dc->last_ier = dc->last_ier | DIAG_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (read_iir & APP1_DL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (receive_data(PORT_APP1, dc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) writew(APP1_DL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (read_iir & APP1_UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dc->last_ier &= ~APP1_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (send_data(PORT_APP1, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) writew(APP1_UL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dc->last_ier = dc->last_ier | APP1_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (read_iir & APP2_DL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (receive_data(PORT_APP2, dc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) writew(APP2_DL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (read_iir & APP2_UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dc->last_ier &= ~APP2_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (send_data(PORT_APP2, dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) writew(APP2_UL, dc->reg_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dc->last_ier = dc->last_ier | APP2_UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) exit_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) spin_unlock(&dc->spin_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) for (a = 0; a < NOZOMI_MAX_PORTS; a++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (test_and_clear_bit(a, &dc->flip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) tty_flip_buffer_push(&dc->port[a].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) none:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) spin_unlock(&dc->spin_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static void nozomi_get_card_type(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) size += pci_resource_len(dc->pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* Assume card type F32_8 if no match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dc->card_type = size == 2048 ? F32_2 : F32_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dev_info(&dc->pdev->dev, "Card type is: %d\n", dc->card_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void nozomi_setup_private_data(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) void __iomem *offset = dc->base_addr + dc->card_type / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) dc->reg_fcr = (void __iomem *)(offset + R_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dc->reg_iir = (void __iomem *)(offset + R_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dc->reg_ier = (void __iomem *)(offset + R_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dc->last_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dc->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dc->port[PORT_MDM].token_dl = MDM_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dc->port[PORT_DIAG].token_dl = DIAG_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dc->port[PORT_APP1].token_dl = APP1_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dc->port[PORT_APP2].token_dl = APP2_DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) for (i = 0; i < MAX_PORT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) init_waitqueue_head(&dc->port[i].tty_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static ssize_t card_type_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) const struct nozomi *dc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return sprintf(buf, "%d\n", dc->card_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static DEVICE_ATTR_RO(card_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static ssize_t open_ttys_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) const struct nozomi *dc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return sprintf(buf, "%u\n", dc->open_ttys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static DEVICE_ATTR_RO(open_ttys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static void make_sysfs_files(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (device_create_file(&dc->pdev->dev, &dev_attr_card_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_err(&dc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "Could not create sysfs file for card_type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (device_create_file(&dc->pdev->dev, &dev_attr_open_ttys))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_err(&dc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "Could not create sysfs file for open_ttys\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static void remove_sysfs_files(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) device_remove_file(&dc->pdev->dev, &dev_attr_card_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) device_remove_file(&dc->pdev->dev, &dev_attr_open_ttys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Allocate memory for one device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static int nozomi_card_init(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct nozomi *dc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int ndev_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_dbg(&pdev->dev, "Init, new card found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) for (ndev_idx = 0; ndev_idx < ARRAY_SIZE(ndevs); ndev_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (!ndevs[ndev_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (ndev_idx >= ARRAY_SIZE(ndevs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_err(&pdev->dev, "no free tty range for this card left\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dc = kzalloc(sizeof(struct nozomi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (unlikely(!dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dev_err(&pdev->dev, "Could not allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dc->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = pci_enable_device(dc->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(&pdev->dev, "Failed to enable PCI Device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = pci_request_regions(dc->pdev, NOZOMI_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dev_err(&pdev->dev, "I/O address 0x%04x already in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) (int) /* nozomi_private.io_addr */ 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) goto err_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* Find out what card type it is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) nozomi_get_card_type(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) dc->base_addr = pci_iomap(dc->pdev, 0, dc->card_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!dc->base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dev_err(&pdev->dev, "Unable to map card MMIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) goto err_rel_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dc->send_buf = kmalloc(SEND_BUF_MAX, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (!dc->send_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(&pdev->dev, "Could not allocate send buffer?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) goto err_free_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) for (i = PORT_MDM; i < MAX_PORT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (kfifo_alloc(&dc->port[i].fifo_ul, FIFO_BUFFER_SIZE_UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) "Could not allocate kfifo buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) goto err_free_kfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) spin_lock_init(&dc->spin_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) nozomi_setup_private_data(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dc->last_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret = request_irq(pdev->irq, &interrupt_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) NOZOMI_NAME, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dev_err(&pdev->dev, "can't request irq %d\n", pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) goto err_free_all_kfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) DBG1("base_addr: %p", dc->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) make_sysfs_files(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dc->index_start = ndev_idx * MAX_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ndevs[ndev_idx] = dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) pci_set_drvdata(pdev, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* Enable RESET interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dc->last_ier = RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) iowrite16(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dc->state = NOZOMI_STATE_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) for (i = 0; i < MAX_PORT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct device *tty_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct port *port = &dc->port[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) port->dc = dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) tty_port_init(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) port->port.ops = &noz_tty_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) tty_dev = tty_port_register_device(&port->port, ntty_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) dc->index_start + i, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (IS_ERR(tty_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = PTR_ERR(tty_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(&pdev->dev, "Could not allocate tty?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) tty_port_destroy(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) goto err_free_tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) err_free_tty:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) for (i--; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) tty_unregister_device(ntty_driver, dc->index_start + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) tty_port_destroy(&dc->port[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) free_irq(pdev->irq, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) err_free_all_kfifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) i = MAX_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) err_free_kfifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) for (i--; i >= PORT_MDM; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) kfifo_free(&dc->port[i].fifo_ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) err_free_sbuf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) kfree(dc->send_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) iounmap(dc->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) err_rel_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) err_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) kfree(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static void tty_exit(struct nozomi *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) DBG1(" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) for (i = 0; i < MAX_PORT; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) tty_port_tty_hangup(&dc->port[i].port, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Racy below - surely should wait for scheduled work to be done or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) complete off a hangup method ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) while (dc->open_ttys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) for (i = 0; i < MAX_PORT; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) tty_unregister_device(ntty_driver, dc->index_start + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) tty_port_destroy(&dc->port[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Deallocate memory for one device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static void nozomi_card_exit(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct ctrl_ul ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct nozomi *dc = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dc->last_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) tty_exit(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* Send 0x0001, command card to resend the reset token. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* This is to get the reset when the module is reloaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ctrl.port = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ctrl.reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ctrl.RTS = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ctrl.DTR = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) DBG1("sending flow control 0x%04X", *((u16 *)&ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Setup dc->reg addresses to we can use defines here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) write_mem32(dc->port[PORT_CTRL].ul_addr[0], (u32 *)&ctrl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) writew(CTRL_UL, dc->reg_fcr); /* push the token to the card. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) remove_sysfs_files(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) free_irq(pdev->irq, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) for (i = 0; i < MAX_PORT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) kfifo_free(&dc->port[i].fifo_ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) kfree(dc->send_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) iounmap(dc->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ndevs[dc->index_start / MAX_PORT] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) kfree(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static void set_rts(const struct tty_struct *tty, int rts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct port *port = get_port_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) port->ctrl_ul.RTS = rts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) port->update_flow_control = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) enable_transmit_ul(PORT_CTRL, get_dc_by_tty(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static void set_dtr(const struct tty_struct *tty, int dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct port *port = get_port_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) DBG1("SETTING DTR index: %d, dtr: %d", tty->index, dtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) port->ctrl_ul.DTR = dtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) port->update_flow_control = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) enable_transmit_ul(PORT_CTRL, get_dc_by_tty(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * TTY code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static int ntty_install(struct tty_driver *driver, struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct port *port = get_port_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (!port || !dc || dc->state != NOZOMI_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ret = tty_standard_install(driver, tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) tty->driver_data = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static void ntty_cleanup(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) tty->driver_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static int ntty_activate(struct tty_port *tport, struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct port *port = container_of(tport, struct port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct nozomi *dc = port->dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) DBG1("open: %d", port->token_dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) spin_lock_irqsave(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dc->last_ier = dc->last_ier | port->token_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) dc->open_ttys++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) spin_unlock_irqrestore(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) printk("noz: activated %d: %p\n", tty->index, tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static int ntty_open(struct tty_struct *tty, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return tty_port_open(&port->port, tty, filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static void ntty_shutdown(struct tty_port *tport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct port *port = container_of(tport, struct port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct nozomi *dc = port->dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) DBG1("close: %d", port->token_dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) spin_lock_irqsave(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dc->last_ier &= ~(port->token_dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) writew(dc->last_ier, dc->reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dc->open_ttys--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) spin_unlock_irqrestore(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) printk("noz: shutdown %p\n", tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static void ntty_close(struct tty_struct *tty, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) tty_port_close(&port->port, tty, filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static void ntty_hangup(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) tty_port_hangup(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * called when the userspace process writes to the tty (/dev/noz*).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * Data is inserted into a fifo, which is then read and transferred to the modem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static int ntty_write(struct tty_struct *tty, const unsigned char *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) int rval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* DBG1( "WRITEx: %d, index = %d", count, index); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (!dc || !port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) rval = kfifo_in(&port->fifo_ul, (unsigned char *)buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) spin_lock_irqsave(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* CTS is only valid on the modem channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (port == &(dc->port[PORT_MDM])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (port->ctrl_dl.CTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) DBG4("Enable interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) enable_transmit_ul(tty->index % MAX_PORT, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) dev_err(&dc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) "CTS not active on modem port?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) enable_transmit_ul(tty->index % MAX_PORT, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) spin_unlock_irqrestore(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * Calculate how much is left in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * This method is called by the upper tty layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * #according to sources N_TTY.c it expects a value >= 0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * does not check for negative values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * If the port is unplugged report lots of room and let the bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * dribble away so we don't block anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static int ntty_write_room(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) int room = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) const struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) room = kfifo_avail(&port->fifo_ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return room;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* Gets io control parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static int ntty_tiocmget(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) const struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) const struct ctrl_dl *ctrl_dl = &port->ctrl_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) const struct ctrl_ul *ctrl_ul = &port->ctrl_ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* Note: these could change under us but it is not clear this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) matters if so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return (ctrl_ul->RTS ? TIOCM_RTS : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) | (ctrl_ul->DTR ? TIOCM_DTR : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) | (ctrl_dl->DCD ? TIOCM_CAR : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) | (ctrl_dl->RI ? TIOCM_RNG : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) | (ctrl_dl->DSR ? TIOCM_DSR : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) | (ctrl_dl->CTS ? TIOCM_CTS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Sets io controls parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static int ntty_tiocmset(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) unsigned int set, unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) spin_lock_irqsave(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (set & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) set_rts(tty, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) else if (clear & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) set_rts(tty, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (set & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) set_dtr(tty, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) else if (clear & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) set_dtr(tty, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) spin_unlock_irqrestore(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static int ntty_cflags_changed(struct port *port, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) struct async_icount *cprev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) const struct async_icount cnow = port->tty_icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ret = ((flags & TIOCM_RNG) && (cnow.rng != cprev->rng))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) || ((flags & TIOCM_DSR) && (cnow.dsr != cprev->dsr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) || ((flags & TIOCM_CD) && (cnow.dcd != cprev->dcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) || ((flags & TIOCM_CTS) && (cnow.cts != cprev->cts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) *cprev = cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static int ntty_tiocgicount(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct serial_icounter_struct *icount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) const struct async_icount cnow = port->tty_icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) icount->cts = cnow.cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) icount->dsr = cnow.dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) icount->rng = cnow.rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) icount->dcd = cnow.dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) icount->rx = cnow.rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) icount->tx = cnow.tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) icount->frame = cnow.frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) icount->overrun = cnow.overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) icount->parity = cnow.parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) icount->brk = cnow.brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) icount->buf_overrun = cnow.buf_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static int ntty_ioctl(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) int rval = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) DBG1("******** IOCTL, cmd: %d", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) case TIOCMIWAIT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) struct async_icount cprev = port->tty_icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) rval = wait_event_interruptible(port->tty_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) ntty_cflags_changed(port, arg, &cprev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) DBG1("ERR: 0x%08X, %d", cmd, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * Called by the upper tty layer when tty buffers are ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * to receive data again after a call to throttle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static void ntty_unthrottle(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) DBG1("UNTHROTTLE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) spin_lock_irqsave(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) enable_transmit_dl(tty->index % MAX_PORT, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) set_rts(tty, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) spin_unlock_irqrestore(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * Called by the upper tty layer when the tty buffers are almost full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * The driver should stop send more data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static void ntty_throttle(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) DBG1("THROTTLE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) spin_lock_irqsave(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) set_rts(tty, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) spin_unlock_irqrestore(&dc->spin_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* Returns number of chars in buffer, called by tty layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static s32 ntty_chars_in_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct nozomi *dc = get_dc_by_tty(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) s32 rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (unlikely(!dc || !port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) goto exit_in_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) rval = kfifo_len(&port->fifo_ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) exit_in_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static const struct tty_port_operations noz_tty_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .activate = ntty_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .shutdown = ntty_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static const struct tty_operations tty_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .ioctl = ntty_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .open = ntty_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .close = ntty_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .hangup = ntty_hangup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .write = ntty_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .write_room = ntty_write_room,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .unthrottle = ntty_unthrottle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .throttle = ntty_throttle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .chars_in_buffer = ntty_chars_in_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .tiocmget = ntty_tiocmget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .tiocmset = ntty_tiocmset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .get_icount = ntty_tiocgicount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .install = ntty_install,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .cleanup = ntty_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* Module initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static struct pci_driver nozomi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .name = NOZOMI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .id_table = nozomi_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .probe = nozomi_card_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .remove = nozomi_card_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static __init int nozomi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) printk(KERN_INFO "Initializing %s\n", VERSION_STRING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ntty_driver = alloc_tty_driver(NTTY_TTY_MAXMINORS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (!ntty_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ntty_driver->driver_name = NOZOMI_NAME_TTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ntty_driver->name = "noz";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ntty_driver->major = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ntty_driver->type = TTY_DRIVER_TYPE_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ntty_driver->subtype = SERIAL_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ntty_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ntty_driver->init_termios = tty_std_termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ntty_driver->init_termios.c_cflag = B115200 | CS8 | CREAD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) HUPCL | CLOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ntty_driver->init_termios.c_ispeed = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ntty_driver->init_termios.c_ospeed = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) tty_set_operations(ntty_driver, &tty_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret = tty_register_driver(ntty_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) printk(KERN_ERR "Nozomi: failed to register ntty driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) goto free_tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ret = pci_register_driver(&nozomi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) printk(KERN_ERR "Nozomi: can't register pci driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) goto unr_tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) unr_tty:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) tty_unregister_driver(ntty_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) free_tty:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) put_tty_driver(ntty_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static __exit void nozomi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) printk(KERN_INFO "Unloading %s\n", DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) pci_unregister_driver(&nozomi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) tty_unregister_driver(ntty_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) put_tty_driver(ntty_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) module_init(nozomi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) module_exit(nozomi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) MODULE_DESCRIPTION(DRIVER_DESC);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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