^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _MXSER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _MXSER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Semi-public control interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * MOXA ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MOXA 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MOXA_GETDATACOUNT (MOXA + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MOXA_DIAGNOSE (MOXA + 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MOXA_CHKPORTENABLE (MOXA + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MOXA_HighSpeedOn (MOXA + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MOXA_GET_MAJOR (MOXA + 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MOXA_GETMSTATUS (MOXA + 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MOXA_SET_OP_MODE (MOXA + 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MOXA_GET_OP_MODE (MOXA + 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RS232_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RS485_2WIRE_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RS422_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RS485_4WIRE_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OP_MODE_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MOXA_SDS_RSTICOUNTER (MOXA + 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MOXA_ASPP_OQUEUE (MOXA + 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MOXA_ASPP_MON (MOXA + 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MOXA_ASPP_LSTATUS (MOXA + 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MOXA_ASPP_MON_EXT (MOXA + 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MOXA_SET_BAUD_METHOD (MOXA + 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* --------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NPPI_NOTIFY_PARITY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NPPI_NOTIFY_FRAMING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPPI_NOTIFY_HW_OVERRUN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NPPI_NOTIFY_SW_OVERRUN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPPI_NOTIFY_BREAK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* follow just for Moxa Must chip define. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* when LCR register (offset 0x03) write following value, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* the Must chip will enter enchance mode. And write value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* on EFR (offset 0x02) bit 6,7 to change bank. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MOXA_MUST_ENTER_ENCHANCE 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* when enhance mode enable, access on general bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MOXA_MUST_GDL_REGISTER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MOXA_MUST_GDL_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* enchance register bank select and enchance mode setting register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* when LCR register equal to 0xBF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MOXA_MUST_EFR_REGISTER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* enchance mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MOXA_MUST_EFR_EFRB_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* enchance reister bank set 0, 1, 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MOXA_MUST_EFR_BANK0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MOXA_MUST_EFR_BANK1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MOXA_MUST_EFR_BANK2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MOXA_MUST_EFR_BANK3 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MOXA_MUST_EFR_BANK_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* set XON1 value register, when LCR=0xBF and change to bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MOXA_MUST_XON1_REGISTER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* set XON2 value register, when LCR=0xBF and change to bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MOXA_MUST_XON2_REGISTER 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MOXA_MUST_XOFF1_REGISTER 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MOXA_MUST_XOFF2_REGISTER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MOXA_MUST_RBRTL_REGISTER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MOXA_MUST_RBRTH_REGISTER 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MOXA_MUST_RBRTI_REGISTER 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MOXA_MUST_THRTL_REGISTER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MOXA_MUST_ENUM_REGISTER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MOXA_MUST_HWID_REGISTER 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MOXA_MUST_ECR_REGISTER 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MOXA_MUST_CSR_REGISTER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* good data mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* only good data put into RxFIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* enable CTS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MOXA_MUST_IER_ECTSI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* enable RTS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MOXA_MUST_IER_ERTSI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* enable Xon/Xoff interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MOXA_MUST_IER_XINT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* enable GDA interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MOXA_MUST_IER_EGDAI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* GDA interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MOXA_MUST_IIR_GDA 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MOXA_MUST_IIR_RDA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MOXA_MUST_IIR_RTO 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MOXA_MUST_IIR_LSR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* received Xon/Xoff or specical interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MOXA_MUST_IIR_XSC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* RTS/CTS change state interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MOXA_MUST_IIR_RTSCTS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MOXA_MUST_IIR_MASK 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MOXA_MUST_MCR_XON_FLAG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MOXA_MUST_MCR_XON_ANY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MOXA_MUST_MCR_TX_XON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* software flow control on chip mask value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MOXA_MUST_EFR_SF_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* send Xon1/Xoff1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MOXA_MUST_EFR_SF_TX1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* send Xon2/Xoff2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MOXA_MUST_EFR_SF_TX2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* send Xon1,Xon2/Xoff1,Xoff2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MOXA_MUST_EFR_SF_TX12 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* don't send Xon/Xoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MOXA_MUST_EFR_SF_TX_NO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Tx software flow control mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MOXA_MUST_EFR_SF_TX_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* don't receive Xon/Xoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MOXA_MUST_EFR_SF_RX_NO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* receive Xon1/Xoff1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MOXA_MUST_EFR_SF_RX1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* receive Xon2/Xoff2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MOXA_MUST_EFR_SF_RX2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* receive Xon1,Xon2/Xoff1,Xoff2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MOXA_MUST_EFR_SF_RX12 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Rx software flow control mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MOXA_MUST_EFR_SF_RX_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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