^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This code is loosely based on the 1.8 moxa driver which is based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Linux serial driver, written by Linus Torvalds, Theodore T'so and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * www.moxa.com.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - Fixed x86_64 cleanness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/ratelimit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "mxser.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MXSER_VERSION "2.0.5" /* 1.14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXSERMAJOR 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MXSER_BOARDS 4 /* Max. boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MXSER_ISR_PASS_LIMIT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*CheckIsMoxaMust return value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MOXA_OTHER_UART 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MOXA_MUST_MU150_HWID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MOXA_MUST_MU860_HWID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WAKEUP_CHARS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UART_MCR_AFE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UART_LSR_SPECIAL 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_POS104UL 0x1044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_DEVICE_ID_CB108 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCI_DEVICE_ID_CP102UF 0x1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_DEVICE_ID_CP112UL 0x1120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_CB114 0x1142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_DEVICE_ID_CP114UL 0x1143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_CB134I 0x1341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_DEVICE_ID_CP138U 0x1380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define C168_ASIC_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define C104_ASIC_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define C102_ASIC_ID 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CI132_ASIC_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CI134_ASIC_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CI104J_ASIC_ID 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MXSER_HIGHBAUD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MXSER_HAS2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* This is only for PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int xmit_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int rx_high_water;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int rx_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int rx_low_water;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) long max_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } Gpci_uart_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mxser_cardinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct mxser_cardinfo mxser_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 0*/ { "C168 series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { "C104 series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { "CI-104J series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { "C168H/PCI series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { "C104H/PCI series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { "CI-132 series", 4, MXSER_HAS2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { "CI-134 series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { "CP-132 series", 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { "CP-114 series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*10*/ { "CT-114 series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { "CP-102 series", 2, MXSER_HIGHBAUD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { "CP-104U series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { "CP-168U series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { "CP-132U series", 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*15*/ { "CP-134U series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { "CP-104JU series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { "Moxa UC7000 Serial", 8, }, /* RC7000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { "CP-118U series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { "CP-102UL series", 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*20*/ { "CP-102U series", 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { "CP-118EL series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { "CP-168EL series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { "CP-104EL series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { "CB-108 series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*25*/ { "CB-114 series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { "CB-134I series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { "CP-138U series", 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { "POS-104UL series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { "CP-114UL series", 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*30*/ { "CP-102UF series", 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { "CP-112UL series", 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* driver_data correspond to the lines in the structure above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) see also ISA probe function before you change something */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct pci_device_id mxser_pcibrds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static unsigned long ioaddr[MXSER_BOARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ttymajor = MXSERMAJOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Variables for insmod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_AUTHOR("Casper Yang");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) module_param_hw_array(ioaddr, ulong, ioport, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) module_param(ttymajor, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct mxser_log {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long rxcnt[MXSER_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long txcnt[MXSER_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mxser_mon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long rxcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long up_rxcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long up_txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int modem_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned char hold_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct mxser_mon_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long rx_cnt[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long tx_cnt[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long up_rxcnt[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long up_txcnt[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int modem_status[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) long baudrate[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int databits[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int stopbits[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int parity[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int flowctrl[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int fifo[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int iftype[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct mxser_board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct mxser_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct tty_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct mxser_board *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long opmode_ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int max_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int rx_high_water;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int rx_trigger; /* Rx fifo trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int rx_low_water;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int baud_base; /* max. speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int type; /* UART type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int x_char; /* xon/xoff character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int IER; /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int MCR; /* Modem control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned char stop_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned char ldisc_stop_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int custom_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char err_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct async_icount icount; /* kernel counters for 4 input interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ignore_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int xmit_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int xmit_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int xmit_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int closing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct ktermios normal_termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mxser_mon mon_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mxser_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const struct mxser_cardinfo *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long vector_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int chip_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int uart_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct mxser_port ports[MXSER_PORTS_PER_BOARD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct mxser_mstatus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tcflag_t cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int ri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct mxser_board mxser_boards[MXSER_BOARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct tty_driver *mxvar_sdriver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct mxser_log mxvar_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int mxser_set_baud_method[MXSER_PORTS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void mxser_enable_must_enchance_mode(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) efr |= MOXA_MUST_EFR_EFRB_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void mxser_disable_must_enchance_mode(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) efr &= ~MOXA_MUST_EFR_BANK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) efr |= MOXA_MUST_EFR_BANK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) outb(value, baseio + MOXA_MUST_XON1_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) efr &= ~MOXA_MUST_EFR_BANK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) efr |= MOXA_MUST_EFR_BANK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void mxser_set_must_fifo_value(struct mxser_port *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) oldlcr = inb(info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) efr &= ~MOXA_MUST_EFR_BANK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) efr |= MOXA_MUST_EFR_BANK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) outb(oldlcr, info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) efr &= ~MOXA_MUST_EFR_BANK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) efr |= MOXA_MUST_EFR_BANK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) efr &= ~MOXA_MUST_EFR_BANK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) efr |= MOXA_MUST_EFR_BANK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) efr &= ~MOXA_MUST_EFR_SF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) efr |= MOXA_MUST_EFR_SF_TX1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) efr |= MOXA_MUST_EFR_SF_RX1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 oldlcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 efr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) oldlcr = inb(baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) outb(oldlcr, baseio + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int CheckIsMoxaMust(unsigned long io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 oldmcr, hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) outb(0, io + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mxser_disable_must_enchance_mode(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) oldmcr = inb(io + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) outb(0, io + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mxser_set_must_xon1_value(io, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if ((hwid = inb(io + UART_MCR)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) outb(oldmcr, io + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return MOXA_OTHER_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mxser_get_must_hardware_id(io, &hwid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (hwid == Gpci_uart_info[i].type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return (int)hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return MOXA_OTHER_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void process_txrx_fifo(struct mxser_port *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) info->rx_trigger = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) info->rx_high_water = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) info->rx_low_water = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) info->xmit_fifo_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for (i = 0; i < UART_INFO_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (info->board->chip_flag == Gpci_uart_info[i].type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) info->rx_trigger = Gpci_uart_info[i].rx_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) info->rx_low_water = Gpci_uart_info[i].rx_low_water;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) info->rx_high_water = Gpci_uart_info[i].rx_high_water;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static unsigned char mxser_msr[MXSER_PORTS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned char status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) status = inb(baseaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mxser_msr[port] &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mxser_msr[port] |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) status = mxser_msr[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mxser_msr[port] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int mxser_carrier_raised(struct tty_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct mxser_port *mp = container_of(port, struct mxser_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void mxser_dtr_rts(struct tty_port *port, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct mxser_port *mp = container_of(port, struct mxser_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) spin_lock_irqsave(&mp->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) outb(inb(mp->ioaddr + UART_MCR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mp->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_unlock_irqrestore(&mp->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int mxser_set_baud(struct tty_struct *tty, long newspd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int quot = 0, baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned char cval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u64 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!info->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (newspd > info->max_baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (newspd == 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) quot = 2 * info->baud_base / 269;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tty_encode_baud_rate(tty, 134, 134);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else if (newspd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) quot = info->baud_base / newspd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (quot == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) quot = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) baud = info->baud_base/quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tty_encode_baud_rate(tty, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) quot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * u64 domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) do_div(timeout, info->baud_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (quot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) info->MCR |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) info->MCR &= ~UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cval = inb(info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #ifdef BOTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (C_BAUD(tty) == BOTHER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) quot = info->baud_base % newspd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) quot *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (quot % newspd > newspd / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) quot /= newspd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) quot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) quot /= newspd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mxser_set_must_enum_value(info->ioaddr, quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mxser_set_must_enum_value(info->ioaddr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * This routine is called to set the UART divisor registers to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * the specified baud rate for a serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void mxser_change_speed(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned cflag, cval, fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cflag = tty->termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!info->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (mxser_set_baud_method[tty->index] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mxser_set_baud(tty, tty_get_baud_rate(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* byte size and parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) switch (cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) cval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) cval = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) cval = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) cval = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) cval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break; /* too keep GCC shut... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) cval |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cval |= UART_LCR_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!(cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) cval |= UART_LCR_EPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (cflag & CMSPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) cval |= UART_LCR_SPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) fcr = UART_FCR_ENABLE_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mxser_set_must_fifo_value(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) fcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) fcr = UART_FCR_ENABLE_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mxser_set_must_fifo_value(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) switch (info->rx_trigger) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fcr |= UART_FCR_TRIGGER_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) fcr |= UART_FCR_TRIGGER_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) fcr |= UART_FCR_TRIGGER_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) fcr |= UART_FCR_TRIGGER_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* CTS flow control flag and modem status interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) info->IER &= ~UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) info->MCR &= ~UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) info->IER |= UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) info->MCR |= UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) status = inb(info->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (tty->hw_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (status & UART_MSR_CTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tty->hw_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (info->type != PORT_16550A &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) !info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) outb(info->IER & ~UART_IER_THRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) info->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) outb(info->IER, info->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!(status & UART_MSR_CTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) tty->hw_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if ((info->type != PORT_16550A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) (!info->board->chip_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) info->IER &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) outb(info->IER, info->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (~cflag & CLOCAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) info->IER |= UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Set up parity check flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (I_INPCK(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (I_BRKINT(tty) || I_PARMRK(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) info->read_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) info->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (I_IGNBRK(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) info->ignore_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) info->read_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * If we're ignore parity and break indicators, ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * overruns too. (For real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (I_IGNPAR(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) info->ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) UART_LSR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) UART_LSR_PE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) UART_LSR_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) info->read_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) UART_LSR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) UART_LSR_PE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) UART_LSR_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (I_IXON(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mxser_enable_must_rx_software_flow_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mxser_disable_must_rx_software_flow_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (I_IXOFF(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mxser_enable_must_tx_software_flow_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mxser_disable_must_tx_software_flow_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) outb(cval, info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void mxser_check_modem_status(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct mxser_port *port, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* update input line counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (status & UART_MSR_TERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) port->icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (status & UART_MSR_DDSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) port->icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (status & UART_MSR_DDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) port->icount.dcd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (status & UART_MSR_DCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) port->icount.cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) port->mon_data.modem_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) wake_up_interruptible(&port->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (status & UART_MSR_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) wake_up_interruptible(&port->port.open_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (tty_port_cts_enabled(&port->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (tty->hw_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (status & UART_MSR_CTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) tty->hw_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if ((port->type != PORT_16550A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) (!port->board->chip_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) outb(port->IER & ~UART_IER_THRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) port->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) port->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) outb(port->IER, port->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!(status & UART_MSR_CTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) tty->hw_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (port->type != PORT_16550A &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) !port->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) port->IER &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) outb(port->IER, port->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct mxser_port *info = container_of(port, struct mxser_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned long page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) page = __get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!info->ioaddr || !info->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) set_bit(TTY_IO_ERROR, &tty->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) goto err_free_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) info->port.xmit_buf = (unsigned char *) page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Clear the FIFO buffers and disable them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * (they will be reenabled in mxser_change_speed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (info->board->chip_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) outb((UART_FCR_CLEAR_RCVR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) UART_FCR_CLEAR_XMIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * At this point there's no way the LSR could still be 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * if it is, then bail out, because there's likely no UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (inb(info->ioaddr + UART_LSR) == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (capable(CAP_SYS_ADMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) set_bit(TTY_IO_ERROR, &tty->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto err_free_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * Clear the interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) (void) inb(info->ioaddr + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (void) inb(info->ioaddr + UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) (void) inb(info->ioaddr + UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (void) inb(info->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * Now, initialize the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) info->MCR = UART_MCR_DTR | UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Finally, enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (info->board->chip_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) info->IER |= MOXA_MUST_IER_EGDAI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * And clear the interrupt registers again for luck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) (void) inb(info->ioaddr + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) (void) inb(info->ioaddr + UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) (void) inb(info->ioaddr + UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (void) inb(info->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) clear_bit(TTY_IO_ERROR, &tty->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * and set the speed of the serial port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mxser_change_speed(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) err_free_xmit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) free_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) info->port.xmit_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * This routine will shutdown a serial port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void mxser_shutdown_port(struct tty_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct mxser_port *info = container_of(port, struct mxser_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * here so the queue might never be waken up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) wake_up_interruptible(&info->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * Free the xmit buffer, if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (info->port.xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) free_page((unsigned long) info->port.xmit_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) info->port.xmit_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) info->IER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) outb(0x00, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* clear Rx/Tx FIFO's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (info->board->chip_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MOXA_MUST_FCR_GDA_MODE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* read data port to reset things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) (void) inb(info->ioaddr + UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (info->board->chip_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * This routine is called whenever a serial port is opened. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * enables interrupts for a serial port, linking in its async structure into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * the IRQ chain. It also performs the serial-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * initialization for the tty structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static int mxser_open(struct tty_struct *tty, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct mxser_port *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) line = tty->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (line == MXSER_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!info->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) tty->driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return tty_port_open(&info->port, tty, filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void mxser_flush_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) char fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) fcr = inb(info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) outb(fcr, info->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static void mxser_close_port(struct tty_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct mxser_port *info = container_of(port, struct mxser_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * At this point we stop accepting input. To do this, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * disable the receive line status interrupts, and tell the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * interrupt driver to stop checking the data ready bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * line status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) info->IER &= ~UART_IER_RLSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (info->board->chip_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) info->IER &= ~MOXA_MUST_RECV_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * Before we drop DTR, make sure the UART transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * has completely drained; this is especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * important if there is a transmit FIFO!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) schedule_timeout_interruptible(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * This routine is called when the serial port gets closed. First, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * wait for the last remaining data to be sent. Then, we unlink its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * async structure from the interrupt chain if necessary, and we free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * that IRQ if nothing is left in the chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static void mxser_close(struct tty_struct *tty, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct tty_port *port = &info->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (tty->index == MXSER_PORTS || info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (tty_port_close_start(port, tty, filp) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) info->closing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mutex_lock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mxser_close_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mxser_flush_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (tty_port_initialized(port) && C_HUPCL(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) tty_port_lower_dtr_rts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mxser_shutdown_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) tty_port_set_initialized(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) info->closing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* Right now the tty_port set is done outside of the close_end helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) as we don't yet have everyone using refcounts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) tty_port_close_end(port, tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) tty_port_tty_set(port, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int c, total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (!info->port.xmit_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SERIAL_XMIT_SIZE - info->xmit_head));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (c <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) info->xmit_head = (info->xmit_head + c) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) (SERIAL_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) info->xmit_cnt += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) buf += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) count -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) total += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (info->xmit_cnt && !tty->stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (!tty->hw_stopped ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) (info->type == PORT_16550A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) (info->board->chip_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) outb(info->IER & ~UART_IER_THRI, info->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!info->port.xmit_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) info->port.xmit_buf[info->xmit_head++] = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) info->xmit_head &= SERIAL_XMIT_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) info->xmit_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (!tty->stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (!tty->hw_stopped ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) (info->type == PORT_16550A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static void mxser_flush_chars(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (info->xmit_cnt <= 0 || tty->stopped || !info->port.xmit_buf ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) (tty->hw_stopped && info->type != PORT_16550A &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) !info->board->chip_flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int mxser_write_room(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret < 0 ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int mxser_chars_in_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return info->xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * ------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * friends of mxser_ioctl()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * ------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int mxser_get_serial_info(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct serial_struct *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct tty_port *port = &info->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (tty->index == MXSER_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) mutex_lock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ss->type = info->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ss->line = tty->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ss->port = info->ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ss->irq = info->board->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ss->flags = info->port.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ss->baud_base = info->baud_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ss->close_delay = info->port.close_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ss->closing_wait = info->port.closing_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ss->custom_divisor = info->custom_divisor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int mxser_set_serial_info(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct serial_struct *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct tty_port *port = &info->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) speed_t baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) unsigned long sl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (tty->index == MXSER_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (tty_io_error(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mutex_lock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!info->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (ss->irq != info->board->irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ss->port != info->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) flags = port->flags & ASYNC_SPD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!capable(CAP_SYS_ADMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if ((ss->baud_base != info->baud_base) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) (ss->close_delay != info->port.close_delay) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ((ss->flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) (ss->flags & ASYNC_USR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * OK, past this point, all the error checking has been done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * At this point, we start making changes.....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) port->flags = ((port->flags & ~ASYNC_FLAGS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) (ss->flags & ASYNC_FLAGS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) port->close_delay = ss->close_delay * HZ / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) port->closing_wait = ss->closing_wait * HZ / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) (ss->baud_base != info->baud_base ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ss->custom_divisor !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) info->custom_divisor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ss->custom_divisor == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) baud = ss->baud_base / ss->custom_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) tty_encode_baud_rate(tty, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) info->type = ss->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) process_txrx_fifo(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (tty_port_initialized(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (flags != (port->flags & ASYNC_SPD_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) spin_lock_irqsave(&info->slock, sl_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mxser_change_speed(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) spin_unlock_irqrestore(&info->slock, sl_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) retval = mxser_activate(port, tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (retval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) tty_port_set_initialized(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * mxser_get_lsr_info - get line status register info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Purpose: Let user call ioctl() to get info when the UART physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * is emptied. On bus types like RS485, the transmitter must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * release the bus after transmitting. This must be done when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * the transmit shift register is empty, not be done when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * transmit holding register is empty. This functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * allows an RS485 driver to be written in user space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static int mxser_get_lsr_info(struct mxser_port *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) unsigned int __user *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) unsigned int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) status = inb(info->ioaddr + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return put_user(result, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int mxser_tiocmget(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) unsigned char control, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (tty->index == MXSER_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (tty_io_error(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) control = info->MCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) status = inb(info->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (status & UART_MSR_ANY_DELTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) mxser_check_modem_status(tty, info, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static int mxser_tiocmset(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) unsigned int set, unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (tty->index == MXSER_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (tty_io_error(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (set & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) info->MCR |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (set & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) info->MCR |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (clear & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) info->MCR &= ~UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (clear & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) info->MCR &= ~UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int __init mxser_program_mode(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) int id, i, j, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) outb(0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) outb(0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) outb(0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) (void)inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) (void)inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) outb(0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) (void)inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) id = inb(port + 1) & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if ((id != C168_ASIC_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) (id != C104_ASIC_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) (id != C102_ASIC_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) (id != CI132_ASIC_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) (id != CI134_ASIC_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) (id != CI104J_ASIC_ID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) for (i = 0, j = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) n = inb(port + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (n == 'M') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) j = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) } else if ((j == 1) && (n == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) j = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (j != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) id = -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static void __init mxser_normal_mode(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) outb(0xA5, port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) outb(0x80, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) outb(12, port + 0); /* 9600 bps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) outb(0, port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) outb(0x03, port + 3); /* 8 data bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) outb(0x13, port + 4); /* loop back mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) n = inb(port + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if ((n & 0x61) == 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if ((n & 1) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) (void)inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) outb(0x00, port + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define CHIP_DO 0x02 /* Serial Data Output in Eprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define CHIP_DI 0x08 /* Serial Data Input in Eprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define EN_CCMD 0x000 /* Chip's command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define EN0_RSARLO 0x008 /* Remote start address reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define EN0_RSARHI 0x009 /* Remote start address reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define EN0_DCFG 0x00E /* Data configuration reg WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static int __init mxser_read_register(int port, unsigned short *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) int i, k, value, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) id = mxser_program_mode(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) for (i = 0; i < 14; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) k = (i & 0x3F) | 0x180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) for (j = 0x100; j > 0; j >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) outb(CHIP_CS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (k & j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) outb(CHIP_CS | CHIP_DO, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) outb(CHIP_CS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) (void)inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) outb(CHIP_CS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) outb(CHIP_CS | CHIP_SK, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (inb(port) & CHIP_DI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) value |= j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) regs[i] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) outb(0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) mxser_normal_mode(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct mxser_port *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct tty_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct tty_struct *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) int result, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) case MOXA_GET_MAJOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) printk_ratelimited(KERN_WARNING "mxser: '%s' uses deprecated ioctl "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) "%x (GET_MAJOR), fix your userspace\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) current->comm, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return put_user(ttymajor, (int __user *)argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) case MOXA_CHKPORTENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) for (i = 0; i < MXSER_BOARDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (mxser_boards[i].ports[j].ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) result |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return put_user(result, (unsigned long __user *)argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) case MOXA_GETDATACOUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* The receive side is locked by port->slock but it isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) clear that an exact snapshot is worth copying here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) case MOXA_GETMSTATUS: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct mxser_mstatus ms, __user *msu = argp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) for (i = 0; i < MXSER_BOARDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ip = &mxser_boards[i].ports[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) port = &ip->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) memset(&ms, 0, sizeof(ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) mutex_lock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (!ip->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) goto copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) tty = tty_port_tty_get(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (!tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ms.cflag = ip->normal_termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ms.cflag = tty->termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) spin_lock_irq(&ip->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) status = inb(ip->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) spin_unlock_irq(&ip->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (status & UART_MSR_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ms.dcd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (status & UART_MSR_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ms.dsr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (status & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ms.cts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) copy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (copy_to_user(msu, &ms, sizeof(ms)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) msu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) case MOXA_ASPP_MON_EXT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) unsigned int cflag, iflag, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) u8 opmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) me = kzalloc(sizeof(*me), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (!me)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (p >= ARRAY_SIZE(me->rx_cnt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) i = MXSER_BOARDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ip = &mxser_boards[i].ports[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) port = &ip->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) mutex_lock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (!ip->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) spin_lock_irq(&ip->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) status = mxser_get_msr(ip->ioaddr, 0, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (status & UART_MSR_TERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ip->icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (status & UART_MSR_DDSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ip->icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (status & UART_MSR_DDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ip->icount.dcd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (status & UART_MSR_DCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ip->icount.cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ip->mon_data.modem_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) me->rx_cnt[p] = ip->mon_data.rxcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) me->tx_cnt[p] = ip->mon_data.txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) me->up_rxcnt[p] = ip->mon_data.up_rxcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) me->up_txcnt[p] = ip->mon_data.up_txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) me->modem_status[p] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ip->mon_data.modem_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) spin_unlock_irq(&ip->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) tty = tty_port_tty_get(&ip->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (!tty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) cflag = ip->normal_termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) iflag = ip->normal_termios.c_iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) me->baudrate[p] = tty_termios_baud_rate(&ip->normal_termios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) cflag = tty->termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) iflag = tty->termios.c_iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) me->baudrate[p] = tty_get_baud_rate(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) me->databits[p] = cflag & CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) me->stopbits[p] = cflag & CSTOPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) me->parity[p] = cflag & (PARENB | PARODD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) CMSPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (cflag & CRTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) me->flowctrl[p] |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (iflag & (IXON | IXOFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) me->flowctrl[p] |= 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (ip->type == PORT_16550A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) me->fifo[p] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ip->board->chip_flag == MOXA_MUST_MU860_HWID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) opmode &= OP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) opmode = RS232_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) me->iftype[p] = opmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) mutex_unlock(&port->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (copy_to_user(argp, me, sizeof(*me)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) kfree(me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct async_icount *cprev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct async_icount cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) cnow = info->icount; /* atomic copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) *cprev = cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static int mxser_ioctl(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) struct async_icount cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (tty->index == MXSER_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return mxser_ioctl_special(cmd, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) unsigned long opmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) int shiftbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) unsigned char val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (info->board->chip_flag != MOXA_MUST_MU860_HWID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) p = tty->index % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (cmd == MOXA_SET_OP_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (get_user(opmode, (int __user *) argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (opmode != RS232_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) opmode != RS485_2WIRE_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) opmode != RS422_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) opmode != RS485_4WIRE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mask = ModeMask[p];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) shiftbit = p * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) spin_lock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) val = inb(info->opmode_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) val |= (opmode << shiftbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) outb(val, info->opmode_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) spin_unlock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) shiftbit = p * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) spin_lock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) opmode = inb(info->opmode_ioaddr) >> shiftbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) spin_unlock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) opmode &= OP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (put_user(opmode, (int __user *)argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (cmd != TIOCMIWAIT && tty_io_error(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) case TIOCSERGETLSR: /* Get line status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return mxser_get_lsr_info(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * - mask passed in arg for lines of interest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * Caller should use TIOCGICOUNT to see which one it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) case TIOCMIWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) cnow = info->icount; /* note the counters on entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return wait_event_interruptible(info->port.delta_msr_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) mxser_cflags_changed(info, arg, &cnow));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) case MOXA_HighSpeedOn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) case MOXA_SDS_RSTICOUNTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) spin_lock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) info->mon_data.rxcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) info->mon_data.txcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) spin_unlock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) case MOXA_ASPP_OQUEUE:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) int len, lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) len = mxser_chars_in_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) spin_lock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) spin_unlock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) len += (lsr ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return put_user(len, (int __user *)argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) case MOXA_ASPP_MON: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) int mcr, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) spin_lock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) status = mxser_get_msr(info->ioaddr, 1, tty->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) mxser_check_modem_status(tty, info, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) mcr = inb(info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) spin_unlock_irq(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (mcr & MOXA_MUST_MCR_XON_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (mcr & MOXA_MUST_MCR_TX_XON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (tty->hw_stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (copy_to_user(argp, &info->mon_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) sizeof(struct mxser_mon)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) case MOXA_ASPP_LSTATUS: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (put_user(info->err_shadow, (unsigned char __user *)argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) info->err_shadow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) case MOXA_SET_BAUD_METHOD: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) int method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (get_user(method, (int __user *)argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) mxser_set_baud_method[tty->index] = method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return put_user(method, (int __user *)argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * Return: write counters to the user passed counter struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * NB: both 1->0 and 0->1 transitions are counted except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * RI where only 0->1 is counted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static int mxser_get_icount(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct serial_icounter_struct *icount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct async_icount cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) cnow = info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) icount->frame = cnow.frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) icount->brk = cnow.brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) icount->overrun = cnow.overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) icount->buf_overrun = cnow.buf_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) icount->parity = cnow.parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) icount->rx = cnow.rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) icount->tx = cnow.tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) icount->cts = cnow.cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) icount->dsr = cnow.dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) icount->rng = cnow.rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) icount->dcd = cnow.dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void mxser_stoprx(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) info->ldisc_stop_rx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (I_IXOFF(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) info->IER &= ~MOXA_MUST_RECV_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) info->x_char = STOP_CHAR(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) outb(0, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (C_CRTSCTS(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) info->MCR &= ~UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * This routine is called by the upper-layer tty layer to signal that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) * incoming characters should be throttled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static void mxser_throttle(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) mxser_stoprx(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static void mxser_unthrottle(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* startrx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) info->ldisc_stop_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (I_IXOFF(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (info->x_char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) info->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) info->IER |= MOXA_MUST_RECV_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) info->x_char = START_CHAR(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) outb(0, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (C_CRTSCTS(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) info->MCR |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) outb(info->MCR, info->ioaddr + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * mxser_stop() and mxser_start()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * This routines are called before setting or resetting tty->stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * They enable or disable transmitter interrupts, as necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static void mxser_stop(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (info->IER & UART_IER_THRI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) info->IER &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static void mxser_start(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (info->xmit_cnt && info->port.xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) info->IER |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) outb(info->IER, info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) mxser_change_speed(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) tty->hw_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) mxser_start(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* Handle sw stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) tty->stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (info->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) mxser_disable_must_rx_software_flow_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) mxser_start(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) * mxser_wait_until_sent() --- wait until the transmitter is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) unsigned long orig_jiffies, char_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) int lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (info->type == PORT_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (info->xmit_fifo_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return; /* Just in case.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * Set the check interval to be 1/5 of the estimated time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) * send a single character, and make it at least 1. The check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) * interval should also be less than the timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * Note: we have to use pretty tight timings here to satisfy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * the NIST-PCTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) char_time = char_time / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (char_time == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) char_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (timeout && timeout < char_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) char_time = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * If the transmitter hasn't cleared in twice the approximate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * amount of time to send the entire FIFO, it probably won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * ever clear. This assumes the UART isn't doing flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * control, which is currently the case. Hence, if it ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * takes longer than info->timeout, this is probably due to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * UART bug of some kind. So, we clamp the timeout parameter at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * 2*info->timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (!timeout || timeout > 2 * info->timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) timeout = 2 * info->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) schedule_timeout_interruptible(char_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (signal_pending(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (timeout && time_after(jiffies, orig_jiffies + timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * This routine is called by tty_hangup() when a hangup is signaled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static void mxser_hangup(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) mxser_flush_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) tty_port_hangup(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * mxser_rs_break() --- routine which turns the break handling on or off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static int mxser_rs_break(struct tty_struct *tty, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) struct mxser_port *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) spin_lock_irqsave(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) info->ioaddr + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) spin_unlock_irqrestore(&info->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static void mxser_receive_chars(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct mxser_port *port, int *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) unsigned char ch, gdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) int ignored = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) int recv_room;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) int max = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) recv_room = tty->receive_room;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (recv_room == 0 && !port->ldisc_stop_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) mxser_stoprx(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (port->board->chip_flag != MOXA_OTHER_UART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (*status & UART_LSR_SPECIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) goto intr_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) (*status & MOXA_MUST_LSR_RERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) goto intr_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (*status & MOXA_MUST_LSR_RERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) goto intr_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) gdl &= MOXA_MUST_GDL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (gdl >= recv_room) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (!port->ldisc_stop_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) mxser_stoprx(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) while (gdl--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ch = inb(port->ioaddr + UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) tty_insert_flip_char(&port->port, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) goto end_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) intr_old:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (max-- < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ch = inb(port->ioaddr + UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (port->board->chip_flag && (*status & UART_LSR_OE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) outb(0x23, port->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) *status &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (*status & port->ignore_status_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (++ignored > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) char flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (*status & UART_LSR_SPECIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (*status & UART_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (port->port.flags & ASYNC_SAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) do_SAK(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) } else if (*status & UART_LSR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) } else if (*status & UART_LSR_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) } else if (*status & UART_LSR_OE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) flag = TTY_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) tty_insert_flip_char(&port->port, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (cnt >= recv_room) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (!port->ldisc_stop_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) mxser_stoprx(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (port->board->chip_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) *status = inb(port->ioaddr + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) } while (*status & UART_LSR_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) end_intr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) mxvar_log.rxcnt[tty->index] += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) port->mon_data.rxcnt += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) port->mon_data.up_rxcnt += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) * We are called from an interrupt context with &port->slock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) * being held. Drop it temporarily in order to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) * recursive locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) spin_unlock(&port->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) tty_flip_buffer_push(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) spin_lock(&port->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) int count, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) outb(port->x_char, port->ioaddr + UART_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) mxvar_log.txcnt[tty->index]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) port->mon_data.txcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) port->mon_data.up_txcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (port->port.xmit_buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (port->xmit_cnt <= 0 || tty->stopped ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) (tty->hw_stopped &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) (port->type != PORT_16550A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) (!port->board->chip_flag))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) port->IER &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) outb(port->IER, port->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) cnt = port->xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) count = port->xmit_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) outb(port->port.xmit_buf[port->xmit_tail++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) port->ioaddr + UART_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (--port->xmit_cnt <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) mxvar_log.txcnt[tty->index] += (cnt - port->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) port->mon_data.txcnt += (cnt - port->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) port->icount.tx += (cnt - port->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if (port->xmit_cnt < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (port->xmit_cnt <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) port->IER &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) outb(port->IER, port->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * This is the serial driver's generic interrupt routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static irqreturn_t mxser_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) int status, iir, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) struct mxser_board *brd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) struct mxser_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) int max, irqbits, bits, msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) unsigned int int_cnt, pass_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) int handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) struct tty_struct *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) for (i = 0; i < MXSER_BOARDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (dev_id == &mxser_boards[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) brd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (i == MXSER_BOARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) goto irq_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (brd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) goto irq_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) max = brd->info->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) irqbits = inb(brd->vector) & brd->vector_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (irqbits == brd->vector_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (irqbits == brd->vector_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) if (bits & irqbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) port = &brd->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) int_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) spin_lock(&port->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) iir = inb(port->ioaddr + UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (iir & UART_IIR_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) iir &= MOXA_MUST_IIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) tty = tty_port_tty_get(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (!tty || port->closing ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) !tty_port_initialized(&port->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) status = inb(port->ioaddr + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) outb(0x27, port->ioaddr + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) inb(port->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) status = inb(port->ioaddr + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (status & UART_LSR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) port->err_shadow |= NPPI_NOTIFY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (status & UART_LSR_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) port->err_shadow |= NPPI_NOTIFY_FRAMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (status & UART_LSR_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) port->err_shadow |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) NPPI_NOTIFY_HW_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (status & UART_LSR_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) port->err_shadow |= NPPI_NOTIFY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (port->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) if (iir == MOXA_MUST_IIR_GDA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) iir == MOXA_MUST_IIR_RDA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) iir == MOXA_MUST_IIR_RTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) iir == MOXA_MUST_IIR_LSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) mxser_receive_chars(tty, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) status &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (status & UART_LSR_DR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) mxser_receive_chars(tty, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) msr = inb(port->ioaddr + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (msr & UART_MSR_ANY_DELTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) mxser_check_modem_status(tty, port, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (port->board->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if (iir == 0x02 && (status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) UART_LSR_THRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) mxser_transmit_chars(tty, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (status & UART_LSR_THRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) mxser_transmit_chars(tty, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) spin_unlock(&port->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) irq_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static const struct tty_operations mxser_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .open = mxser_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .close = mxser_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .write = mxser_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .put_char = mxser_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .flush_chars = mxser_flush_chars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .write_room = mxser_write_room,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .chars_in_buffer = mxser_chars_in_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .flush_buffer = mxser_flush_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .ioctl = mxser_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .throttle = mxser_throttle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .unthrottle = mxser_unthrottle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .set_termios = mxser_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .stop = mxser_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .start = mxser_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .hangup = mxser_hangup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .break_ctl = mxser_rs_break,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .wait_until_sent = mxser_wait_until_sent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .tiocmget = mxser_tiocmget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .tiocmset = mxser_tiocmset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .set_serial = mxser_set_serial_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .get_serial = mxser_get_serial_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .get_icount = mxser_get_icount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static const struct tty_port_operations mxser_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .carrier_raised = mxser_carrier_raised,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .dtr_rts = mxser_dtr_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .activate = mxser_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .shutdown = mxser_shutdown_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * The MOXA Smartio/Industio serial driver boot-time initialization code!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static bool allow_overlapping_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) module_param(allow_overlapping_vector, bool, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) MODULE_PARM_DESC(allow_overlapping_vector, "whether we allow ISA cards to be configured such that vector overlabs IO ports (default=no)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static bool mxser_overlapping_vector(struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) return allow_overlapping_vector &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) brd->vector >= brd->ports[0].ioaddr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) brd->vector < brd->ports[0].ioaddr + 8 * brd->info->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static int mxser_request_vector(struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (mxser_overlapping_vector(brd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) return request_region(brd->vector, 1, "mxser(vector)") ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static void mxser_release_vector(struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) if (mxser_overlapping_vector(brd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) release_region(brd->vector, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static void mxser_release_ISA_res(struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) mxser_release_vector(brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static int mxser_initbrd(struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) struct mxser_port *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) printk(KERN_INFO "mxser: max. baud rate = %d bps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) brd->ports[0].max_baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) info = &brd->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) tty_port_init(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) info->port.ops = &mxser_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) info->board = brd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) info->stop_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) info->ldisc_stop_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /* Enhance mode enabled here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (brd->chip_flag != MOXA_OTHER_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) mxser_enable_must_enchance_mode(info->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) info->type = brd->uart_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) process_txrx_fifo(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) info->custom_divisor = info->baud_base * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) info->port.close_delay = 5 * HZ / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) info->port.closing_wait = 30 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) info->normal_termios = mxvar_sdriver->init_termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) memset(&info->mon_data, 0, sizeof(struct mxser_mon));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) info->err_shadow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) spin_lock_init(&info->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* before set INT ISR, disable all int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) outb(inb(info->ioaddr + UART_IER) & 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) info->ioaddr + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) for (i = 0; i < brd->info->nports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) tty_port_destroy(&brd->ports[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "conflict with another device.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) brd->info->name, brd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static void mxser_board_remove(struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) tty_unregister_device(mxvar_sdriver, brd->idx + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) tty_port_destroy(&brd->ports[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) free_irq(brd->irq, brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int id, i, bits, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) unsigned short regs[16], irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) unsigned char scratch, scratch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) brd->chip_flag = MOXA_OTHER_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) id = mxser_read_register(cap, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) case C168_ASIC_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) brd->info = &mxser_cards[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) case C104_ASIC_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) brd->info = &mxser_cards[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) case CI104J_ASIC_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) brd->info = &mxser_cards[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) case C102_ASIC_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) brd->info = &mxser_cards[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) case CI132_ASIC_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) brd->info = &mxser_cards[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) case CI134_ASIC_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) brd->info = &mxser_cards[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) Flag-hack checks if configuration should be read as 2-port here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) irq = regs[9] & 0xF000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) irq = irq | (irq >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if (irq != (regs[9] & 0xFF00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) goto err_irqconflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) } else if (brd->info->nports == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) irq = regs[9] & 0xF000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) irq = irq | (irq >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) irq = irq | (irq >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (irq != regs[9])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) goto err_irqconflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) } else if (brd->info->nports == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) irq = regs[9] & 0xF000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) irq = irq | (irq >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) irq = irq | (irq >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if ((irq != regs[9]) || (irq != regs[10]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) goto err_irqconflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) printk(KERN_ERR "mxser: interrupt number unset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) brd->irq = ((int)(irq & 0xF000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) if ((regs[12] & 0x80) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) printk(KERN_ERR "mxser: invalid interrupt vector\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) brd->vector = (int)regs[11]; /* interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) if (id == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) brd->vector_mask = 0x00FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) brd->vector_mask = 0x000F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (regs[12] & bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) brd->ports[i].baud_base = 921600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) brd->ports[i].max_baud = 921600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) brd->ports[i].baud_base = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) brd->ports[i].max_baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) outb(0, cap + UART_EFR); /* EFR is the same as FCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) outb(scratch2, cap + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) scratch = inb(cap + UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (scratch & 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) brd->uart_type = PORT_16550A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) brd->uart_type = PORT_16450;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) "mxser(IO)")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) printk(KERN_ERR "mxser: can't request ports I/O region: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) "0x%.8lx-0x%.8lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) brd->ports[0].ioaddr, brd->ports[0].ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) 8 * brd->info->nports - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ret = mxser_request_vector(brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) printk(KERN_ERR "mxser: can't request interrupt vector region: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) "0x%.8lx-0x%.8lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) brd->ports[0].ioaddr, brd->ports[0].ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) 8 * brd->info->nports - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) return brd->info->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) err_irqconflict:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) printk(KERN_ERR "mxser: invalid interrupt number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) static int mxser_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct mxser_board *brd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) unsigned long ioaddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) struct device *tty_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) int retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) for (i = 0; i < MXSER_BOARDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if (mxser_boards[i].info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (i >= MXSER_BOARDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) dev_err(&pdev->dev, "too many boards found (maximum %d), board "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) "not configured\n", MXSER_BOARDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) brd = &mxser_boards[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) brd->idx = i * MXSER_PORTS_PER_BOARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) mxser_cards[ent->driver_data].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) pdev->bus->number, PCI_SLOT(pdev->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) retval = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) dev_err(&pdev->dev, "PCI enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) /* io address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) ioaddress = pci_resource_start(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) retval = pci_request_region(pdev, 2, "mxser(IO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) goto err_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) brd->info = &mxser_cards[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) for (i = 0; i < brd->info->nports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) brd->ports[i].ioaddr = ioaddress + 8 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) /* vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) ioaddress = pci_resource_start(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) retval = pci_request_region(pdev, 3, "mxser(vector)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) goto err_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) brd->vector = ioaddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) brd->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) brd->uart_type = PORT_16550A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) brd->vector_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) for (j = 0; j < UART_INFO_NUM; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (Gpci_uart_info[j].type == brd->chip_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) brd->ports[i].max_baud =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) Gpci_uart_info[j].max_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) /* exception....CP-102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (brd->info->flags & MXSER_HIGHBAUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) brd->ports[i].max_baud = 921600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) brd->ports[i].opmode_ioaddr = ioaddress + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) outb(0, ioaddress + 4); /* default set to RS232 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) brd->vector_mask |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) brd->ports[i].baud_base = 921600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) /* mxser_initbrd will hook ISR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) retval = mxser_initbrd(brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) goto err_rel3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) tty_dev = tty_port_register_device(&brd->ports[i].port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) mxvar_sdriver, brd->idx + i, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) if (IS_ERR(tty_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) retval = PTR_ERR(tty_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) tty_unregister_device(mxvar_sdriver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) brd->idx + i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) goto err_relbrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) pci_set_drvdata(pdev, brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) err_relbrd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) for (i = 0; i < brd->info->nports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) tty_port_destroy(&brd->ports[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) free_irq(brd->irq, brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) err_rel3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) pci_release_region(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) err_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) brd->info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) pci_release_region(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) err_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static void mxser_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) struct mxser_board *brd = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) mxser_board_remove(brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) pci_release_region(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) pci_release_region(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) brd->info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static struct pci_driver mxser_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .name = "mxser",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .id_table = mxser_pcibrds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .probe = mxser_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .remove = mxser_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static int __init mxser_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) struct mxser_board *brd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) struct device *tty_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) unsigned int b, i, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (!mxvar_sdriver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) MXSER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) /* Initialize the tty_driver structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) mxvar_sdriver->name = "ttyMI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) mxvar_sdriver->major = ttymajor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) mxvar_sdriver->minor_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) mxvar_sdriver->init_termios = tty_std_termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) tty_set_operations(mxvar_sdriver, &mxser_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) retval = tty_register_driver(mxvar_sdriver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) "tty driver !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) goto err_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) /* Start finding ISA boards here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) for (m = 0, b = 0; b < MXSER_BOARDS; b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) if (!ioaddr[b])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) brd = &mxser_boards[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) retval = mxser_get_ISA_conf(ioaddr[b], brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (retval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) brd->info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) printk(KERN_INFO "mxser: found MOXA %s board (CAP=0x%lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) brd->info->name, ioaddr[b]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) /* mxser_initbrd will hook ISR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (mxser_initbrd(brd) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) mxser_release_ISA_res(brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) brd->info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) brd->idx = m * MXSER_PORTS_PER_BOARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) for (i = 0; i < brd->info->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) tty_dev = tty_port_register_device(&brd->ports[i].port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) mxvar_sdriver, brd->idx + i, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) if (IS_ERR(tty_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) tty_unregister_device(mxvar_sdriver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) brd->idx + i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) for (i = 0; i < brd->info->nports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) tty_port_destroy(&brd->ports[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) free_irq(brd->irq, brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) mxser_release_ISA_res(brd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) brd->info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) if (brd->info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) m++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) retval = pci_register_driver(&mxser_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) printk(KERN_ERR "mxser: can't register pci driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (!m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) goto err_unr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) } /* else: we have some ISA cards under control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) err_unr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) tty_unregister_driver(mxvar_sdriver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) err_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) put_tty_driver(mxvar_sdriver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) static void __exit mxser_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) pci_unregister_driver(&mxser_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) if (mxser_boards[i].info != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) mxser_board_remove(&mxser_boards[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) tty_unregister_driver(mxvar_sdriver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) put_tty_driver(mxvar_sdriver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) for (i = 0; i < MXSER_BOARDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (mxser_boards[i].info != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) mxser_release_ISA_res(&mxser_boards[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) module_init(mxser_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) module_exit(mxser_module_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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