Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef MOXA_H_FILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define MOXA_H_FILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define	MOXA		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define MOXA_GET_IQUEUE 	(MOXA + 1)	/* get input buffered count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define MOXA_GET_OQUEUE 	(MOXA + 2)	/* get output buffered count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define MOXA_GETDATACOUNT       (MOXA + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define MOXA_GET_IOQUEUE	(MOXA + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define MOXA_FLUSH_QUEUE	(MOXA + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MOXA_GETMSTATUS         (MOXA + 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *    System Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define Magic_code	0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *    for C218 BIOS initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define C218_ConfBase	0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define C218_status	(C218_ConfBase + 0)	/* BIOS running status    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define C218_diag	(C218_ConfBase + 2)	/* diagnostic status      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define C218_key	(C218_ConfBase + 4)	/* WORD (0x218 for C218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define C218DLoad_len	(C218_ConfBase + 6)	/* WORD           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define C218check_sum	(C218_ConfBase + 8)	/* BYTE           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define C218chksum_ok	(C218_ConfBase + 0x0a)	/* BYTE (1:ok)            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define C218_TestRx	(C218_ConfBase + 0x10)	/* 8 bytes for 8 ports    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define C218_TestTx	(C218_ConfBase + 0x18)	/* 8 bytes for 8 ports    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define C218_RXerr	(C218_ConfBase + 0x20)	/* 8 bytes for 8 ports    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define C218_ErrFlag	(C218_ConfBase + 0x28)	/* 8 bytes for 8 ports    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define C218_LoadBuf	0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define C218_KeyCode	0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CP204J_KeyCode	0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *    for C320 BIOS initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define C320_ConfBase	0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define C320_LoadBuf	0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define STS_init	0x05	/* for C320_status        */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define C320_status	C320_ConfBase + 0	/* BIOS running status    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define C320_diag	C320_ConfBase + 2	/* diagnostic status      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define C320_key	C320_ConfBase + 4	/* WORD (0320H for C320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define C320DLoad_len	C320_ConfBase + 6	/* WORD           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define C320check_sum	C320_ConfBase + 8	/* WORD           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define C320chksum_ok	C320_ConfBase + 0x0a	/* WORD (1:ok)            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define C320bapi_len	C320_ConfBase + 0x0c	/* WORD           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define C320UART_no	C320_ConfBase + 0x0e	/* WORD           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define C320_KeyCode	0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define FixPage_addr	0x0000	/* starting addr of static page  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DynPage_addr	0x2000	/* starting addr of dynamic page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define C218_start	0x3000	/* starting addr of C218 BIOS prg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define Control_reg	0x1ff0	/* select page and reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HW_reset	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *    Function Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define FC_CardReset	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define FC_ChannelReset 1	/* C320 firmware not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define FC_EnableCH	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define FC_DisableCH	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define FC_SetParam	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define FC_SetMode	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define FC_SetRate	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define FC_LineControl	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define FC_LineStatus	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define FC_XmitControl	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define FC_FlushQueue	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define FC_SendBreak	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define FC_StopBreak	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define FC_LoopbackON	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define FC_LoopbackOFF	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define FC_ClrIrqTable	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define FC_SendXon	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define FC_SetTermIrq	17	/* C320 firmware not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define FC_SetCntIrq	18	/* C320 firmware not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define FC_SetBreakIrq	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define FC_SetLineIrq	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define FC_SetFlowCtl	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define FC_GenIrq	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define FC_InCD180	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define FC_OutCD180	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define FC_InUARTreg	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define FC_OutUARTreg	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define FC_SetXonXoff	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define FC_OutCD180CCR	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define FC_ExtIQueue	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define FC_ExtOQueue	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define FC_ClrLineIrq	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define FC_HWFlowCtl	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define FC_GetClockRate 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define FC_SetBaud	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FC_SetDataMode  41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FC_GetCCSR      43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FC_GetDataError 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FC_RxControl	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FC_ImmSend	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FC_SetXonState	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FC_SetXoffState	53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FC_SetRxFIFOTrig 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FC_SetTxFIFOCnt 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FC_UnixRate	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FC_UnixResetTimer 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define	RxFIFOTrig1	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define	RxFIFOTrig4	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define	RxFIFOTrig8	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define	RxFIFOTrig14	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *    Dual-Ported RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRAM_global	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INT_data	(DRAM_global + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define Config_base	(DRAM_global + 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IRQindex	(INT_data + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IRQpending	(INT_data + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IRQtable	(INT_data + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *    Interrupt Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IntrRx		0x01	/* receiver data O.K.             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IntrTx		0x02	/* transmit buffer empty  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IntrFunc	0x04	/* function complete              */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IntrBreak	0x08	/* received break         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IntrLine	0x10	/* line status change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				   for transmitter                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IntrIntr	0x20	/* received INTR code             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IntrQuit	0x40	/* received QUIT code             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IntrEOF 	0x80	/* received EOF code              */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IntrRxTrigger 	0x100	/* rx data count reach trigger value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IntrTxTrigger 	0x200	/* tx data count below trigger value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define Magic_no	(Config_base + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define Card_model_no	(Config_base + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define Total_ports	(Config_base + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define Module_cnt	(Config_base + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define Module_no	(Config_base + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define Timer_10ms	(Config_base + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define Disable_IRQ	(Config_base + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TMS320_PORT1	(Config_base + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TMS320_PORT2	(Config_base + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TMS320_CLOCK	(Config_base + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *    DATA BUFFER in DRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define Extern_table	0x400	/* Base address of the external table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				   (24 words *    64) total 3K bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				   (24 words * 128) total 6K bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define Extern_size	0x60	/* 96 bytes                       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RXrptr		0x00	/* read pointer for RX buffer     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RXwptr		0x02	/* write pointer for RX buffer    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TXrptr		0x04	/* read pointer for TX buffer     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TXwptr		0x06	/* write pointer for TX buffer    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HostStat	0x08	/* IRQ flag and general flag      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FlagStat	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FlowControl	0x0C	/* B7 B6 B5 B4 B3 B2 B1 B0              */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				/*  x  x  x  x  |  |  |  |            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				/*              |  |  |  + CTS flow   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				/*              |  |  +--- RTS flow   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				/*              |  +------ TX Xon/Xoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				/*              +--------- RX Xon/Xoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define Break_cnt	0x0E	/* received break count   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CD180TXirq	0x10	/* if non-0: enable TX irq        */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RX_mask 	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TX_mask 	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define Ofs_rxb 	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define Ofs_txb 	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define Page_rxb	0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define Page_txb	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EndPage_rxb	0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EndPage_txb	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define Data_error	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RxTrigger	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TxTrigger	0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define rRXwptr 	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define Low_water	0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FuncCode	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FuncArg 	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FuncArg1	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define C218rx_size	0x2000	/* 8K bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define C218tx_size	0x8000	/* 32K bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define C218rx_mask	(C218rx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define C218tx_mask	(C218tx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define C320p8rx_size	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define C320p8tx_size	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define C320p8rx_mask	(C320p8rx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define C320p8tx_mask	(C320p8tx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define C320p16rx_size	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define C320p16tx_size	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define C320p16rx_mask	(C320p16rx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define C320p16tx_mask	(C320p16tx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define C320p24rx_size	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define C320p24tx_size	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define C320p24rx_mask	(C320p24rx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define C320p24tx_mask	(C320p24tx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define C320p32rx_size	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define C320p32tx_size	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define C320p32rx_mask	(C320p32rx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define C320p32tx_mask	(C320p32tx_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define Page_size	0x2000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define Page_mask	(Page_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define C218rx_spage	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define C218tx_spage	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define C218rx_pageno	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define C218tx_pageno	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define C218buf_pageno	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define C320p8rx_spage	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define C320p8tx_spage	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define C320p8rx_pgno	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define C320p8tx_pgno	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define C320p8buf_pgno	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define C320p16rx_spage 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define C320p16tx_spage 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define C320p16rx_pgno	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define C320p16tx_pgno	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define C320p16buf_pgno 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define C320p24rx_spage 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define C320p24tx_spage 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define C320p24rx_pgno	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define C320p24tx_pgno	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define C320p24buf_pgno 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define C320p32rx_spage 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define C320p32tx_ofs	C320p32rx_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define C320p32tx_spage 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define C320p32buf_pgno 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  *    Host Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define WakeupRx	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define WakeupTx	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define WakeupBreak	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define WakeupLine	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define WakeupIntr	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define WakeupQuit	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define WakeupEOF	0x80	/* used in VTIME control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define WakeupRxTrigger	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define WakeupTxTrigger	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  *    Flag status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define Rx_over		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define Xoff_state	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define Tx_flowOff	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define Tx_enable	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CTS_state	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DSR_state	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DCD_state	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  *    FlowControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CTS_FlowCtl	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RTS_FlowCtl	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define Tx_FlowCtl	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define Rx_FlowCtl	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IXM_IXANY	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LowWater	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DTR_ON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define RTS_ON		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CTS_ON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DSR_ON		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DCD_ON		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* mode definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define	MX_CS8		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define	MX_CS7		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define	MX_CS6		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define	MX_CS5		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define	MX_STOP1	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define	MX_STOP15	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define	MX_STOP2	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define	MX_PARNONE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define	MX_PAREVEN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define	MX_PARODD	0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define	MX_PARMARK	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define	MX_PARSPACE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif