Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/dcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "hvc_console.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Disable DCC driver at runtime. Want driver enabled for GKI, but some devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * do not support the registers and crash when driver pokes the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) module_param(enable, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* DCC Status Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DCC_STATUS_RX		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DCC_STATUS_TX		(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void dcc_uart_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	while (__dcc_getstatus() & DCC_STATUS_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	__dcc_putchar(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static void dcc_early_write(struct console *con, const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	uart_console_write(&dev->port, s, n, dcc_uart_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int __init dcc_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 					  const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	device->con->write = dcc_early_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) EARLYCON_DECLARE(dcc, dcc_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		while (__dcc_getstatus() & DCC_STATUS_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		__dcc_putchar(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	for (i = 0; i < count; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		if (__dcc_getstatus() & DCC_STATUS_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			buf[i] = __dcc_getchar();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * Check if the DCC is enabled.  If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * then we assume then this function will be called first on core 0.  That
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * way, dcc_core0_available will be true only if it's available on core 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static bool hvc_dcc_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned long time = jiffies + (HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	static bool dcc_core0_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * If we're not on core 0, but we previously confirmed that DCC is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * active, then just return true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (smp_processor_id() && dcc_core0_available)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Write a test character to check if it is handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	__dcc_putchar('\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	while (time_is_after_jiffies(time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (!(__dcc_getstatus() & DCC_STATUS_TX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			dcc_core0_available = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void dcc_put_work_fn(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void dcc_get_work_fn(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static DECLARE_WORK(dcc_pwork, dcc_put_work_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static DECLARE_WORK(dcc_gwork, dcc_get_work_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static DEFINE_SPINLOCK(dcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static DEFINE_KFIFO(inbuf, unsigned char, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static DEFINE_KFIFO(outbuf, unsigned char, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * Workqueue function that writes the output FIFO to the DCC on core 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void dcc_put_work_fn(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned char ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	spin_lock_irqsave(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* While there's data in the output FIFO, write it to the DCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	while (kfifo_get(&outbuf, &ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		hvc_dcc_put_chars(0, &ch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* While we're at it, check for any input characters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	while (!kfifo_is_full(&inbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (!hvc_dcc_get_chars(0, &ch, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		kfifo_put(&inbuf, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	spin_unlock_irqrestore(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * Workqueue function that reads characters from DCC and puts them into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * input FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void dcc_get_work_fn(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned char ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * Read characters from DCC and put them into the input FIFO, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * long as there is room and we have characters to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	spin_lock_irqsave(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	while (!kfifo_is_full(&inbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (!hvc_dcc_get_chars(0, &ch, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		kfifo_put(&inbuf, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	spin_unlock_irqrestore(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * Write characters directly to the DCC if we're on core 0 and the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * is empty, or write them to the FIFO if we're not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int hvc_dcc0_put_chars(uint32_t vt, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					     int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	spin_lock_irqsave(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (smp_processor_id() || (!kfifo_is_empty(&outbuf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		len = kfifo_in(&outbuf, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		spin_unlock_irqrestore(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		 * We just push data to the output FIFO, so schedule the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		 * workqueue that will actually write that data to DCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		schedule_work_on(0, &dcc_pwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * If we're already on core 0, and the FIFO is empty, then just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * write the data to DCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	len = hvc_dcc_put_chars(vt, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	spin_unlock_irqrestore(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * Read characters directly from the DCC if we're on core 0 and the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * is empty, or read them from the FIFO if we're not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int hvc_dcc0_get_chars(uint32_t vt, char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	spin_lock_irqsave(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (smp_processor_id() || (!kfifo_is_empty(&inbuf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		len = kfifo_out(&inbuf, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		spin_unlock_irqrestore(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		 * If the FIFO was empty, there may be characters in the DCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		 * that we haven't read yet.  Schedule a workqueue to fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		 * the input FIFO, so that the next time this function is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		 * called, we'll have data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			schedule_work_on(0, &dcc_gwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * If we're already on core 0, and the FIFO is empty, then just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * read the data from DCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	len = hvc_dcc_get_chars(vt, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	spin_unlock_irqrestore(&dcc_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct hv_ops hvc_dcc_get_put_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.get_chars = hvc_dcc0_get_chars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.put_chars = hvc_dcc0_put_chars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct hv_ops hvc_dcc_get_put_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.get_chars = hvc_dcc_get_chars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.put_chars = hvc_dcc_put_chars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int __init hvc_dcc_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (!enable || !hvc_dcc_check())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Returns -1 if error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ret = hvc_instantiate(0, 0, &hvc_dcc_get_put_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return ret < 0 ? -ENODEV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) console_initcall(hvc_dcc_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int __init hvc_dcc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct hvc_struct *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (!enable || !hvc_dcc_check())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	p = hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return PTR_ERR_OR_ZERO(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) device_initcall(hvc_dcc_init);