Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Thunderbolt Time Management Unit (TMU) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	    Rajmohan Mani <rajmohan.mani@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "tb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static const char *tb_switch_tmu_mode_name(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	bool root_switch = !tb_route(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	switch (sw->tmu.rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	case TB_SWITCH_TMU_RATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		return "off";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	case TB_SWITCH_TMU_RATE_HIFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		/* Root switch does not have upstream directionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		if (root_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			return "HiFi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		if (sw->tmu.unidirectional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			return "uni-directional, HiFi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		return "bi-directional, HiFi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	case TB_SWITCH_TMU_RATE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		if (root_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			return "normal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		return "uni-directional, normal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static bool tb_switch_tmu_ucap_supported(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			 sw->tmu.cap + TMU_RTR_CS_0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return !!(val & TMU_RTR_CS_0_UCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int tb_switch_tmu_rate_read(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			 sw->tmu.cap + TMU_RTR_CS_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	val >>= TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int tb_switch_tmu_rate_write(struct tb_switch *sw, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			 sw->tmu.cap + TMU_RTR_CS_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	val &= ~TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	val |= rate << TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return tb_sw_write(sw, &val, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			   sw->tmu.cap + TMU_RTR_CS_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int tb_port_tmu_write(struct tb_port *port, u8 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			     u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	data |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return tb_port_write(port, &data, TB_CFG_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			     port->cap_tmu + offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int tb_port_tmu_set_unidirectional(struct tb_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					  bool unidirectional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!port->sw->tmu.has_ucap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	val = unidirectional ? TMU_ADP_CS_3_UDM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return tb_port_tmu_write(port, TMU_ADP_CS_3, TMU_ADP_CS_3_UDM, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline int tb_port_tmu_unidirectional_disable(struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return tb_port_tmu_set_unidirectional(port, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static bool tb_port_tmu_is_unidirectional(struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ret = tb_port_read(port, &val, TB_CFG_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			   port->cap_tmu + TMU_ADP_CS_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return val & TMU_ADP_CS_3_UDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int tb_switch_tmu_set_time_disruption(struct tb_switch *sw, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			 sw->tmu.cap + TMU_RTR_CS_0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		val |= TMU_RTR_CS_0_TD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		val &= ~TMU_RTR_CS_0_TD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return tb_sw_write(sw, &val, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			   sw->tmu.cap + TMU_RTR_CS_0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * tb_switch_tmu_init() - Initialize switch TMU structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * @sw: Switch to initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * This function must be called before other TMU related functions to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * makes the internal structures are filled in correctly. Does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * change any hardware configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int tb_switch_tmu_init(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct tb_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (tb_switch_is_icm(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret = tb_switch_find_cap(sw, TB_SWITCH_CAP_TMU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		sw->tmu.cap = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	tb_switch_for_each_port(sw, port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		cap = tb_port_find_cap(port, TB_PORT_CAP_TIME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (cap > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			port->cap_tmu = cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = tb_switch_tmu_rate_read(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	sw->tmu.rate = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	sw->tmu.has_ucap = tb_switch_tmu_ucap_supported(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (sw->tmu.has_ucap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		tb_sw_dbg(sw, "TMU: supports uni-directional mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (tb_route(sw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			struct tb_port *up = tb_upstream_port(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			sw->tmu.unidirectional =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				tb_port_tmu_is_unidirectional(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		sw->tmu.unidirectional = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	tb_sw_dbg(sw, "TMU: current mode: %s\n", tb_switch_tmu_mode_name(sw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * tb_switch_tmu_post_time() - Update switch local time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * @sw: Switch whose time to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * Updates switch local time using time posting procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int tb_switch_tmu_post_time(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	unsigned int  post_local_time_offset, post_time_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct tb_switch *root_switch = sw->tb->root_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u64 hi, mid, lo, local_time, post_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int i, ret, retries = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 gm_local_time[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (!tb_route(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!tb_switch_is_usb4(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Need to be able to read the grand master time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (!root_switch->tmu.cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ret = tb_sw_read(root_switch, gm_local_time, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			 root_switch->tmu.cap + TMU_RTR_CS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			 ARRAY_SIZE(gm_local_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (i = 0; i < ARRAY_SIZE(gm_local_time); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		tb_sw_dbg(root_switch, "local_time[%d]=0x%08x\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			  gm_local_time[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* Convert to nanoseconds (drop fractional part) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	hi = gm_local_time[2] & TMU_RTR_CS_3_LOCAL_TIME_NS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	mid = gm_local_time[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	lo = (gm_local_time[0] & TMU_RTR_CS_1_LOCAL_TIME_NS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	local_time = hi << 48 | mid << 16 | lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* Tell the switch that time sync is disrupted for a while */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = tb_switch_tmu_set_time_disruption(sw, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	post_local_time_offset = sw->tmu.cap + TMU_RTR_CS_22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	post_time_offset = sw->tmu.cap + TMU_RTR_CS_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * Write the Grandmaster time to the Post Local Time registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 * of the new switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ret = tb_sw_write(sw, &local_time, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			  post_local_time_offset, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * Have the new switch update its local time (by writing 1 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * the post_time registers) and wait for the completion of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * same (post_time register becomes 0). This means the time has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * been converged properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	post_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ret = tb_sw_write(sw, &post_time, TB_CFG_SWITCH, post_time_offset, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		ret = tb_sw_read(sw, &post_time, TB_CFG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				 post_time_offset, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	} while (--retries && post_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (!retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	tb_sw_dbg(sw, "TMU: updated local time to %#llx\n", local_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	tb_switch_tmu_set_time_disruption(sw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * tb_switch_tmu_disable() - Disable TMU of a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  * @sw: Switch whose TMU to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  * Turns off TMU of @sw if it is enabled. If not enabled does nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int tb_switch_tmu_disable(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!tb_switch_is_usb4(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* Already disabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (sw->tmu.rate == TB_SWITCH_TMU_RATE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (sw->tmu.unidirectional) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		struct tb_switch *parent = tb_switch_parent(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		struct tb_port *up, *down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		up = tb_upstream_port(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		down = tb_port_at(tb_route(sw), parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		/* The switch may be unplugged so ignore any errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		tb_port_tmu_unidirectional_disable(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ret = tb_port_tmu_unidirectional_disable(down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	sw->tmu.unidirectional = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	sw->tmu.rate = TB_SWITCH_TMU_RATE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	tb_sw_dbg(sw, "TMU: disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  * tb_switch_tmu_enable() - Enable TMU on a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * @sw: Switch whose TMU to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * Enables TMU of a switch to be in bi-directional, HiFi mode. In this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  * all tunneling should work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int tb_switch_tmu_enable(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (!tb_switch_is_usb4(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (tb_switch_tmu_is_enabled(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ret = tb_switch_tmu_set_time_disruption(sw, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/* Change mode to bi-directional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (tb_route(sw) && sw->tmu.unidirectional) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		struct tb_switch *parent = tb_switch_parent(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		struct tb_port *up, *down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		up = tb_upstream_port(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		down = tb_port_at(tb_route(sw), parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		ret = tb_port_tmu_unidirectional_disable(down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		ret = tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_HIFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		ret = tb_port_tmu_unidirectional_disable(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		ret = tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_HIFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	sw->tmu.unidirectional = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	sw->tmu.rate = TB_SWITCH_TMU_RATE_HIFI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	tb_sw_dbg(sw, "TMU: mode set to: %s\n", tb_switch_tmu_mode_name(sw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return tb_switch_tmu_set_time_disruption(sw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }