^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Thunderbolt driver - Port/Switch config area registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Every thunderbolt device consists (logically) of a switch with multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COUNTERS) which are used to configure the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _TB_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _TB_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * TODO: should be 63? But we do not know how to receive frames larger than 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TB_MAX_CONFIG_RW_LENGTH 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum tb_switch_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) TB_SWITCH_CAP_TMU = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) TB_SWITCH_CAP_VSE = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum tb_switch_vse_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) TB_VSE_CAP_TIME2 = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) TB_VSE_CAP_IECS = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum tb_port_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) TB_PORT_CAP_PHY = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) TB_PORT_CAP_POWER = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) TB_PORT_CAP_TIME1 = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) TB_PORT_CAP_ADAP = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) TB_PORT_CAP_VSE = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) TB_PORT_CAP_USB4 = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum tb_port_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) TB_PORT_CONNECTING = 1, /* retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) TB_PORT_UP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) TB_PORT_UNPLUGGED = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* capability headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct tb_cap_basic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* enum tb_cap cap:8; prevent "narrower than values of its type" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 cap; /* if cap == 0x05 then we have a extended capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * struct tb_cap_extended_short - Switch extended short capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @next: Pointer to the next capability. If @next and @length are zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * then we have a long cap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @cap: Base capability ID (see &enum tb_switch_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @length: Length of this capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct tb_cap_extended_short {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 vsec_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * struct tb_cap_extended_long - Switch extended long capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @zero1: This field should be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @cap: Base capability ID (see &enum tb_switch_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @zero2: This field should be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @next: Pointer to the next capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @length: Length of this capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tb_cap_extended_long {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 zero1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 vsec_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 zero2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * struct tb_cap_any - Structure capable of hold every capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @basic: Basic capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @extended_short: Vendor specific capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @extended_long: Vendor specific extended capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct tb_cap_any {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct tb_cap_basic basic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct tb_cap_extended_short extended_short;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct tb_cap_extended_long extended_long;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tb_cap_link_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct tb_cap_extended_long cap_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 count:4; /* number of link controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 unknown1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 base_offset:8; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * offset (into this capability) of the configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * area of the first link controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 length:12; /* link controller configuration area length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 unknown2:4; /* TODO check that length is correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct tb_cap_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct tb_cap_basic cap_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 unknown1:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 unknown2:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 unknown3:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum tb_port_state state:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 unknown4:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct tb_eeprom_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool clock:1; /* send pulse to transfer one bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool access_low:1; /* set to 0 before access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool data_out:1; /* to eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bool data_in:1; /* from eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool access_high:1; /* set to 1 before access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool not_present:1; /* should be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool unknown1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool present:1; /* should be 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 unknown2:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tb_cap_plug_events {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct tb_cap_extended_short cap_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 __unknown1:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 plug_events:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 __unknown2:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 __unknown3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 __unknown4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct tb_eeprom_ctl eeprom_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 __unknown5[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* device headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Present on port 0 in TB_CFG_SWITCH at address zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct tb_regs_switch_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 first_cap_offset:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 upstream_port_number:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 max_port_number:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 depth:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 __unknown1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 revision:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 route_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 route_hi:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bool enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 plug_events_delay:8; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * RW, pause between plug events in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * milliseconds. Writing 0x00 is interpreted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * as 255ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 cmuv:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 __unknown4:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 thunderbolt_version:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* USB4 version 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define USB4_VERSION_1_0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ROUTER_CS_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ROUTER_CS_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ROUTER_CS_5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ROUTER_CS_5_SLP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ROUTER_CS_5_WOP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ROUTER_CS_5_WOU BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ROUTER_CS_5_C3S BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ROUTER_CS_5_PTO BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ROUTER_CS_5_UTO BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ROUTER_CS_5_HCO BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ROUTER_CS_5_CV BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ROUTER_CS_6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ROUTER_CS_6_SLPR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ROUTER_CS_6_TNS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ROUTER_CS_6_WOPS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ROUTER_CS_6_WOUS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ROUTER_CS_6_HCI BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ROUTER_CS_6_CR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ROUTER_CS_7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ROUTER_CS_9 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ROUTER_CS_25 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ROUTER_CS_26 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ROUTER_CS_26_STATUS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ROUTER_CS_26_ONS BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ROUTER_CS_26_OV BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Router TMU configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TMU_RTR_CS_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TMU_RTR_CS_0_TD BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TMU_RTR_CS_0_UCAP BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TMU_RTR_CS_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TMU_RTR_CS_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TMU_RTR_CS_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TMU_RTR_CS_22 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TMU_RTR_CS_24 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum tb_port_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) TB_TYPE_INACTIVE = 0x000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TB_TYPE_PORT = 0x000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TB_TYPE_NHI = 0x000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* TB_TYPE_SATA = 0x080000, lower order bits are not known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TB_TYPE_DP_HDMI_IN = 0x0e0101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TB_TYPE_DP_HDMI_OUT = 0x0e0102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) TB_TYPE_PCIE_DOWN = 0x100101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TB_TYPE_PCIE_UP = 0x100102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) TB_TYPE_USB3_DOWN = 0x200101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TB_TYPE_USB3_UP = 0x200102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Present on every port in TB_CF_PORT at address zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct tb_regs_port_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 first_cap_offset:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 max_counters:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 counters_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 __unknown1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 revision:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum tb_port_type type:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 thunderbolt_version:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 __unknown2:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 port_number:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 __unknown3:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 nfc_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* DWORD 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 max_in_hop_id:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 max_out_hop_id:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 __unknown4:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* DWORD 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 __unknown5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* DWORD 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 __unknown6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Basic adapter configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ADP_CS_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ADP_CS_4_LCK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ADP_CS_5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ADP_CS_5_LCA_MASK GENMASK(28, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ADP_CS_5_LCA_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* TMU adapter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TMU_ADP_CS_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TMU_ADP_CS_3_UDM BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Lane adapter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LANE_ADP_CS_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LANE_ADP_CS_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define LANE_ADP_CS_1_LD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define LANE_ADP_CS_1_LB BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* USB4 port registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PORT_CS_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PORT_CS_1_LENGTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PORT_CS_1_TARGET_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PORT_CS_1_TARGET_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PORT_CS_1_RETIMER_INDEX_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PORT_CS_1_WNR_WRITE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PORT_CS_1_NR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PORT_CS_1_RC BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PORT_CS_1_PND BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define PORT_CS_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PORT_CS_18 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PORT_CS_18_BE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PORT_CS_18_TCM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PORT_CS_18_WOU4S BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PORT_CS_19 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PORT_CS_19_PC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PORT_CS_19_PID BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PORT_CS_19_WOC BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PORT_CS_19_WOD BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PORT_CS_19_WOU4 BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Display Port adapter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ADP_DP_CS_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ADP_DP_CS_0_AE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ADP_DP_CS_0_VE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ADP_DP_CS_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ADP_DP_CS_2_HDP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ADP_DP_CS_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ADP_DP_CS_3_HDPC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DP_LOCAL_CAP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DP_REMOTE_CAP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DP_STATUS_CTRL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DP_STATUS_CTRL_CMHS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DP_STATUS_CTRL_UF BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DP_COMMON_CAP 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * with exception of DPRX done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DP_COMMON_CAP_RATE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DP_COMMON_CAP_RATE_RBR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DP_COMMON_CAP_RATE_HBR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DP_COMMON_CAP_RATE_HBR2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DP_COMMON_CAP_RATE_HBR3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DP_COMMON_CAP_LANES_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DP_COMMON_CAP_1_LANE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DP_COMMON_CAP_2_LANES 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DP_COMMON_CAP_4_LANES 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DP_COMMON_CAP_DPRX_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* PCIe adapter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ADP_PCIE_CS_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ADP_PCIE_CS_0_PE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* USB adapter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ADP_USB3_CS_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ADP_USB3_CS_0_V BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ADP_USB3_CS_0_PE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ADP_USB3_CS_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ADP_USB3_CS_1_CDBW_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ADP_USB3_CS_1_HCA BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ADP_USB3_CS_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ADP_USB3_CS_2_ADBW_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define ADP_USB3_CS_2_CMR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ADP_USB3_CS_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ADP_USB3_CS_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ADP_USB3_CS_4_ALR_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ADP_USB3_CS_4_ALR_20G 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define ADP_USB3_CS_4_ULV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define ADP_USB3_CS_4_MSLR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define ADP_USB3_CS_4_MSLR_20G 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Hop register from TB_CFG_HOPS. 8 byte per entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct tb_regs_hop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 next_hop:11; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * hop to take after sending the packet through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * out_port (on the incoming port of the next switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 out_port:6; /* next port of the path (on the same switch) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 initial_credits:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 unknown1:6; /* set to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bool enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 weight:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 unknown2:4; /* set to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 priority:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool drop_packages:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bool counter_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) bool ingress_fc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bool egress_fc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bool ingress_shared_buffer:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bool egress_shared_buffer:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool pending:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 unknown3:3; /* set to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Common link controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define TB_LC_DESC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TB_LC_DESC_SIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define TB_LC_DESC_PORT_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define TB_LC_FUSE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TB_LC_SNK_ALLOCATION 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TB_LC_POWER 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Link controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define TB_LC_PORT_ATTR 0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TB_LC_PORT_ATTR_BE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TB_LC_SX_CTRL 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TB_LC_SX_CTRL_WOC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TB_LC_SX_CTRL_WOD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define TB_LC_SX_CTRL_WOU4 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TB_LC_SX_CTRL_WOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TB_LC_SX_CTRL_L1C BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TB_LC_SX_CTRL_L1D BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TB_LC_SX_CTRL_L2C BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TB_LC_SX_CTRL_L2D BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TB_LC_SX_CTRL_UPSTREAM BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TB_LC_SX_CTRL_SLP BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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