^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Thunderbolt driver - bus logic (NHI independent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef TB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/thunderbolt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "tb_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ctl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "dma_port.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NVM_MIN_SIZE SZ_32K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NVM_MAX_SIZE SZ_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Intel specific NVM offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NVM_DEVID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NVM_VERSION 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NVM_FLASH_SIZE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * struct tb_nvm - Structure holding NVM information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @dev: Owner of the NVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @major: Major version number of the active NVM portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @minor: Minor version number of the active NVM portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @id: Identifier used with both NVM portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @active: Active portion NVMem device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @non_active: Non-active portion NVMem device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @buf: Buffer where the NVM image is stored before it is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * the actual NVM flash device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @buf_data_size: Number of bytes actually consumed by the new NVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @authenticating: The device is authenticating the new NVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @flushed: The image has been flushed to the storage area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The user of this structure needs to handle serialization of possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * concurrent access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct tb_nvm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct nvmem_device *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct nvmem_device *non_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) size_t buf_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bool authenticating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TB_SWITCH_KEY_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TB_SWITCH_MAX_DEPTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USB4_SWITCH_MAX_DEPTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * enum tb_switch_tmu_rate - TMU refresh rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @TB_SWITCH_TMU_RATE_OFF: %0 (Disable Time Sync handshake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @TB_SWITCH_TMU_RATE_HIFI: %16 us time interval between successive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * transmission of the Delay Request TSNOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * (Time Sync Notification Ordered Set) on a Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @TB_SWITCH_TMU_RATE_NORMAL: %1 ms time interval between successive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * transmission of the Delay Request TSNOS on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * a Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum tb_switch_tmu_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) TB_SWITCH_TMU_RATE_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) TB_SWITCH_TMU_RATE_HIFI = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) TB_SWITCH_TMU_RATE_NORMAL = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * struct tb_switch_tmu - Structure holding switch TMU configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @cap: Offset to the TMU capability (%0 if not found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @has_ucap: Does the switch support uni-directional mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @rate: TMU refresh rate related to upstream switch. In case of root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * switch this holds the domain rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @unidirectional: Is the TMU in uni-directional or bi-directional mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * related to upstream switch. Don't case for root switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct tb_switch_tmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool has_ucap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum tb_switch_tmu_rate rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool unidirectional;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * struct tb_switch - a thunderbolt switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @dev: Device for the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @config: Switch configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @ports: Ports in this switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @dma_port: If the switch has port supporting DMA configuration based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * mailbox this will hold the pointer to that (%NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * otherwise). If set it also means the switch has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * upgradeable NVM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @tmu: The switch TMU configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @tb: Pointer to the domain the switch belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @uid: Unique ID of the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @uuid: UUID of the switch (or %NULL if not supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @vendor: Vendor ID of the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @device: Device ID of the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @vendor_name: Name of the vendor (or %NULL if not known)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @device_name: Name of the device (or %NULL if not known)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @link_speed: Speed of the link in Gb/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @link_width: Width of the link (1 or 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @link_usb4: Upstream link is USB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @generation: Switch Thunderbolt generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @cap_plug_events: Offset to the plug events capability (%0 if not found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @cap_lc: Offset to the link controller capability (%0 if not found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @is_unplugged: The switch is going away
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @drom: DROM of the switch (%NULL if not found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @nvm: Pointer to the NVM if the switch has one (%NULL otherwise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @no_nvm_upgrade: Prevent NVM upgrade of this switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @safe_mode: The switch is in safe-mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @boot: Whether the switch was already authorized on boot or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @rpm: The switch supports runtime PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @authorized: Whether the switch is authorized by user or policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @security_level: Switch supported security level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @debugfs_dir: Pointer to the debugfs structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @key: Contains the key used to challenge the device or %NULL if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * supported. Size of the key is %TB_SWITCH_KEY_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @connection_id: Connection ID used with ICM messaging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @connection_key: Connection key used with ICM messaging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @link: Root switch link this switch is connected (ICM only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @depth: Depth in the chain this switch is connected (ICM only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @rpm_complete: Completion used to wait for runtime resume to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * complete (ICM only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @quirks: Quirks used for this Thunderbolt switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * When the switch is being added or removed to the domain (other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * switches) you need to have domain lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct tb_switch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tb_regs_switch_header config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tb_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct tb_dma_port *dma_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tb_switch_tmu tmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct tb *tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u64 uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) uuid_t *uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *vendor_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *device_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int link_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool link_usb4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int cap_plug_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int cap_lc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool is_unplugged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 *drom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct tb_nvm *nvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool no_nvm_upgrade;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool safe_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int authorized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum tb_security_level security_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 *key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 connection_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 connection_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct completion rpm_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * struct tb_port - a thunderbolt port, part of a tb_switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @config: Cached port configuration read from registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @sw: Switch the port belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @remote: Remote port (%NULL if not connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @xdomain: Remote host (%NULL if not connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @cap_phy: Offset, zero if not found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @cap_tmu: Offset of the adapter specific TMU capability (%0 if not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @cap_adap: Offset of the adapter specific capability (%0 if not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @cap_usb4: Offset to the USB4 port capability (%0 if not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @port: Port number on switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @disabled: Disabled by eeprom or enabled but not implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @bonded: true if the port is bonded (two lanes combined as one)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @dual_link_port: If the switch is connected using two ports, points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * to the other port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @link_nr: Is this primary or secondary port on the dual_link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @in_hopids: Currently allocated input HopIDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @out_hopids: Currently allocated output HopIDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @list: Used to link ports to DP resources list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct tb_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct tb_regs_port_header config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct tb_switch *sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct tb_port *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct tb_xdomain *xdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int cap_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int cap_tmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int cap_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int cap_usb4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bool bonded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct tb_port *dual_link_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 link_nr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct ida in_hopids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ida out_hopids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * tb_retimer: Thunderbolt retimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @dev: Device for the retimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @tb: Pointer to the domain the retimer belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @index: Retimer index facing the router USB4 port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @vendor: Vendor ID of the retimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @device: Device ID of the retimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @port: Pointer to the lane 0 adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @nvm: Pointer to the NVM if the retimer has one (%NULL otherwise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @auth_status: Status of last NVM authentication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct tb_retimer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct tb *tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct tb_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct tb_nvm *nvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 auth_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * struct tb_path_hop - routing information for a tb_path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @in_port: Ingress port of a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @out_port: Egress port of a switch where the packet is routed out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * (must be on the same switch than @in_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @in_hop_index: HopID where the path configuration entry is placed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * the path config space of @in_port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @in_counter_index: Used counter index (not used in the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * currently, %-1 to disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @next_hop_index: HopID of the packet when it is routed out from @out_port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @initial_credits: Number of initial flow control credits allocated for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Hop configuration is always done on the IN port of a switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * in_port and out_port have to be on the same switch. Packets arriving on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * in_port with "hop" = in_hop_index will get routed to through out_port. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * next hop to take (on out_port->remote) is determined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * next_hop_index. When routing packet to another switch (out->remote is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * set) the @next_hop_index must match the @in_hop_index of that next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * hop to make routing possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * in_counter_index is the index of a counter (in TB_CFG_COUNTERS) on the in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct tb_path_hop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct tb_port *in_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct tb_port *out_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int in_hop_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int in_counter_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int next_hop_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int initial_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * enum tb_path_port - path options mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @TB_PATH_NONE: Do not activate on any hop on path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @TB_PATH_SOURCE: Activate on the first hop (out of src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @TB_PATH_INTERNAL: Activate on the intermediate hops (not the first/last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @TB_PATH_DESTINATION: Activate on the last hop (into dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @TB_PATH_ALL: Activate on all hops on the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum tb_path_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) TB_PATH_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) TB_PATH_SOURCE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) TB_PATH_INTERNAL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) TB_PATH_DESTINATION = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) TB_PATH_ALL = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * struct tb_path - a unidirectional path between two ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @tb: Pointer to the domain structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @name: Name of the path (used for debugging)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @nfc_credits: Number of non flow controlled credits allocated for the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @ingress_shared_buffer: Shared buffering used for ingress ports on the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @egress_shared_buffer: Shared buffering used for egress ports on the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @ingress_fc_enable: Flow control for ingress ports on the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @egress_fc_enable: Flow control for egress ports on the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @priority: Priority group if the path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @weight: Weight of the path inside the priority group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @drop_packages: Drop packages from queue tail or head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @activated: Is the path active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @clear_fc: Clear all flow control from the path config space entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * when deactivating this path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @hops: Path hops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @path_length: How many hops the path uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * A path consists of a number of hops (see &struct tb_path_hop). To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * establish a PCIe tunnel two paths have to be created between the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * PCIe ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct tb_path {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct tb *tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int nfc_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum tb_path_port ingress_shared_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) enum tb_path_port egress_shared_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) enum tb_path_port ingress_fc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum tb_path_port egress_fc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int priority:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int weight:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool drop_packages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bool activated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) bool clear_fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct tb_path_hop *hops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int path_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* HopIDs 0-7 are reserved by the Thunderbolt protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TB_PATH_MIN_HOPID 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Support paths from the farthest (depth 6) router to the host and back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * to the same level (not necessarily to the same router).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TB_PATH_MAX_HOPS (7 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Possible wake types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TB_WAKE_ON_CONNECT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TB_WAKE_ON_DISCONNECT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TB_WAKE_ON_USB4 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TB_WAKE_ON_USB3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TB_WAKE_ON_PCIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * struct tb_cm_ops - Connection manager specific operations vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @driver_ready: Called right after control channel is started. Used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * ICM to send driver ready message to the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @start: Starts the domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @stop: Stops the domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @suspend_noirq: Connection manager specific suspend_noirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @resume_noirq: Connection manager specific resume_noirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @suspend: Connection manager specific suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @freeze_noirq: Connection manager specific freeze_noirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @thaw_noirq: Connection manager specific thaw_noirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @complete: Connection manager specific complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @runtime_suspend: Connection manager specific runtime_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @runtime_resume: Connection manager specific runtime_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @runtime_suspend_switch: Runtime suspend a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @runtime_resume_switch: Runtime resume a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @handle_event: Handle thunderbolt event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * @get_boot_acl: Get boot ACL list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * @set_boot_acl: Set boot ACL list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * @approve_switch: Approve switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @add_switch_key: Add key to switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * @challenge_switch_key: Challenge switch using key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @disconnect_pcie_paths: Disconnects PCIe paths before NVM update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @approve_xdomain_paths: Approve (establish) XDomain DMA paths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @disconnect_xdomain_paths: Disconnect XDomain DMA paths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct tb_cm_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int (*driver_ready)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int (*start)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void (*stop)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int (*suspend_noirq)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int (*resume_noirq)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int (*suspend)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int (*freeze_noirq)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int (*thaw_noirq)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void (*complete)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int (*runtime_suspend)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int (*runtime_resume)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int (*runtime_suspend_switch)(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int (*runtime_resume_switch)(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void (*handle_event)(struct tb *tb, enum tb_cfg_pkg_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) const void *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int (*get_boot_acl)(struct tb *tb, uuid_t *uuids, size_t nuuids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int (*set_boot_acl)(struct tb *tb, const uuid_t *uuids, size_t nuuids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int (*approve_switch)(struct tb *tb, struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int (*add_switch_key)(struct tb *tb, struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int (*challenge_switch_key)(struct tb *tb, struct tb_switch *sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) const u8 *challenge, u8 *response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int (*disconnect_pcie_paths)(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int (*approve_xdomain_paths)(struct tb *tb, struct tb_xdomain *xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int (*disconnect_xdomain_paths)(struct tb *tb, struct tb_xdomain *xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static inline void *tb_priv(struct tb *tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return (void *)tb->privdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TB_AUTOSUSPEND_DELAY 15000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* helper functions & macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * tb_upstream_port() - return the upstream port of a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Every switch has an upstream port (for the root switch it is the NHI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * During switch alloc/init tb_upstream_port()->remote may be NULL, even for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * non root switches (on the NHI port remote is always NULL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Return: Returns the upstream port of the switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static inline struct tb_port *tb_upstream_port(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return &sw->ports[sw->config.upstream_port_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * tb_is_upstream_port() - Is the port upstream facing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * @port: Port to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Returns true if @port is upstream facing port. In case of dual link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * ports both return true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline bool tb_is_upstream_port(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) const struct tb_port *upstream_port = tb_upstream_port(port->sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return port == upstream_port || port->dual_link_port == upstream_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline u64 tb_route(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ((u64) sw->config.route_hi) << 32 | sw->config.route_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline struct tb_port *tb_port_at(u64 route, struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) port = route >> (sw->config.depth * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (WARN_ON(port > sw->config.max_port_number))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return &sw->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * tb_port_has_remote() - Does the port have switch connected downstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * @port: Port to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Returns true only when the port is primary port and has remote set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static inline bool tb_port_has_remote(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (tb_is_upstream_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!port->remote)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (port->dual_link_port && port->link_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline bool tb_port_is_null(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return port && port->port && port->config.type == TB_TYPE_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline bool tb_port_is_nhi(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return port && port->config.type == TB_TYPE_NHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline bool tb_port_is_pcie_down(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return port && port->config.type == TB_TYPE_PCIE_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static inline bool tb_port_is_pcie_up(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return port && port->config.type == TB_TYPE_PCIE_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static inline bool tb_port_is_dpin(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return port && port->config.type == TB_TYPE_DP_HDMI_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static inline bool tb_port_is_dpout(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return port && port->config.type == TB_TYPE_DP_HDMI_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static inline bool tb_port_is_usb3_down(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return port && port->config.type == TB_TYPE_USB3_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline bool tb_port_is_usb3_up(const struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return port && port->config.type == TB_TYPE_USB3_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static inline int tb_sw_read(struct tb_switch *sw, void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enum tb_cfg_space space, u32 offset, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (sw->is_unplugged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return tb_cfg_read(sw->tb->ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) tb_route(sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline int tb_sw_write(struct tb_switch *sw, const void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) enum tb_cfg_space space, u32 offset, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (sw->is_unplugged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return tb_cfg_write(sw->tb->ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tb_route(sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static inline int tb_port_read(struct tb_port *port, void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) enum tb_cfg_space space, u32 offset, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (port->sw->is_unplugged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return tb_cfg_read(port->sw->tb->ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tb_route(port->sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) port->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static inline int tb_port_write(struct tb_port *port, const void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) enum tb_cfg_space space, u32 offset, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (port->sw->is_unplugged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return tb_cfg_write(port->sw->tb->ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tb_route(port->sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) port->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define tb_err(tb, fmt, arg...) dev_err(&(tb)->nhi->pdev->dev, fmt, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define tb_WARN(tb, fmt, arg...) dev_WARN(&(tb)->nhi->pdev->dev, fmt, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define tb_warn(tb, fmt, arg...) dev_warn(&(tb)->nhi->pdev->dev, fmt, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define tb_info(tb, fmt, arg...) dev_info(&(tb)->nhi->pdev->dev, fmt, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define tb_dbg(tb, fmt, arg...) dev_dbg(&(tb)->nhi->pdev->dev, fmt, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define __TB_SW_PRINT(level, sw, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct tb_switch *__sw = (sw); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) level(__sw->tb, "%llx: " fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tb_route(__sw), ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define tb_sw_WARN(sw, fmt, arg...) __TB_SW_PRINT(tb_WARN, sw, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define tb_sw_warn(sw, fmt, arg...) __TB_SW_PRINT(tb_warn, sw, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define tb_sw_info(sw, fmt, arg...) __TB_SW_PRINT(tb_info, sw, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define tb_sw_dbg(sw, fmt, arg...) __TB_SW_PRINT(tb_dbg, sw, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define __TB_PORT_PRINT(level, _port, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const struct tb_port *__port = (_port); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) level(__port->sw->tb, "%llx:%x: " fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) tb_route(__port->sw), __port->port, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define tb_port_WARN(port, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) __TB_PORT_PRINT(tb_WARN, port, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define tb_port_warn(port, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __TB_PORT_PRINT(tb_warn, port, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define tb_port_info(port, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __TB_PORT_PRINT(tb_info, port, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define tb_port_dbg(port, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) __TB_PORT_PRINT(tb_dbg, port, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct tb *icm_probe(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct tb *tb_probe(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) extern struct device_type tb_domain_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) extern struct device_type tb_retimer_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) extern struct device_type tb_switch_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int tb_domain_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void tb_domain_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int tb_xdomain_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) void tb_xdomain_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct tb *tb_domain_alloc(struct tb_nhi *nhi, size_t privsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int tb_domain_add(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) void tb_domain_remove(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int tb_domain_suspend_noirq(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int tb_domain_resume_noirq(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int tb_domain_suspend(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int tb_domain_freeze_noirq(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int tb_domain_thaw_noirq(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void tb_domain_complete(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int tb_domain_runtime_suspend(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int tb_domain_runtime_resume(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int tb_domain_approve_switch(struct tb *tb, struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int tb_domain_approve_switch_key(struct tb *tb, struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int tb_domain_challenge_switch_key(struct tb *tb, struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int tb_domain_disconnect_pcie_paths(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int tb_domain_approve_xdomain_paths(struct tb *tb, struct tb_xdomain *xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int tb_domain_disconnect_xdomain_paths(struct tb *tb, struct tb_xdomain *xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int tb_domain_disconnect_all_paths(struct tb *tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static inline struct tb *tb_domain_get(struct tb *tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) get_device(&tb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static inline void tb_domain_put(struct tb *tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) put_device(&tb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct tb_nvm *tb_nvm_alloc(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int tb_nvm_add_active(struct tb_nvm *nvm, size_t size, nvmem_reg_read_t reg_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int tb_nvm_write_buf(struct tb_nvm *nvm, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) size_t bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int tb_nvm_add_non_active(struct tb_nvm *nvm, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) nvmem_reg_write_t reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void tb_nvm_free(struct tb_nvm *nvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void tb_nvm_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct tb_switch *tb_switch_alloc(struct tb *tb, struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u64 route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct tb_switch *tb_switch_alloc_safe_mode(struct tb *tb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct device *parent, u64 route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int tb_switch_configure(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int tb_switch_add(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) void tb_switch_remove(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) void tb_switch_suspend(struct tb_switch *sw, bool runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int tb_switch_resume(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int tb_switch_reset(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) void tb_sw_set_unplugged(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct tb_port *tb_switch_find_port(struct tb_switch *sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) enum tb_port_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct tb_switch *tb_switch_find_by_link_depth(struct tb *tb, u8 link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct tb_switch *tb_switch_find_by_uuid(struct tb *tb, const uuid_t *uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct tb_switch *tb_switch_find_by_route(struct tb *tb, u64 route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * tb_switch_for_each_port() - Iterate over each switch port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * @sw: Switch whose ports to iterate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * @p: Port used as iterator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Iterates over each switch port skipping the control port (port %0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define tb_switch_for_each_port(sw, p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) for ((p) = &(sw)->ports[1]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (p) <= &(sw)->ports[(sw)->config.max_port_number]; (p)++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static inline struct tb_switch *tb_switch_get(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) get_device(&sw->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static inline void tb_switch_put(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) put_device(&sw->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static inline bool tb_is_switch(const struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return dev->type == &tb_switch_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static inline struct tb_switch *tb_to_switch(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (tb_is_switch(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return container_of(dev, struct tb_switch, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static inline struct tb_switch *tb_switch_parent(struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return tb_to_switch(sw->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static inline bool tb_switch_is_light_ridge(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return sw->config.vendor_id == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static inline bool tb_switch_is_eagle_ridge(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return sw->config.vendor_id == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sw->config.device_id == PCI_DEVICE_ID_INTEL_EAGLE_RIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static inline bool tb_switch_is_cactus_ridge(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) switch (sw->config.device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static inline bool tb_switch_is_falcon_ridge(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (sw->config.device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static inline bool tb_switch_is_alpine_ridge(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) switch (sw->config.device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static inline bool tb_switch_is_titan_ridge(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) switch (sw->config.device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static inline bool tb_switch_is_ice_lake(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) switch (sw->config.device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case PCI_DEVICE_ID_INTEL_ICL_NHI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case PCI_DEVICE_ID_INTEL_ICL_NHI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static inline bool tb_switch_is_tiger_lake(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) switch (sw->config.device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case PCI_DEVICE_ID_INTEL_TGL_NHI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case PCI_DEVICE_ID_INTEL_TGL_NHI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case PCI_DEVICE_ID_INTEL_TGL_H_NHI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case PCI_DEVICE_ID_INTEL_TGL_H_NHI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * tb_switch_is_usb4() - Is the switch USB4 compliant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * @sw: Switch to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * Returns true if the @sw is USB4 compliant router, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static inline bool tb_switch_is_usb4(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return sw->config.thunderbolt_version == USB4_VERSION_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * tb_switch_is_icm() - Is the switch handled by ICM firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * @sw: Switch to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * In case there is a need to differentiate whether ICM firmware or SW CM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * is handling @sw this function can be called. It is valid to call this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * after tb_switch_alloc() and tb_switch_configure() has been called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * (latter only for SW CM case).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static inline bool tb_switch_is_icm(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return !sw->config.enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int tb_switch_lane_bonding_enable(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) void tb_switch_lane_bonding_disable(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int tb_switch_configure_link(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) void tb_switch_unconfigure_link(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) bool tb_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int tb_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) void tb_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int tb_switch_tmu_init(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int tb_switch_tmu_post_time(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int tb_switch_tmu_disable(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int tb_switch_tmu_enable(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static inline bool tb_switch_tmu_is_enabled(const struct tb_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return sw->tmu.rate == TB_SWITCH_TMU_RATE_HIFI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) !sw->tmu.unidirectional;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int tb_wait_for_port(struct tb_port *port, bool wait_if_unplugged);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int tb_port_add_nfc_credits(struct tb_port *port, int credits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int tb_port_set_initial_credits(struct tb_port *port, u32 credits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int tb_port_clear_counter(struct tb_port *port, int counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int tb_port_unlock(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int tb_port_enable(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int tb_port_disable(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int tb_port_alloc_in_hopid(struct tb_port *port, int hopid, int max_hopid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) void tb_port_release_in_hopid(struct tb_port *port, int hopid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int tb_port_alloc_out_hopid(struct tb_port *port, int hopid, int max_hopid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) void tb_port_release_out_hopid(struct tb_port *port, int hopid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct tb_port *tb_next_port_on_path(struct tb_port *start, struct tb_port *end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct tb_port *prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * tb_for_each_port_on_path() - Iterate over each port on path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * @src: Source port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * @dst: Destination port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * @p: Port used as iterator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Walks over each port on path from @src to @dst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define tb_for_each_port_on_path(src, dst, p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) for ((p) = tb_next_port_on_path((src), (dst), NULL); (p); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (p) = tb_next_port_on_path((src), (dst), (p)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int tb_port_get_link_speed(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int tb_switch_find_vse_cap(struct tb_switch *sw, enum tb_switch_vse_cap vsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int tb_switch_next_cap(struct tb_switch *sw, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int tb_port_find_cap(struct tb_port *port, enum tb_port_cap cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int tb_port_next_cap(struct tb_port *port, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) bool tb_port_is_enabled(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) bool tb_usb3_port_is_enabled(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int tb_usb3_port_enable(struct tb_port *port, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) bool tb_pci_port_is_enabled(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int tb_pci_port_enable(struct tb_port *port, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int tb_dp_port_hpd_is_active(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int tb_dp_port_hpd_clear(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int tb_dp_port_set_hops(struct tb_port *port, unsigned int video,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) unsigned int aux_tx, unsigned int aux_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) bool tb_dp_port_is_enabled(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int tb_dp_port_enable(struct tb_port *port, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct tb_path *tb_path_discover(struct tb_port *src, int src_hopid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct tb_port *dst, int dst_hopid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct tb_port **last, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct tb_path *tb_path_alloc(struct tb *tb, struct tb_port *src, int src_hopid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct tb_port *dst, int dst_hopid, int link_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) void tb_path_free(struct tb_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int tb_path_activate(struct tb_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void tb_path_deactivate(struct tb_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) bool tb_path_is_invalid(struct tb_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) bool tb_path_port_on_path(const struct tb_path *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) const struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int tb_drom_read(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int tb_lc_configure_port(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) void tb_lc_unconfigure_port(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int tb_lc_configure_xdomain(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) void tb_lc_unconfigure_xdomain(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int tb_lc_set_sleep(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) bool tb_lc_lane_bonding_possible(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int tb_lc_force_power(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static inline int tb_route_length(u64 route)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return (fls64(route) + TB_ROUTE_SHIFT - 1) / TB_ROUTE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * tb_downstream_route() - get route to downstream switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * Port must not be the upstream port (otherwise a loop is created).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * Return: Returns a route to the switch behind @port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static inline u64 tb_downstream_route(struct tb_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return tb_route(port->sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) | ((u64) port->port << (port->sw->config.depth * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) bool tb_xdomain_handle_request(struct tb *tb, enum tb_cfg_pkg_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) const void *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct tb_xdomain *tb_xdomain_alloc(struct tb *tb, struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u64 route, const uuid_t *local_uuid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) const uuid_t *remote_uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) void tb_xdomain_add(struct tb_xdomain *xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) void tb_xdomain_remove(struct tb_xdomain *xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct tb_xdomain *tb_xdomain_find_by_link_depth(struct tb *tb, u8 link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int tb_retimer_scan(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) void tb_retimer_remove_all(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static inline bool tb_is_retimer(const struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return dev->type == &tb_retimer_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static inline struct tb_retimer *tb_to_retimer(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (tb_is_retimer(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return container_of(dev, struct tb_retimer, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int usb4_switch_setup(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) bool usb4_switch_lane_bonding_possible(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int usb4_switch_set_sleep(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int usb4_switch_nvm_sector_size(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const void *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int usb4_switch_nvm_authenticate(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) const struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) const struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int usb4_port_unlock(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int usb4_port_configure(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) void usb4_port_unconfigure(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int usb4_port_configure_xdomain(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) void usb4_port_unconfigure_xdomain(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int usb4_port_enumerate_retimers(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u8 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) const void *buf, u8 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int usb4_port_retimer_is_last(struct tb_port *port, u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned int address, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned int address, void *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int usb4_usb3_port_max_link_rate(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int usb4_usb3_port_actual_link_rate(struct tb_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int *downstream_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int *downstream_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) int *downstream_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Keep link controller awake during update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) void tb_check_quirks(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) void tb_acpi_add_links(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static inline void tb_acpi_add_links(struct tb_nhi *nhi) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) void tb_debugfs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) void tb_debugfs_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void tb_switch_debugfs_init(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) void tb_switch_debugfs_remove(struct tb_switch *sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static inline void tb_debugfs_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static inline void tb_debugfs_exit(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static inline void tb_switch_debugfs_init(struct tb_switch *sw) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static inline void tb_switch_debugfs_remove(struct tb_switch *sw) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #ifdef CONFIG_USB4_KUNIT_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int tb_test_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) void tb_test_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static inline int tb_test_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static inline void tb_test_exit(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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