^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Thunderbolt driver - NHI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef NHI_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define NHI_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum ring_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) RING_FLAG_PCI_NO_SNOOP = 1 << 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) RING_FLAG_ENABLE = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct ring_desc - TX/RX ring entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * For TX set length/eof/sof.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * For RX length/eof/sof are set by the NHI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct ring_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u64 phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 length:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 eof:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 sof:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum ring_desc_flags flags:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 time; /* write zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* NHI registers in bar 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 00: physical pointer to an array of struct ring_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 08: ring tail (set by NHI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 10: ring head (index of first non posted descriptor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 12: descriptor count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_TX_RING_BASE 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 00: physical pointer to an array of struct ring_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 08: ring head (index of first not posted descriptor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 10: ring tail (set by NHI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 12: descriptor count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 14: max frame sizes (anything larger than 0x100 has no effect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_RX_RING_BASE 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 00: enum_ring_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 04: isoch time stamp ?? (write 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * ..: unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_TX_OPTIONS_BASE 0x19800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 00: enum ring_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * the corresponding TX hop id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ..: unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_RX_OPTIONS_BASE 0x29800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * three bitfields: tx, rx, rx overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * cleared on read. New interrupts are fired only after ALL registers have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * read (even those containing only disabled rings).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_RING_NOTIFY_BASE 0x37800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * two bitfields: rx, tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * enable/disable interrupts set/clear the corresponding bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_RING_INTERRUPT_BASE 0x38200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_INT_THROTTLING_RATE 0x38c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Interrupt Vector Allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_INT_VEC_ALLOC_BASE 0x38c40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_INT_VEC_ALLOC_BITS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* The last 11 bits contain the number of hops supported by the NHI port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_HOP_COUNT 0x39640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_DMA_MISC 0x39864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_INMAIL_DATA 0x39900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_INMAIL_CMD 0x39904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_INMAIL_CMD_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_INMAIL_ERROR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_INMAIL_OP_REQUEST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_OUTMAIL_CMD 0x3990c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define REG_FW_STS 0x39944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define REG_FW_STS_NVM_AUTH_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define REG_FW_STS_CIO_RESET_REQ BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define REG_FW_STS_ICM_EN_CPU BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define REG_FW_STS_ICM_EN_INVERT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define REG_FW_STS_ICM_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* ICL NHI VSEC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* FW ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VS_CAP_9 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VS_CAP_9_FW_READY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* UUID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VS_CAP_10 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VS_CAP_11 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* LTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VS_CAP_15 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VS_CAP_16 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* TBT2PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VS_CAP_18 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VS_CAP_18_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* PCIe2TBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VS_CAP_19 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VS_CAP_19_VALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VS_CAP_19_CMD_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VS_CAP_19_CMD_MASK GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Force power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VS_CAP_22 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VS_CAP_22_FORCE_POWER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VS_CAP_22_DMA_DELAY_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @ICL_LC_GO2SX: Ask LC to enter Sx without wake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum icl_lc_mailbox_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ICL_LC_GO2SX = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ICL_LC_GO2SX_NO_WAKE = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ICL_LC_PREPARE_FOR_RESET = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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