^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NHI specific operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "nhi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "nhi_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "tb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Ice Lake specific NHI operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int check_for_device(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return tb_is_switch(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct tb *tb = pci_get_drvdata(nhi->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ret = device_for_each_child(&tb->root_switch->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) check_for_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return ret > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 vs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The Thunderbolt host controller is present always in Ice Lake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * but the firmware may not be loaded and running (depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * whether there is device connected and so on). Each time the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * controller is used we need to "Force Power" it first and wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * for the firmware to indicate it is up and running. This "Force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Power" is really not about actually powering on/off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * controller so it is accessible even if "Force Power" is off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * The actual power management happens inside shared ACPI power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * resources using standard ACPI methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) vs_cap |= VS_CAP_22_FORCE_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) vs_cap &= ~VS_CAP_22_FORCE_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int retries = 350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Wait until the firmware tells it is up and running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (val & VS_CAP_9_FW_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) usleep_range(3000, 3100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_write_config_dword(nhi->pdev, VS_CAP_19, data | VS_CAP_19_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) end = jiffies + msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pci_read_config_dword(nhi->pdev, VS_CAP_18, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (data & VS_CAP_18_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } while (time_before(jiffies, end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Clear the valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_write_config_dword(nhi->pdev, VS_CAP_19, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void icl_nhi_set_ltr(struct tb_nhi *nhi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 max_ltr, ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) max_ltr &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Program the same value for both snoop and no-snoop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ltr = max_ltr << 16 | max_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int icl_nhi_suspend(struct tb_nhi *nhi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct tb *tb = pci_get_drvdata(nhi->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (icl_nhi_is_device_connected(nhi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (tb_switch_is_icm(tb->root_switch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * If there is no device connected we need to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * both: a handshake through LC mailbox and force power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * down before entering D3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return icl_nhi_force_power(nhi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tb *tb = pci_get_drvdata(nhi->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum icl_lc_mailbox_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!pm_suspend_via_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return icl_nhi_suspend(nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!tb_switch_is_icm(tb->root_switch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) icl_nhi_lc_mailbox_cmd(nhi, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int icl_nhi_resume(struct tb_nhi *nhi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = icl_nhi_force_power(nhi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) icl_nhi_set_ltr(nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void icl_nhi_shutdown(struct tb_nhi *nhi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) icl_nhi_force_power(nhi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct tb_nhi_ops icl_nhi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .init = icl_nhi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .suspend_noirq = icl_nhi_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .resume_noirq = icl_nhi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .runtime_suspend = icl_nhi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .runtime_resume = icl_nhi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .shutdown = icl_nhi_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags