^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Thunderbolt driver - NHI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef DSL3510_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DSL3510_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/thunderbolt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum nhi_fw_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) NHI_FW_SAFE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) NHI_FW_AUTH_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) NHI_FW_EP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) NHI_FW_CM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum nhi_mailbox_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) NHI_MAILBOX_SAVE_DEVS = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) NHI_MAILBOX_DRV_UNLOADS = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) NHI_MAILBOX_DISCONNECT_PA = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) NHI_MAILBOX_DISCONNECT_PB = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * struct tb_nhi_ops - NHI specific optional operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @init: NHI specific initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @suspend_noirq: NHI specific suspend_noirq hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @resume_noirq: NHI specific resume_noirq hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @runtime_suspend: NHI specific runtime_suspend hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @runtime_resume: NHI specific runtime_resume hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @shutdown: NHI specific shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct tb_nhi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int (*init)(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int (*resume_noirq)(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int (*runtime_suspend)(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int (*runtime_resume)(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void (*shutdown)(struct tb_nhi *nhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern const struct tb_nhi_ops icl_nhi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * PCI IDs used in this driver from Win Ridge forward. There is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * need for the PCI quirk anymore as we will use ICM also on Apple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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