^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ZTE's zx2967 family thermal sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 ZTE Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Baoyou Xie <baoyou.xie@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Power Mode: 0->low 1->high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ZX2967_THERMAL_POWER_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ZX2967_POWER_MODE_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZX2967_POWER_MODE_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* DCF Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZX2967_THERMAL_DCF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZX2967_DCF_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZX2967_DCF_FREEZE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Selection Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ZX2967_THERMAL_SEL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ZX2967_THERMAL_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ZX2967_THERMAL_READY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZX2967_THERMAL_TEMP_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZX2967_THERMAL_ID_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZX2967_THERMAL_ID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * struct zx2967_thermal_priv - zx2967 thermal sensor private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @tzd: struct thermal_zone_device where the sensor is registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @lock: prevents read sensor in parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @clk_topcrm: topcrm clk structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @clk_apb: apb clk structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @regs: pointer to base address of the thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @dev: struct device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct zx2967_thermal_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk_topcrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk_apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int zx2967_thermal_get_temp(void *data, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct zx2967_thermal_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!priv->tzd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel_relaxed(ZX2967_POWER_MODE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regs + ZX2967_THERMAL_POWER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMAL_DCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = readl_relaxed(regs + ZX2967_THERMAL_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val &= ~ZX2967_THERMAL_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val |= ZX2967_THERMAL_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(val, regs + ZX2967_THERMAL_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Must wait for a while, surely it's a bit odd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * otherwise temperature value we got has a few deviation, even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * the THERMAL_READY bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) usleep_range(100, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = readx_poll_timeout(readl, regs + ZX2967_THERMAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val, val & ZX2967_THERMAL_READY, 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ZX2967_GET_TEMP_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(priv->dev, "Thermal sensor data timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel_relaxed(ZX2967_DCF_FREEZE | ZX2967_DCF_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) regs + ZX2967_THERMAL_DCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = readl_relaxed(regs + ZX2967_THERMAL_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) & ZX2967_THERMAL_TEMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(ZX2967_POWER_MODE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regs + ZX2967_THERMAL_POWER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Calculate temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * In dts, slope is multiplied by 1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *temp = DIV_ROUND_CLOSEST(((s32)val + priv->tzd->tzp->offset) * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) priv->tzd->tzp->slope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct thermal_zone_of_device_ops zx2967_of_thermal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .get_temp = zx2967_thermal_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int zx2967_thermal_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct zx2967_thermal_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) priv->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (IS_ERR(priv->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return PTR_ERR(priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) priv->clk_topcrm = devm_clk_get(&pdev->dev, "topcrm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (IS_ERR(priv->clk_topcrm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = PTR_ERR(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(&pdev->dev, "failed to get topcrm clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = clk_prepare_enable(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(&pdev->dev, "failed to enable topcrm clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) priv->clk_apb = devm_clk_get(&pdev->dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(priv->clk_apb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = PTR_ERR(priv->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(&pdev->dev, "failed to get apb clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto disable_clk_topcrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = clk_prepare_enable(priv->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(&pdev->dev, "failed to enable apb clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto disable_clk_topcrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) priv->tzd = thermal_zone_of_sensor_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0, priv, &zx2967_of_thermal_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (IS_ERR(priv->tzd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = PTR_ERR(priv->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(&pdev->dev, "failed to register sensor: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto disable_clk_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (priv->tzd->tzp->slope == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) thermal_zone_of_sensor_unregister(&pdev->dev, priv->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(&pdev->dev, "coefficients of sensor is invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto disable_clk_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) disable_clk_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk_disable_unprepare(priv->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) disable_clk_topcrm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk_disable_unprepare(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int zx2967_thermal_exit(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct zx2967_thermal_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) thermal_zone_of_sensor_unregister(&pdev->dev, priv->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clk_disable_unprepare(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clk_disable_unprepare(priv->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct of_device_id zx2967_thermal_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .compatible = "zte,zx296718-thermal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_DEVICE_TABLE(of, zx2967_thermal_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int zx2967_thermal_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct zx2967_thermal_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (priv && priv->clk_topcrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk_disable_unprepare(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (priv && priv->clk_apb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk_disable_unprepare(priv->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int zx2967_thermal_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct zx2967_thermal_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) error = clk_prepare_enable(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) error = clk_prepare_enable(priv->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk_disable_unprepare(priv->clk_topcrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static SIMPLE_DEV_PM_OPS(zx2967_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) zx2967_thermal_suspend, zx2967_thermal_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct platform_driver zx2967_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .probe = zx2967_thermal_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .remove = zx2967_thermal_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "zx2967_thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .of_match_table = zx2967_thermal_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .pm = &zx2967_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) module_platform_driver(zx2967_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DESCRIPTION("ZTE zx2967 thermal driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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