Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * uniphier_thermal.c - Socionext UniPhier thermal driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2014      Panasonic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2016-2017 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "thermal_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * block registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * addresses are the offset from .block_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PVTCTLEN			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PVTCTLEN_EN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PVTCTLMODE			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PVTCTLMODE_MASK			0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PVTCTLMODE_TEMPMON		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define EMONREPEAT			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EMONREPEAT_ENDLESS		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EMONREPEAT_PERIOD		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EMONREPEAT_PERIOD_1000000	0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * common registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * addresses are the offset from .map_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PVTCTLSEL			0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PVTCTLSEL_MASK			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PVTCTLSEL_MONITOR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SETALERT0			0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SETALERT1			0x0914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SETALERT2			0x0918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SETALERT_TEMP_OVF		(GENMASK(7, 0) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SETALERT_TEMP_OVF_VALUE(val)	(((val) & GENMASK(7, 0)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SETALERT_EN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PMALERTINTCTL			0x0920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PMALERTINTCTL_CLR(ch)		BIT(4 * (ch) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PMALERTINTCTL_SET(ch)		BIT(4 * (ch) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PMALERTINTCTL_EN(ch)		BIT(4 * (ch) + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PMALERTINTCTL_MASK		(GENMASK(10, 8) | GENMASK(6, 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					 GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TMOD				0x0928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TMOD_WIDTH			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TMODCOEF			0x0e5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TMODSETUP0_EN			BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TMODSETUP0_VAL(val)		(((val) & GENMASK(13, 0)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TMODSETUP1_EN			BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TMODSETUP1_VAL(val)		((val) & GENMASK(14, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* SoC critical temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CRITICAL_TEMP_LIMIT		(120 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Max # of alert channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define ALERT_CH_NUM			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* SoC specific thermal sensor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) struct uniphier_tm_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 block_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 tmod_setup_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct uniphier_tm_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	bool alert_en[ALERT_CH_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct thermal_zone_device *tz_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	const struct uniphier_tm_soc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int uniphier_tm_initialize_sensor(struct uniphier_tm_dev *tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct regmap *map = tdev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 tmod_calib[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* stop PVT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			  PVTCTLEN_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * Since SoC has a calibrated value that was set in advance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * TMODCOEF shows non-zero and PVT refers the value internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * If TMODCOEF shows zero, the boards don't have the calibrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * value, and the driver has to set default value from DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (!val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		/* look for the default values in DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		ret = of_property_read_u32_array(tdev->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 						 "socionext,tmod-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 						 tmod_calib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 						 ARRAY_SIZE(tmod_calib));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		regmap_write(map, tdev->data->tmod_setup_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			TMODSETUP0_EN | TMODSETUP0_VAL(tmod_calib[0]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			TMODSETUP1_EN | TMODSETUP1_VAL(tmod_calib[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* select temperature mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	regmap_write_bits(map, tdev->data->block_base + PVTCTLMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			  PVTCTLMODE_MASK, PVTCTLMODE_TEMPMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* set monitoring period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	regmap_write_bits(map, tdev->data->block_base + EMONREPEAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			  EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			  EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD_1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* set monitor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	regmap_write_bits(map, tdev->data->map_base + PVTCTLSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			  PVTCTLSEL_MASK, PVTCTLSEL_MONITOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void uniphier_tm_set_alert(struct uniphier_tm_dev *tdev, u32 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				  u32 temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct regmap *map = tdev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* set alert temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	regmap_write_bits(map, tdev->data->map_base + SETALERT0 + (ch << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			  SETALERT_EN | SETALERT_TEMP_OVF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			  SETALERT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			  SETALERT_TEMP_OVF_VALUE(temp / 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void uniphier_tm_enable_sensor(struct uniphier_tm_dev *tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct regmap *map = tdev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	for (i = 0; i < ALERT_CH_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (tdev->alert_en[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			bits |= PMALERTINTCTL_EN(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* enable alert interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			  PMALERTINTCTL_MASK, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* start PVT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			  PVTCTLEN_EN, PVTCTLEN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	usleep_range(700, 1500);	/* The spec note says at least 700us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void uniphier_tm_disable_sensor(struct uniphier_tm_dev *tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct regmap *map = tdev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* disable alert interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			  PMALERTINTCTL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* stop PVT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			  PVTCTLEN_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	usleep_range(1000, 2000);	/* The spec note says at least 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int uniphier_tm_get_temp(void *data, int *out_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct uniphier_tm_dev *tdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct regmap *map = tdev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = regmap_read(map, tdev->data->map_base + TMOD, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* MSB of the TMOD field is a sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	*out_temp = sign_extend32(temp, TMOD_WIDTH - 1) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct thermal_zone_of_device_ops uniphier_of_thermal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.get_temp = uniphier_tm_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void uniphier_tm_irq_clear(struct uniphier_tm_dev *tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 mask = 0, bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	for (i = 0; i < ALERT_CH_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		mask |= (PMALERTINTCTL_CLR(i) | PMALERTINTCTL_SET(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		bits |= PMALERTINTCTL_CLR(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* clear alert interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	regmap_write_bits(tdev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			  tdev->data->map_base + PMALERTINTCTL, mask, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static irqreturn_t uniphier_tm_alarm_irq(int irq, void *_tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct uniphier_tm_dev *tdev = _tdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	uniphier_tm_irq_clear(tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static irqreturn_t uniphier_tm_alarm_irq_thread(int irq, void *_tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct uniphier_tm_dev *tdev = _tdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	thermal_zone_device_update(tdev->tz_dev, THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int uniphier_tm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct uniphier_tm_dev *tdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	const struct thermal_trip *trips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int i, ret, irq, ntrips, crit_temp = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	tdev = devm_kzalloc(dev, sizeof(*tdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	tdev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	tdev->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (WARN_ON(!tdev->data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* get regmap from syscon node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	parent = of_get_parent(dev->of_node); /* parent should be syscon node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	regmap = syscon_node_to_regmap(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dev_err(dev, "failed to get regmap (error %ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	tdev->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = uniphier_tm_initialize_sensor(tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		dev_err(dev, "failed to initialize sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ret = devm_request_threaded_irq(dev, irq, uniphier_tm_alarm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 					uniphier_tm_alarm_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 					0, "thermal", tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	platform_set_drvdata(pdev, tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	tdev->tz_dev = devm_thermal_zone_of_sensor_register(dev, 0, tdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 						&uniphier_of_thermal_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (IS_ERR(tdev->tz_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dev_err(dev, "failed to register sensor device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return PTR_ERR(tdev->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* get trip points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	trips = of_thermal_get_trip_points(tdev->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ntrips = of_thermal_get_ntrips(tdev->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (ntrips > ALERT_CH_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		dev_err(dev, "thermal zone has too many trips\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* set alert temperatures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	for (i = 0; i < ntrips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (trips[i].type == THERMAL_TRIP_CRITICAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		    trips[i].temperature < crit_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			crit_temp = trips[i].temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		uniphier_tm_set_alert(tdev, i, trips[i].temperature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		tdev->alert_en[i] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (crit_temp > CRITICAL_TEMP_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		dev_err(dev, "critical trip is over limit(>%d), or not set\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			CRITICAL_TEMP_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	uniphier_tm_enable_sensor(tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int uniphier_tm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct uniphier_tm_dev *tdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* disable sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	uniphier_tm_disable_sensor(tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct uniphier_tm_soc_data uniphier_pxs2_tm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.map_base        = 0xe000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.block_base      = 0xe000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.tmod_setup_addr = 0xe904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct uniphier_tm_soc_data uniphier_ld20_tm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.map_base        = 0xe000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.block_base      = 0xe800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.tmod_setup_addr = 0xe938,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct of_device_id uniphier_tm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.compatible = "socionext,uniphier-pxs2-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.data       = &uniphier_pxs2_tm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.compatible = "socionext,uniphier-ld20-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.data       = &uniphier_ld20_tm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.compatible = "socionext,uniphier-pxs3-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.data       = &uniphier_ld20_tm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DEVICE_TABLE(of, uniphier_tm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct platform_driver uniphier_tm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.probe = uniphier_tm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.remove = uniphier_tm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.name = "uniphier-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.of_match_table = uniphier_tm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) module_platform_driver(uniphier_tm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DESCRIPTION("UniPhier thermal driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_LICENSE("GPL v2");