^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP5xxx bandgap registers, bitfields and temperature definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Eduardo Valentin <eduardo.valentin@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __OMAP5XXX_BANDGAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __OMAP5XXX_BANDGAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * *** OMAP5430 ***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Below, in sequence, are the Register definitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the bitfields and the temperature definitions for OMAP5430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OMAP5430 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Registers are defined as offsets. The offsets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * relative to FUSE_OPP_BGAP_GPU on 5430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Register below are grouped by domain (not necessarily in offset order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* OMAP5430.GPU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* OMAP5430.MPU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* OMAP5430.MPU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* OMAP5430.common register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP5430_BGAP_STATUS_OFFSET 0x1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Register bitfields for OMAP5430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * All the macros bellow define the required bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * controlling temperature on OMAP5430. Bit defines are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * grouped by register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* OMAP5430.TEMP_SENSOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* OMAP5430.BANDGAP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP5430_MASK_COLD_GPU_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP5430_MASK_HOT_MPU_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP5430_MASK_COLD_MPU_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* OMAP5430.BANDGAP_COUNTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP5430_COUNTER_MASK (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* OMAP5430.BANDGAP_THRESHOLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP5430_T_HOT_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP5430_T_COLD_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* OMAP5430.TSHUT_THRESHOLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* OMAP5430.BANDGAP_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP5430_COLD_GPU_FLAG_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP5430_HOT_MPU_FLAG_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP5430_COLD_MPU_FLAG_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Temperature limits and thresholds for OMAP5430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * All the macros bellow are definitions for handling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * ADC conversions and representation of temperature limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * and thresholds for OMAP5430. Definitions are grouped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * by temperature domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* OMAP5430.common temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* ADC conversion table limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP5430_ADC_START_VALUE 540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP5430_ADC_END_VALUE 945
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* OMAP5430.GPU temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP5430_GPU_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP5430_GPU_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP5430_GPU_TSHUT_HOT 915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP5430_GPU_TSHUT_COLD 900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP5430_GPU_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP5430_GPU_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* OMAP5430.MPU temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP5430_MPU_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP5430_MPU_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP5430_MPU_TSHUT_HOT 915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP5430_MPU_TSHUT_COLD 900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP5430_MPU_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP5430_MPU_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* OMAP5430.CORE temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP5430_CORE_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP5430_CORE_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP5430_CORE_TSHUT_HOT 915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP5430_CORE_TSHUT_COLD 900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP5430_CORE_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP5430_CORE_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif /* __OMAP5XXX_BANDGAP_H */
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