^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP4xxx bandgap registers, bitfields and temperature definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Eduardo Valentin <eduardo.valentin@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __OMAP4XXX_BANDGAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __OMAP4XXX_BANDGAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * *** OMAP4430 ***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Below, in sequence, are the Register definitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the bitfields and the temperature definitions for OMAP4430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OMAP4430 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Registers are defined as offsets. The offsets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * relative to FUSE_OPP_BGAP on 4430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* OMAP4430.FUSE_OPP_BGAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP4430_FUSE_OPP_BGAP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* OMAP4430.TEMP_SENSOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4430_TEMP_SENSOR_CTRL_OFFSET 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Register and bit definitions for OMAP4430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * All the macros bellow define the required bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * controlling temperature on OMAP4430. Bit defines are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * grouped by register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* OMAP4430.TEMP_SENSOR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP4430_BGAP_TEMPSOFF_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP4430_BGAP_TSHUT_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP4430_SINGLE_MODE_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Temperature limits and thresholds for OMAP4430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * All the macros bellow are definitions for handling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * ADC conversions and representation of temperature limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * and thresholds for OMAP4430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * ADC conversion table limits. Ignore values outside the TRM listed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * range to avoid bogus thermal shutdowns. See omap4430 TRM chapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * "18.4.10.2.3 ADC Codes Versus Temperature".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4430_ADC_START_VALUE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4430_ADC_END_VALUE 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* bandgap clock limits (no control on 4430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP4430_MAX_FREQ 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP4430_MIN_FREQ 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * *** OMAP4460 *** Applicable for OMAP4470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Below, in sequence, are the Register definitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * the bitfields and the temperature definitions for OMAP4460.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * OMAP4460 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Registers are defined as offsets. The offsets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * relative to FUSE_OPP_BGAP on 4460.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* OMAP4460.FUSE_OPP_BGAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP4460_FUSE_OPP_BGAP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* OMAP4460.TEMP_SENSOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP4460_TEMP_SENSOR_CTRL_OFFSET 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* OMAP4460.BANDGAP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP4460_BGAP_CTRL_OFFSET 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* OMAP4460.BANDGAP_COUNTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP4460_BGAP_COUNTER_OFFSET 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* OMAP4460.BANDGAP_THRESHOLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP4460_BGAP_THRESHOLD_OFFSET 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* OMAP4460.TSHUT_THRESHOLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP4460_BGAP_TSHUT_OFFSET 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* OMAP4460.BANDGAP_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP4460_BGAP_STATUS_OFFSET 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Register bitfields for OMAP4460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * All the macros bellow define the required bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * controlling temperature on OMAP4460. Bit defines are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * grouped by register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* OMAP4460.TEMP_SENSOR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP4460_BGAP_TEMPSOFF_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* OMAP4460.BANDGAP_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP4460_SINGLE_MODE_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP4460_MASK_HOT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP4460_MASK_COLD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* OMAP4460.BANDGAP_COUNTER bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP4460_COUNTER_MASK (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* OMAP4460.BANDGAP_THRESHOLD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP4460_T_HOT_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP4460_T_COLD_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* OMAP4460.TSHUT_THRESHOLD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP4460_TSHUT_HOT_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* OMAP4460.BANDGAP_STATUS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP4460_HOT_FLAG_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP4460_COLD_FLAG_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Temperature limits and thresholds for OMAP4460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * All the macros bellow are definitions for handling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * ADC conversions and representation of temperature limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * and thresholds for OMAP4460.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* ADC conversion table limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP4460_ADC_START_VALUE 530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP4460_ADC_END_VALUE 932
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP4460_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP4460_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP4460_TSHUT_HOT 900 /* 122 deg C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP4460_TSHUT_COLD 895 /* 100 deg C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP4460_T_HOT 800 /* 73 deg C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP4460_T_COLD 795 /* 71 deg C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif /* __OMAP4XXX_BANDGAP_H */
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