Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRA752 thermal data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Contact:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Eduardo Valentin <eduardo.valentin@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This file is partially autogenerated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ti-thermal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "ti-bandgap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "dra752-bandgap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * IVA and DSPEVE need to describe the individual registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * bit fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * DRA752 CORE thermal sensor register offsets and bit-fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static struct temp_sensor_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) dra752_core_temp_sensor_registers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * DRA752 IVA thermal sensor register offsets and bit-fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct temp_sensor_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) dra752_iva_temp_sensor_registers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * DRA752 MPU thermal sensor register offsets and bit-fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static struct temp_sensor_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) dra752_mpu_temp_sensor_registers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * DRA752 DSPEVE thermal sensor register offsets and bit-fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct temp_sensor_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dra752_dspeve_temp_sensor_registers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * DRA752 GPU thermal sensor register offsets and bit-fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct temp_sensor_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dra752_gpu_temp_sensor_registers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Thresholds and limits for DRA752 MPU temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.t_hot = DRA752_MPU_T_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.t_cold = DRA752_MPU_T_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.min_freq = DRA752_MPU_MIN_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.max_freq = DRA752_MPU_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Thresholds and limits for DRA752 GPU temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.t_hot = DRA752_GPU_T_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.t_cold = DRA752_GPU_T_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.min_freq = DRA752_GPU_MIN_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.max_freq = DRA752_GPU_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Thresholds and limits for DRA752 CORE temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct temp_sensor_data dra752_core_temp_sensor_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.t_hot = DRA752_CORE_T_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.t_cold = DRA752_CORE_T_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.min_freq = DRA752_CORE_MIN_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.max_freq = DRA752_CORE_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Thresholds and limits for DRA752 DSPEVE temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.t_hot = DRA752_DSPEVE_T_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.t_cold = DRA752_DSPEVE_T_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.min_freq = DRA752_DSPEVE_MIN_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.max_freq = DRA752_DSPEVE_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Thresholds and limits for DRA752 IVA temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct temp_sensor_data dra752_iva_temp_sensor_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.t_hot = DRA752_IVA_T_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.t_cold = DRA752_IVA_T_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.min_freq = DRA752_IVA_MIN_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.max_freq = DRA752_IVA_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * DRA752 : Temperature values in milli degree celsius
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * ADC code values from 540 to 945
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Index 540 - 549 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	-40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	-37800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Index 550 - 559 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	-37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	-33400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Index 560 - 569 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	-33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	-29400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Index 570 - 579 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	-29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	-25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* Index 580 - 589 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	-24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	-21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* Index 590 - 599 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	-20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	-16600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* Index 600 - 609 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	-16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	-12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* Index 610 - 619 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	-11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	-8200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Index 620 - 629 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	-7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	-3900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Index 630 - 639 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	-3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* Index 640 - 649 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* Index 650 - 659 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	8600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Index 660 - 669 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	12700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* Index 670 - 679 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	17000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* Index 680 - 689 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Index 690 - 699 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	25400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Index 700 - 709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	29400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* Index 710 - 719 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	33800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* Index 720 - 729 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	37800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Index 730 - 739 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	41800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* Index 740 - 749 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	46200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Index 750 - 759 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	50200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* Index 760 - 769 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	54200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* Index 770 - 779 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	58600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* Index 780 - 789 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	62600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* Index 790 - 799 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	66600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Index 800 - 809 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	70600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Index 810 - 819 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	75000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/* Index 820 - 829 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	79000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* Index 830 - 839 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	83000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Index 840 - 849 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	87000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Index 850 - 859 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	91000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Index 860 - 869 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Index 870 - 879 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	99400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* Index 880 - 889 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	103400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* Index 890 - 899 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	107400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Index 900 - 909 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	111400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* Index 910 - 919 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	115400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* Index 920 - 929 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	119400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/* Index 930 - 939 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	123400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* Index 940 - 945 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	123800, 124200, 124600, 124900, 125000, 125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* DRA752 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const struct ti_bandgap_data dra752_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.features = TI_BANDGAP_FEATURE_FREEZE_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			TI_BANDGAP_FEATURE_TALERT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			TI_BANDGAP_FEATURE_COUNTER_DELAY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			TI_BANDGAP_FEATURE_HISTORY_BUFFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			TI_BANDGAP_FEATURE_ERRATA_814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.fclock_name = "l3instr_ts_gclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.div_ck_name = "l3instr_ts_gclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.conv_table = dra752_adc_to_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.adc_start_val = DRA752_ADC_START_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.adc_end_val = DRA752_ADC_END_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.expose_sensor = ti_thermal_expose_sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.remove_sensor = ti_thermal_remove_sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.sensors = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.registers = &dra752_mpu_temp_sensor_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.ts_data = &dra752_mpu_temp_sensor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.domain = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.register_cooling = ti_thermal_register_cpu_cooling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.unregister_cooling = ti_thermal_unregister_cpu_cooling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.registers = &dra752_gpu_temp_sensor_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.ts_data = &dra752_gpu_temp_sensor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.domain = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.registers = &dra752_core_temp_sensor_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.ts_data = &dra752_core_temp_sensor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.domain = "core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.registers = &dra752_dspeve_temp_sensor_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.ts_data = &dra752_dspeve_temp_sensor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.domain = "dspeve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.registers = &dra752_iva_temp_sensor_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.ts_data = &dra752_iva_temp_sensor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.domain = "iva",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.sensor_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };