^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRA752 bandgap registers, bitfields and temperature definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Eduardo Valentin <eduardo.valentin@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This is an auto generated file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DRA752_BANDGAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DRA752_BANDGAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * *** DRA752 ***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Below, in sequence, are the Register definitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the bitfields and the temperature definitions for DRA752.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * DRA752 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Registers are defined as offsets. The offsets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * relative to FUSE_OPP_BGAP_GPU on DRA752.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * DRA752_BANDGAP_BASE 0x4a0021e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Register below are grouped by domain (not necessarily in offset order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* DRA752.common register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* DRA752.core register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRA752_DTEMP_CORE_1_OFFSET 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRA752_DTEMP_CORE_2_OFFSET 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* DRA752.iva register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* DRA752.mpu register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* DRA752.dspeve register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* DRA752.gpu register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Register bitfields for DRA752
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * All the macros bellow define the required bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * controlling temperature on DRA752. Bit defines are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * grouped by register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* DRA752.BANDGAP_STATUS_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* DRA752.BANDGAP_CTRL_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* DRA752.BANDGAP_STATUS_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* DRA752.BANDGAP_CTRL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* DRA752.TEMP_SENSOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* DRA752.BANDGAP_THRESHOLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Temperature limits and thresholds for DRA752
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * All the macros bellow are definitions for handling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * ADC conversions and representation of temperature limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * and thresholds for DRA752. Definitions are grouped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * by temperature domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* DRA752.common temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* ADC conversion table limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DRA752_ADC_START_VALUE 540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRA752_ADC_END_VALUE 945
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* DRA752.GPU temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DRA752_GPU_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRA752_GPU_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DRA752_GPU_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRA752_GPU_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* DRA752.MPU temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DRA752_MPU_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRA752_MPU_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRA752_MPU_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRA752_MPU_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* DRA752.CORE temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DRA752_CORE_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRA752_CORE_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DRA752_CORE_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRA752_CORE_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* DRA752.DSPEVE temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRA752_DSPEVE_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRA752_DSPEVE_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRA752_DSPEVE_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DRA752_DSPEVE_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* DRA752.IVA temperature definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* bandgap clock limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DRA752_IVA_MAX_FREQ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRA752_IVA_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* interrupts thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DRA752_IVA_T_HOT 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DRA752_IVA_T_COLD 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif /* __DRA752_BANDGAP_H */
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