^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/thermal/tegra124-soctherm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "soctherm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA210_THRESH_GRAIN 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA210_BPTT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct tegra_tsensor_configuration tegra210_tsensor_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .tall = 16300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .tiddq_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .ten_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .tsample = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .tsample_ate = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .id = TEGRA124_SOCTHERM_SENSOR_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .sensor_temp_offset = SENSOR_TEMP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .pdiv_mask = SENSOR_PDIV_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pllx_hotspot_diff = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .id = TEGRA124_SOCTHERM_SENSOR_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .sensor_temp_offset = SENSOR_TEMP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pdiv_mask = SENSOR_PDIV_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pllx_hotspot_diff = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct tegra_tsensor_group tegra210_tsensor_group_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .sensor_temp_offset = SENSOR_TEMP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct tegra_tsensor_group tegra210_tsensor_group_mem = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .id = TEGRA124_SOCTHERM_SENSOR_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .sensor_temp_offset = SENSOR_TEMP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pdiv_mask = SENSOR_PDIV_MEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pllx_hotspot_diff = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &tegra210_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &tegra210_tsensor_group_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &tegra210_tsensor_group_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &tegra210_tsensor_group_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct tegra_tsensor tegra210_tsensors[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .base = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .calib_fuse_offset = 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .fuse_corr_alpha = 1085000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .fuse_corr_beta = 3244200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .group = &tegra210_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .base = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .calib_fuse_offset = 0x084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .fuse_corr_alpha = 1126200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .fuse_corr_beta = -67500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .group = &tegra210_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .base = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .calib_fuse_offset = 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .fuse_corr_alpha = 1098400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .fuse_corr_beta = 2251100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .group = &tegra210_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .base = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .calib_fuse_offset = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .fuse_corr_alpha = 1108000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .fuse_corr_beta = 602700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .group = &tegra210_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .base = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .calib_fuse_offset = 0x158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .fuse_corr_alpha = 1069200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .fuse_corr_beta = 3549900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .group = &tegra210_tsensor_group_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .base = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .calib_fuse_offset = 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .fuse_corr_alpha = 1173700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .fuse_corr_beta = -6263600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .group = &tegra210_tsensor_group_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .base = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .calib_fuse_offset = 0x154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .fuse_corr_alpha = 1074300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .fuse_corr_beta = 2734900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .group = &tegra210_tsensor_group_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .base = 0x1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .config = &tegra210_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .calib_fuse_offset = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .fuse_corr_alpha = 1039700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .fuse_corr_beta = 6829100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .group = &tegra210_tsensor_group_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Mask/shift bits in FUSE_TSENSOR_COMMON and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * FUSE_TSENSOR_COMMON, which are described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * tegra_soctherm_fuse.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .fuse_base_cp_mask = 0x3ff << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .fuse_base_cp_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .fuse_base_ft_mask = 0x7ff << 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .fuse_base_ft_shift = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .fuse_shift_ft_mask = 0x1f << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .fuse_shift_ft_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .fuse_spare_realignment = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const struct tegra_soctherm_soc tegra210_soctherm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .tsensors = tegra210_tsensors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .num_tsensors = ARRAY_SIZE(tegra210_tsensors),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .ttgs = tegra210_tsensor_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .tfuse = &tegra210_soctherm_fuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .thresh_grain = TEGRA210_THRESH_GRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .bptt = TEGRA210_BPTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .use_ccroc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .thermtrips = tegra210_tsensor_thermtrips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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