^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/thermal/tegra124-soctherm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "soctherm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA124_THERMTRIP_ANY_EN_MASK (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA124_THERMTRIP_MEM_EN_MASK (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA124_THERMTRIP_GPU_EN_MASK (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA124_THERMTRIP_CPU_EN_MASK (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA124_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA124_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA124_THRESH_GRAIN 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA124_BPTT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct tegra_tsensor_configuration tegra124_tsensor_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .tall = 16300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .tiddq_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ten_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .tsample = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .tsample_ate = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .id = TEGRA124_SOCTHERM_SENSOR_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .sensor_temp_offset = SENSOR_TEMP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .pdiv_mask = SENSOR_PDIV_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .pllx_hotspot_diff = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .id = TEGRA124_SOCTHERM_SENSOR_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .sensor_temp_offset = SENSOR_TEMP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .pdiv_mask = SENSOR_PDIV_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pllx_hotspot_diff = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .sensor_temp_offset = SENSOR_TEMP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .id = TEGRA124_SOCTHERM_SENSOR_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .sensor_temp_offset = SENSOR_TEMP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .pdiv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pdiv_ate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pdiv_mask = SENSOR_PDIV_MEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pllx_hotspot_diff = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &tegra124_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &tegra124_tsensor_group_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &tegra124_tsensor_group_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &tegra124_tsensor_group_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct tegra_tsensor tegra124_tsensors[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .base = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .calib_fuse_offset = 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .fuse_corr_alpha = 1135400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .fuse_corr_beta = -6266900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .group = &tegra124_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .base = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .calib_fuse_offset = 0x084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .fuse_corr_alpha = 1122220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .fuse_corr_beta = -5700700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .group = &tegra124_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .base = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .calib_fuse_offset = 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .fuse_corr_alpha = 1127000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .fuse_corr_beta = -6768200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .group = &tegra124_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .base = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .calib_fuse_offset = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .fuse_corr_alpha = 1110900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .fuse_corr_beta = -6232000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .group = &tegra124_tsensor_group_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .base = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .calib_fuse_offset = 0x158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .fuse_corr_alpha = 1122300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .fuse_corr_beta = -5936400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .group = &tegra124_tsensor_group_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .base = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .calib_fuse_offset = 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .fuse_corr_alpha = 1145700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .fuse_corr_beta = -7124600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .group = &tegra124_tsensor_group_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .base = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .calib_fuse_offset = 0x154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .fuse_corr_alpha = 1120100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .fuse_corr_beta = -6000500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .group = &tegra124_tsensor_group_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .base = 0x1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .config = &tegra124_tsensor_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .calib_fuse_offset = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .fuse_corr_alpha = 1106500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .fuse_corr_beta = -6729300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .group = &tegra124_tsensor_group_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Mask/shift bits in FUSE_TSENSOR_COMMON and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * FUSE_TSENSOR_COMMON, which are described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * tegra_soctherm_fuse.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .fuse_base_cp_mask = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .fuse_base_cp_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .fuse_base_ft_mask = 0x7ff << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .fuse_base_ft_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .fuse_shift_ft_mask = 0x1f << 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .fuse_shift_ft_shift = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .fuse_spare_realignment = 0x1fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct tegra_soctherm_soc tegra124_soctherm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .tsensors = tegra124_tsensors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .num_tsensors = ARRAY_SIZE(tegra124_tsensors),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ttgs = tegra124_tsensor_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .tfuse = &tegra124_soctherm_fuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .thresh_grain = TEGRA124_THRESH_GRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .bptt = TEGRA124_BPTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .use_ccroc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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