^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define THERMCTL_LEVEL0_GROUP_CPU 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define THERMCTL_LEVEL0_GROUP_GPU 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define THERMCTL_LEVEL0_GROUP_MEM 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define THERMCTL_LEVEL0_GROUP_TSENSE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SENSOR_CONFIG2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SENSOR_CONFIG2_THERMA_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SENSOR_CONFIG2_THERMA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SENSOR_CONFIG2_THERMB_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SENSOR_CONFIG2_THERMB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define THERMCTL_THERMTRIP_CTL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* BITs are defined in device file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define THERMCTL_INTR_ENABLE 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define THERMCTL_INTR_DISABLE 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TH_INTR_UP_DN_EN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define THERM_IRQ_MEM_MASK (TH_INTR_UP_DN_EN << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define THERM_IRQ_GPU_MASK (TH_INTR_UP_DN_EN << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define THERM_IRQ_CPU_MASK (TH_INTR_UP_DN_EN << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define THERM_IRQ_TSENSE_MASK (TH_INTR_UP_DN_EN << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SENSOR_PDIV 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SENSOR_PDIV_CPU_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SENSOR_PDIV_GPU_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SENSOR_PDIV_MEM_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SENSOR_HOTSPOT_OFF 0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SENSOR_TEMP1 0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SENSOR_TEMP2 0x1cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * struct tegra_tsensor_group - SOC_THERM sensor group data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @name: short name of the temperature sensor group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @id: numeric ID of the temperature sensor group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @sensor_temp_offset: offset of the SENSOR_TEMP* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @pdiv: the sensor count post-divider to use during runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @pdiv_ate: the sensor count post-divider used during automated test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PLLX sensor group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct tegra_tsensor_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 sensor_temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 sensor_temp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 pdiv, pdiv_ate, pdiv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 pllx_hotspot_diff, pllx_hotspot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 thermtrip_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 thermtrip_any_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 thermtrip_threshold_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 thermctl_isr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 thermctl_lvl0_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 thermctl_lvl0_up_thresh_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 thermctl_lvl0_dn_thresh_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tegra_tsensor_configuration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct tegra_tsensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct tegra_tsensor_configuration *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const u32 calib_fuse_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Correction values used to modify values read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * calibration fuses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const s32 fuse_corr_alpha, fuse_corr_beta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct tegra_tsensor_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct tsensor_group_thermtrips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct tegra_soctherm_fuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 fuse_base_cp_mask, fuse_base_cp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 fuse_base_ft_mask, fuse_base_ft_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 fuse_spare_realignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct tsensor_shared_calib {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 base_cp, base_ft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 actual_temp_cp, actual_temp_ft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct tegra_soctherm_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct tegra_tsensor *tsensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const unsigned int num_tsensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct tegra_tsensor_group **ttgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const unsigned int num_ttgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct tegra_soctherm_fuse *tfuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const int thresh_grain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const unsigned int bptt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const bool use_ccroc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct tsensor_group_thermtrips *thermtrips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct tsensor_shared_calib *shared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct tsensor_shared_calib *shared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 *calib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_ARCH_TEGRA_124_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern const struct tegra_soctherm_soc tegra124_soctherm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_ARCH_TEGRA_132_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) extern const struct tegra_soctherm_soc tegra132_soctherm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_ARCH_TEGRA_210_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern const struct tegra_soctherm_soc tegra210_soctherm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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