^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Thermal sensor driver for Allwinner SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Yangtao Li
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on the work of Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the work of Ondrej Jirman <megous@megous.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on the work of Josef Gajdusek <atx@atx.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "thermal_hwmon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_SENSOR_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FT_TEMP_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEMP_CALIB_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CALIBRATE_DEFAULT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUN8I_THS_CTRL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN8I_THS_CTRL2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN8I_THS_IC 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN8I_THS_IS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN8I_THS_MFC 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN8I_THS_TEMP_CALIB 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUN8I_THS_TEMP_DATA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN50I_THS_CTRL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN50I_H6_THS_ENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUN50I_H6_THS_PC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUN50I_H6_THS_DIC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUN50I_H6_THS_DIS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUN50I_H6_THS_MFC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUN50I_H6_THS_TEMP_CALIB 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN50I_H6_THS_TEMP_DATA 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN50I_THS_FILTER_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* millidegree celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct tsensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ths_device *tmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ths_thermal_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool has_mod_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool has_bus_clk_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int sensor_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ft_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int temp_data_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int (*calibrate)(struct ths_device *tmdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 *caldata, int callen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int (*init)(struct ths_device *tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int (*irq_ack)(struct ths_device *tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int (*calc_temp)(struct ths_device *tmdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int id, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct ths_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct ths_thermal_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk *mod_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct tsensor sensor[MAX_SENSOR_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Temp Unit: millidegree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int sun8i_ths_calc_temp(struct ths_device *tmdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return tmdev->chip->offset - (reg * tmdev->chip->scale / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int sun50i_h5_calc_temp(struct ths_device *tmdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (reg >= 0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -1191 * reg / 10 + 223000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -1452 * reg / 10 + 259000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -1590 * reg / 10 + 276000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int sun8i_ths_get_temp(void *data, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct tsensor *s = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ths_device *tmdev = s->tmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_read(tmdev->regmap, tmdev->chip->temp_data_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x4 * s->id, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* ths have no data yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *temp = tmdev->chip->calc_temp(tmdev, s->id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * According to the original sdk, there are some platforms(rarely)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * that add a fixed offset value after calculating the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * value. We can't simply put it on the formula for calculating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * temperature above, because the formula for calculating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * temperature above is also used when the sensor is calibrated. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * do this, the correct calibration formula is hard to know.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *temp += tmdev->chip->ft_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct thermal_zone_of_device_ops ths_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .get_temp = sun8i_ths_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct regmap_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .max_register = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int sun8i_h3_irq_ack(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int i, state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_read(tmdev->regmap, SUN8I_THS_IS, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (i = 0; i < tmdev->chip->sensor_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (state & SUN8I_THS_DATA_IRQ_STS(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regmap_write(tmdev->regmap, SUN8I_THS_IS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SUN8I_THS_DATA_IRQ_STS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int sun50i_h6_irq_ack(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int i, state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (i = 0; i < tmdev->chip->sensor_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SUN50I_H6_THS_DATA_IRQ_STS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static irqreturn_t sun8i_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct ths_device *tmdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i, state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) state = tmdev->chip->irq_ack(tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (i = 0; i < tmdev->chip->sensor_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (state & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) thermal_zone_device_update(tmdev->sensor[i].tzd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int sun8i_h3_ths_calibrate(struct ths_device *tmdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u16 *caldata, int callen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for (i = 0; i < tmdev->chip->sensor_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int offset = (i % 2) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_update_bits(tmdev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0xfff << offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) caldata[i] << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u16 *caldata, int callen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct device *dev = tmdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int i, ft_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * efuse layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 0 11 16 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * +-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * |temp| |sensor0|sensor1|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * +-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * The calibration data on the H6 is the ambient temperature and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * sensor values that are filled during the factory test stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * The unit of stored FT temperature is 0.1 degreee celusis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * We need to calculate a delta between measured and caluclated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * register values and this will become a calibration offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < tmdev->chip->sensor_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int cdata, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Calibration data is CALIBRATE_DEFAULT - (calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * temperature from sensor reading at factory temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * minus actual factory temperature) * 14.88 (scale from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * temperature to register values)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cdata = CALIBRATE_DEFAULT -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ((sensor_temp - ft_temp) * 10 / tmdev->chip->scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (cdata & ~TEMP_CALIB_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Calibration value more than 12-bit, but calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * register is 12-bit. In this case, ths hardware can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * still work without calibration, although the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * won't be so accurate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_warn(dev, "sensor%d is not calibrated.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) offset = (i % 2) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) regmap_update_bits(tmdev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0xfff << offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cdata << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int sun8i_ths_calibrate(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct nvmem_cell *calcell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct device *dev = tmdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 *caldata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) size_t callen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) calcell = devm_nvmem_cell_get(dev, "calibration");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(calcell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (PTR_ERR(calcell) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Even if the external calibration data stored in sid is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * not accessible, the THS hardware can still work, although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * the data won't be so accurate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * The default value of calibration register is 0x800 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * every sensor, and the calibration value is usually 0x7xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * or 0x8xx, so they won't be away from the default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * for a lot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * So here we do not return error if the calibartion data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * not available, except the probe needs deferring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) caldata = nvmem_cell_read(calcell, &callen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (IS_ERR(caldata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = PTR_ERR(caldata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tmdev->chip->calibrate(tmdev, caldata, callen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) kfree(caldata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int sun8i_ths_resource_init(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct device *dev = tmdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tmdev->regmap = devm_regmap_init_mmio(dev, base, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (IS_ERR(tmdev->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return PTR_ERR(tmdev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (tmdev->chip->has_bus_clk_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tmdev->reset = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (IS_ERR(tmdev->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return PTR_ERR(tmdev->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tmdev->bus_clk = devm_clk_get(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (IS_ERR(tmdev->bus_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return PTR_ERR(tmdev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (tmdev->chip->has_mod_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (IS_ERR(tmdev->mod_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return PTR_ERR(tmdev->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = reset_control_deassert(tmdev->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = clk_prepare_enable(tmdev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto assert_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = clk_set_rate(tmdev->mod_clk, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) goto bus_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = clk_prepare_enable(tmdev->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto bus_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = sun8i_ths_calibrate(tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto mod_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mod_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clk_disable_unprepare(tmdev->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bus_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk_disable_unprepare(tmdev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) assert_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) reset_control_assert(tmdev->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int sun8i_h3_thermal_init(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* average over 4 samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) regmap_write(tmdev->regmap, SUN8I_THS_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SUN50I_THS_FILTER_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SUN50I_THS_FILTER_TYPE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * clkin = 24MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * filter_samples = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * period = 0.25s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * x = period * clkin / 4096 / filter_samples - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * = 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) val = GENMASK(7 + tmdev->chip->sensor_num, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regmap_write(tmdev->regmap, SUN8I_THS_IC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SUN50I_H6_THS_PC_TEMP_PERIOD(365) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * T_acq = 20us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * clkin = 24MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * x = T_acq * clkin - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * = 479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regmap_write(tmdev->regmap, SUN8I_THS_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SUN8I_THS_CTRL0_T_ACQ0(479));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val = GENMASK(tmdev->chip->sensor_num - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regmap_write(tmdev->regmap, SUN8I_THS_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SUN8I_THS_CTRL2_T_ACQ1(479) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Without this undocummented value, the returned temperatures would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * be higher than real ones by about 20C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SUN50I_H6_CTRL0_UNK 0x0000002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int sun50i_h6_thermal_init(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * T_acq = 20us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * clkin = 24MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * x = T_acq * clkin - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * = 479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* average over 4 samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SUN50I_THS_FILTER_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SUN50I_THS_FILTER_TYPE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * clkin = 24MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * filter_samples = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * period = 0.25s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * x = period * clkin / 4096 / filter_samples - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * = 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) regmap_write(tmdev->regmap, SUN50I_H6_THS_PC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SUN50I_H6_THS_PC_TEMP_PERIOD(365));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* enable sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val = GENMASK(tmdev->chip->sensor_num - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* thermal data interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val = GENMASK(tmdev->chip->sensor_num - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int sun8i_ths_register(struct ths_device *tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (i = 0; i < tmdev->chip->sensor_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tmdev->sensor[i].tmdev = tmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tmdev->sensor[i].id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) tmdev->sensor[i].tzd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) devm_thermal_zone_of_sensor_register(tmdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &tmdev->sensor[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &ths_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(tmdev->sensor[i].tzd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return PTR_ERR(tmdev->sensor[i].tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_warn(tmdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "Failed to add hwmon sysfs attributes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int sun8i_ths_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct ths_device *tmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tmdev = devm_kzalloc(dev, sizeof(*tmdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!tmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tmdev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tmdev->chip = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!tmdev->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) platform_set_drvdata(pdev, tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = sun8i_ths_resource_init(tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = tmdev->chip->init(tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = sun8i_ths_register(tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Avoid entering the interrupt handler, the thermal device is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * registered yet, we deffer the registration of the interrupt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = devm_request_threaded_irq(dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sun8i_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) IRQF_ONESHOT, "ths", tmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int sun8i_ths_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ths_device *tmdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clk_disable_unprepare(tmdev->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk_disable_unprepare(tmdev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) reset_control_assert(tmdev->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct ths_thermal_chip sun8i_a83t_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .sensor_num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .scale = 705,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .offset = 191668,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .temp_data_base = SUN8I_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .calibrate = sun8i_h3_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .init = sun8i_h3_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .irq_ack = sun8i_h3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .calc_temp = sun8i_ths_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const struct ths_thermal_chip sun8i_h3_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .sensor_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .scale = 1211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .offset = 217000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .has_mod_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .has_bus_clk_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .temp_data_base = SUN8I_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .calibrate = sun8i_h3_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .init = sun8i_h3_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .irq_ack = sun8i_h3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .calc_temp = sun8i_ths_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct ths_thermal_chip sun8i_r40_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .sensor_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .offset = 251086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .scale = 1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .has_mod_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .has_bus_clk_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .temp_data_base = SUN8I_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .calibrate = sun8i_h3_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .init = sun8i_h3_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .irq_ack = sun8i_h3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .calc_temp = sun8i_ths_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct ths_thermal_chip sun50i_a64_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .sensor_num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .offset = 260890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .scale = 1170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .has_mod_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .has_bus_clk_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .temp_data_base = SUN8I_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .calibrate = sun8i_h3_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .init = sun8i_h3_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .irq_ack = sun8i_h3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .calc_temp = sun8i_ths_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct ths_thermal_chip sun50i_a100_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .sensor_num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .has_bus_clk_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .ft_deviation = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .offset = 187744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .scale = 672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .calibrate = sun50i_h6_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .init = sun50i_h6_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .irq_ack = sun50i_h6_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .calc_temp = sun8i_ths_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const struct ths_thermal_chip sun50i_h5_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .sensor_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .has_mod_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .has_bus_clk_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .temp_data_base = SUN8I_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .calibrate = sun8i_h3_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .init = sun8i_h3_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .irq_ack = sun8i_h3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .calc_temp = sun50i_h5_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct ths_thermal_chip sun50i_h6_ths = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .sensor_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .has_bus_clk_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .ft_deviation = 7000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .offset = 187744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .scale = 672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .calibrate = sun50i_h6_ths_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .init = sun50i_h6_thermal_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .irq_ack = sun50i_h6_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .calc_temp = sun8i_ths_calc_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct of_device_id of_ths_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MODULE_DEVICE_TABLE(of, of_ths_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static struct platform_driver ths_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .probe = sun8i_ths_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .remove = sun8i_ths_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "sun8i-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .of_match_table = of_ths_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) module_platform_driver(ths_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SOC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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